From 70ea186dd4ba56f05770cc0652df0e3aecf58c82 Mon Sep 17 00:00:00 2001 From: Janek van Oirschot Date: Tue, 4 Mar 2025 13:17:28 +0000 Subject: [PATCH 1/3] [AMDGPU] Masked load vectortype test --- .../CodeGen/AMDGPU/masked-load-vectortypes.ll | 255 ++++++++++++++++++ 1 file changed, 255 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll diff --git a/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll new file mode 100644 index 0000000000000..55da31eea05b4 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll @@ -0,0 +1,255 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck --check-prefix=GFX942 %s + +define <2 x i32> @masked_load_v2i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_v2i32: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-NEXT: v_mov_b32_e32 v1, v0 +; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-NEXT: s_cbranch_execz .LBB0_2 +; GFX942-NEXT: ; %bb.1: ; %cond.load +; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] +; GFX942-NEXT: .LBB0_2: +; GFX942-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +entry: + %0 = insertelement <2 x i1> poison, i1 %mask, i64 0 + %1 = shufflevector <2 x i1> %0, <2 x i1> poison, <2 x i32> zeroinitializer + %result = tail call <2 x i32> @llvm.masked.load.v2i32.p1(ptr addrspace(1) %ptr, i32 2, <2 x i1> %1, <2 x i32> zeroinitializer) + ret <2 x i32> %result +} + +define <4 x i32> @masked_load_v4i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_v4i32: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-NEXT: v_mov_b32_e32 v1, v0 +; GFX942-NEXT: v_mov_b32_e32 v2, v0 +; GFX942-NEXT: v_mov_b32_e32 v3, v0 +; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-NEXT: s_cbranch_execz .LBB1_2 +; GFX942-NEXT: ; %bb.1: ; %cond.load +; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX942-NEXT: .LBB1_2: +; GFX942-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +entry: + %0 = insertelement <4 x i1> poison, i1 %mask, i64 0 + %1 = shufflevector <4 x i1> %0, <4 x i1> poison, <4 x i32> zeroinitializer + %result = tail call <4 x i32> @llvm.masked.load.v4i32.p1(ptr addrspace(1) %ptr, i32 4, <4 x i1> %1, <4 x i32> zeroinitializer) + ret <4 x i32> %result +} + +define <4 x float> @masked_load_v4f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_v4f32: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-NEXT: v_mov_b32_e32 v1, v0 +; GFX942-NEXT: v_mov_b32_e32 v2, v0 +; GFX942-NEXT: v_mov_b32_e32 v3, v0 +; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-NEXT: s_cbranch_execz .LBB2_2 +; GFX942-NEXT: ; %bb.1: ; %cond.load +; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX942-NEXT: .LBB2_2: +; GFX942-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +entry: + %0 = insertelement <4 x i1> poison, i1 %mask, i64 0 + %1 = shufflevector <4 x i1> %0, <4 x i1> poison, <4 x i32> zeroinitializer + %result = tail call <4 x float> @llvm.masked.load.v4f32.p1(ptr addrspace(1) %ptr, i32 4, <4 x i1> %1, <4 x float> zeroinitializer) + ret <4 x float> %result +} + +define <8 x i32> @masked_load_v8i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_v8i32: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-NEXT: v_mov_b32_e32 v1, v0 +; GFX942-NEXT: v_mov_b32_e32 v2, v0 +; GFX942-NEXT: v_mov_b32_e32 v3, v0 +; GFX942-NEXT: v_mov_b32_e32 v4, v0 +; GFX942-NEXT: v_mov_b32_e32 v5, v0 +; GFX942-NEXT: v_mov_b32_e32 v6, v0 +; GFX942-NEXT: v_mov_b32_e32 v7, v0 +; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-NEXT: s_cbranch_execz .LBB3_2 +; GFX942-NEXT: ; %bb.1: ; %cond.load +; GFX942-NEXT: global_load_dwordx4 v[4:7], v0, s[0:1] offset:16 +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX942-NEXT: .LBB3_2: +; GFX942-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +entry: + %0 = insertelement <8 x i1> poison, i1 %mask, i64 0 + %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x i32> zeroinitializer) + ret <8 x i32> %result +} + +define <8 x float> @masked_load_v8f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_v8f32: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-NEXT: v_mov_b32_e32 v1, v0 +; GFX942-NEXT: v_mov_b32_e32 v2, v0 +; GFX942-NEXT: v_mov_b32_e32 v3, v0 +; GFX942-NEXT: v_mov_b32_e32 v4, v0 +; GFX942-NEXT: v_mov_b32_e32 v5, v0 +; GFX942-NEXT: v_mov_b32_e32 v6, v0 +; GFX942-NEXT: v_mov_b32_e32 v7, v0 +; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-NEXT: s_cbranch_execz .LBB4_2 +; GFX942-NEXT: ; %bb.1: ; %cond.load +; GFX942-NEXT: global_load_dwordx4 v[4:7], v0, s[0:1] offset:16 +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX942-NEXT: .LBB4_2: +; GFX942-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +entry: + %0 = insertelement <8 x i1> poison, i1 %mask, i64 0 + %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x float> @llvm.masked.load.v8f32.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x float> zeroinitializer) + ret <8 x float> %result +} + +define <8 x i16> @masked_load_v8i16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_v8i16: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-NEXT: v_mov_b32_e32 v1, v0 +; GFX942-NEXT: v_mov_b32_e32 v2, v0 +; GFX942-NEXT: v_mov_b32_e32 v3, v0 +; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-NEXT: s_cbranch_execz .LBB5_2 +; GFX942-NEXT: ; %bb.1: ; %cond.load +; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX942-NEXT: .LBB5_2: +; GFX942-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +entry: + %0 = insertelement <8 x i1> poison, i1 %mask, i16 0 + %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x i16> @llvm.masked.load.v8i16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x i16> zeroinitializer) + ret <8 x i16> %result +} + +define <8 x half> @masked_load_v8f16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_v8f16: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-NEXT: v_mov_b32_e32 v1, v0 +; GFX942-NEXT: v_mov_b32_e32 v2, v0 +; GFX942-NEXT: v_mov_b32_e32 v3, v0 +; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-NEXT: s_cbranch_execz .LBB6_2 +; GFX942-NEXT: ; %bb.1: ; %cond.load +; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX942-NEXT: .LBB6_2: +; GFX942-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +entry: + %0 = insertelement <8 x i1> poison, i1 %mask, i16 0 + %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x half> @llvm.masked.load.v8f16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x half> zeroinitializer) + ret <8 x half> %result +} + +define <8 x bfloat> @masked_load_v8bf16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_v8bf16: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-NEXT: v_mov_b32_e32 v1, v0 +; GFX942-NEXT: v_mov_b32_e32 v2, v0 +; GFX942-NEXT: v_mov_b32_e32 v3, v0 +; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-NEXT: s_cbranch_execz .LBB7_2 +; GFX942-NEXT: ; %bb.1: ; %cond.load +; GFX942-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] +; GFX942-NEXT: .LBB7_2: +; GFX942-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +entry: + %0 = insertelement <8 x i1> poison, i1 %mask, i32 0 + %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x bfloat> @llvm.masked.load.v8bf16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x bfloat> zeroinitializer) + ret <8 x bfloat> %result +} + +define <16 x i8> @masked_load_v16i8(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_v16i8: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v16, 0 +; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GFX942-NEXT: v_mov_b32_e32 v17, v16 +; GFX942-NEXT: v_mov_b32_e32 v18, v16 +; GFX942-NEXT: v_mov_b32_e32 v19, v16 +; GFX942-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-NEXT: s_cbranch_execz .LBB8_2 +; GFX942-NEXT: ; %bb.1: ; %cond.load +; GFX942-NEXT: global_load_dwordx4 v[16:19], v16, s[0:1] +; GFX942-NEXT: .LBB8_2: +; GFX942-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: v_lshrrev_b64 v[20:21], 24, v[16:17] +; GFX942-NEXT: v_lshrrev_b64 v[22:23], 24, v[18:19] +; GFX942-NEXT: v_lshrrev_b32_e32 v1, 8, v16 +; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v16 +; GFX942-NEXT: v_lshrrev_b32_e32 v5, 8, v17 +; GFX942-NEXT: v_lshrrev_b32_e32 v6, 16, v17 +; GFX942-NEXT: v_lshrrev_b32_e32 v7, 24, v17 +; GFX942-NEXT: v_lshrrev_b32_e32 v9, 8, v18 +; GFX942-NEXT: v_lshrrev_b32_e32 v10, 16, v18 +; GFX942-NEXT: v_lshrrev_b32_e32 v13, 8, v19 +; GFX942-NEXT: v_lshrrev_b32_e32 v14, 16, v19 +; GFX942-NEXT: v_lshrrev_b32_e32 v15, 24, v19 +; GFX942-NEXT: v_mov_b32_e32 v0, v16 +; GFX942-NEXT: v_mov_b32_e32 v3, v20 +; GFX942-NEXT: v_mov_b32_e32 v4, v17 +; GFX942-NEXT: v_mov_b32_e32 v8, v18 +; GFX942-NEXT: v_mov_b32_e32 v11, v22 +; GFX942-NEXT: v_mov_b32_e32 v12, v19 +; GFX942-NEXT: s_setpc_b64 s[30:31] +entry: + %0 = insertelement <16 x i1> poison, i1 %mask, i32 0 + %1 = shufflevector <16 x i1> %0, <16 x i1> poison, <16 x i32> zeroinitializer + %result = tail call <16 x i8> @llvm.masked.load.v16i8.p1(ptr addrspace(1) %ptr, i32 4, <16 x i1> %1, <16 x i8> zeroinitializer) + ret <16 x i8> %result +} From bd9b711385be75ff03e8cd306af39fce2f647a39 Mon Sep 17 00:00:00 2001 From: Janek van Oirschot Date: Tue, 4 Mar 2025 13:40:22 +0000 Subject: [PATCH 2/3] Some forgotten requested changes to test --- .../CodeGen/AMDGPU/masked-load-vectortypes.ll | 90 +++++++++---------- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll index 55da31eea05b4..1441ca3295a22 100644 --- a/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll +++ b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck --check-prefix=GFX942 %s -define <2 x i32> @masked_load_v2i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_v2i32: +define <2 x i32> @masked_load_ptr1_mask_v2i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_ptr1_mask_v2i32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -18,14 +18,14 @@ define <2 x i32> @masked_load_v2i32(ptr addrspace(1) inreg nocapture readonly %p ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] entry: - %0 = insertelement <2 x i1> poison, i1 %mask, i64 0 - %1 = shufflevector <2 x i1> %0, <2 x i1> poison, <2 x i32> zeroinitializer - %result = tail call <2 x i32> @llvm.masked.load.v2i32.p1(ptr addrspace(1) %ptr, i32 2, <2 x i1> %1, <2 x i32> zeroinitializer) + %partialmaskvec = insertelement <2 x i1> poison, i1 %mask, i64 0 + %maskvec = shufflevector <2 x i1> %partialmaskvec, <2 x i1> poison, <2 x i32> zeroinitializer + %result = tail call <2 x i32> @llvm.masked.load.v2i32.p1(ptr addrspace(1) %ptr, i32 2, <2 x i1> %maskvec, <2 x i32> zeroinitializer) ret <2 x i32> %result } -define <4 x i32> @masked_load_v4i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_v4i32: +define <4 x i32> @masked_load_ptr1_mask_v4i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_ptr1_mask_v4i32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -43,14 +43,14 @@ define <4 x i32> @masked_load_v4i32(ptr addrspace(1) inreg nocapture readonly %p ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] entry: - %0 = insertelement <4 x i1> poison, i1 %mask, i64 0 - %1 = shufflevector <4 x i1> %0, <4 x i1> poison, <4 x i32> zeroinitializer - %result = tail call <4 x i32> @llvm.masked.load.v4i32.p1(ptr addrspace(1) %ptr, i32 4, <4 x i1> %1, <4 x i32> zeroinitializer) + %partialmaskvec = insertelement <4 x i1> poison, i1 %mask, i64 0 + %maskvec = shufflevector <4 x i1> %partialmaskvec, <4 x i1> poison, <4 x i32> zeroinitializer + %result = tail call <4 x i32> @llvm.masked.load.v4i32.p1(ptr addrspace(1) %ptr, i32 4, <4 x i1> %maskvec, <4 x i32> zeroinitializer) ret <4 x i32> %result } -define <4 x float> @masked_load_v4f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_v4f32: +define <4 x float> @masked_load_ptr1_mask_v4f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_ptr1_mask_v4f32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -68,14 +68,14 @@ define <4 x float> @masked_load_v4f32(ptr addrspace(1) inreg nocapture readonly ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] entry: - %0 = insertelement <4 x i1> poison, i1 %mask, i64 0 - %1 = shufflevector <4 x i1> %0, <4 x i1> poison, <4 x i32> zeroinitializer - %result = tail call <4 x float> @llvm.masked.load.v4f32.p1(ptr addrspace(1) %ptr, i32 4, <4 x i1> %1, <4 x float> zeroinitializer) + %partialmaskvec = insertelement <4 x i1> poison, i1 %mask, i64 0 + %maskvec = shufflevector <4 x i1> %partialmaskvec, <4 x i1> poison, <4 x i32> zeroinitializer + %result = tail call <4 x float> @llvm.masked.load.v4f32.p1(ptr addrspace(1) %ptr, i32 4, <4 x i1> %maskvec, <4 x float> zeroinitializer) ret <4 x float> %result } -define <8 x i32> @masked_load_v8i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_v8i32: +define <8 x i32> @masked_load_ptr1_mask_v8i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_ptr1_mask_v8i32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -99,14 +99,14 @@ define <8 x i32> @masked_load_v8i32(ptr addrspace(1) inreg nocapture readonly %p ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] entry: - %0 = insertelement <8 x i1> poison, i1 %mask, i64 0 - %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer - %result = tail call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x i32> zeroinitializer) + %partialmaskvec = insertelement <8 x i1> poison, i1 %mask, i64 0 + %maskvec = shufflevector <8 x i1> %partialmaskvec, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %maskvec, <8 x i32> zeroinitializer) ret <8 x i32> %result } -define <8 x float> @masked_load_v8f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_v8f32: +define <8 x float> @masked_load_ptr1_mask_v8f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_ptr1_mask_v8f32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -130,14 +130,14 @@ define <8 x float> @masked_load_v8f32(ptr addrspace(1) inreg nocapture readonly ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] entry: - %0 = insertelement <8 x i1> poison, i1 %mask, i64 0 - %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer - %result = tail call <8 x float> @llvm.masked.load.v8f32.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x float> zeroinitializer) + %partialmaskvec = insertelement <8 x i1> poison, i1 %mask, i64 0 + %maskvec = shufflevector <8 x i1> %partialmaskvec, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x float> @llvm.masked.load.v8f32.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %maskvec, <8 x float> zeroinitializer) ret <8 x float> %result } -define <8 x i16> @masked_load_v8i16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_v8i16: +define <8 x i16> @masked_load_ptr1_mask_v8i16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_ptr1_mask_v8i16: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -155,14 +155,14 @@ define <8 x i16> @masked_load_v8i16(ptr addrspace(1) inreg nocapture readonly %p ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] entry: - %0 = insertelement <8 x i1> poison, i1 %mask, i16 0 - %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer - %result = tail call <8 x i16> @llvm.masked.load.v8i16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x i16> zeroinitializer) + %partialmaskvec = insertelement <8 x i1> poison, i1 %mask, i16 0 + %maskvec = shufflevector <8 x i1> %partialmaskvec, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x i16> @llvm.masked.load.v8i16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %maskvec, <8 x i16> zeroinitializer) ret <8 x i16> %result } -define <8 x half> @masked_load_v8f16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_v8f16: +define <8 x half> @masked_load_ptr1_mask_v8f16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_ptr1_mask_v8f16: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -180,14 +180,14 @@ define <8 x half> @masked_load_v8f16(ptr addrspace(1) inreg nocapture readonly % ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] entry: - %0 = insertelement <8 x i1> poison, i1 %mask, i16 0 - %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer - %result = tail call <8 x half> @llvm.masked.load.v8f16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x half> zeroinitializer) + %partialmaskvec = insertelement <8 x i1> poison, i1 %mask, i16 0 + %maskvec = shufflevector <8 x i1> %partialmaskvec, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x half> @llvm.masked.load.v8f16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %maskvec, <8 x half> zeroinitializer) ret <8 x half> %result } -define <8 x bfloat> @masked_load_v8bf16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_v8bf16: +define <8 x bfloat> @masked_load_ptr1_mask_v8bf16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_ptr1_mask_v8bf16: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -205,14 +205,14 @@ define <8 x bfloat> @masked_load_v8bf16(ptr addrspace(1) inreg nocapture readonl ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] entry: - %0 = insertelement <8 x i1> poison, i1 %mask, i32 0 - %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer - %result = tail call <8 x bfloat> @llvm.masked.load.v8bf16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x bfloat> zeroinitializer) + %partialmaskvec = insertelement <8 x i1> poison, i1 %mask, i32 0 + %maskvec = shufflevector <8 x i1> %partialmaskvec, <8 x i1> poison, <8 x i32> zeroinitializer + %result = tail call <8 x bfloat> @llvm.masked.load.v8bf16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %maskvec, <8 x bfloat> zeroinitializer) ret <8 x bfloat> %result } -define <16 x i8> @masked_load_v16i8(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_v16i8: +define <16 x i8> @masked_load_ptr1_mask_v16i8(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: masked_load_ptr1_mask_v16i8: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -248,8 +248,8 @@ define <16 x i8> @masked_load_v16i8(ptr addrspace(1) inreg nocapture readonly %p ; GFX942-NEXT: v_mov_b32_e32 v12, v19 ; GFX942-NEXT: s_setpc_b64 s[30:31] entry: - %0 = insertelement <16 x i1> poison, i1 %mask, i32 0 - %1 = shufflevector <16 x i1> %0, <16 x i1> poison, <16 x i32> zeroinitializer - %result = tail call <16 x i8> @llvm.masked.load.v16i8.p1(ptr addrspace(1) %ptr, i32 4, <16 x i1> %1, <16 x i8> zeroinitializer) + %partialmaskvec = insertelement <16 x i1> poison, i1 %mask, i32 0 + %maskvec = shufflevector <16 x i1> %partialmaskvec, <16 x i1> poison, <16 x i32> zeroinitializer + %result = tail call <16 x i8> @llvm.masked.load.v16i8.p1(ptr addrspace(1) %ptr, i32 4, <16 x i1> %maskvec, <16 x i8> zeroinitializer) ret <16 x i8> %result } From 27ac5b95b23f9759037b1b6dfbf828f0b828659a Mon Sep 17 00:00:00 2001 From: Janek van Oirschot Date: Thu, 6 Mar 2025 13:22:32 +0000 Subject: [PATCH 3/3] Rename functions --- .../CodeGen/AMDGPU/masked-load-vectortypes.ll | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll index 1441ca3295a22..c29e8d64a2838 100644 --- a/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll +++ b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck --check-prefix=GFX942 %s -define <2 x i32> @masked_load_ptr1_mask_v2i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_ptr1_mask_v2i32: +define <2 x i32> @uniform_masked_load_ptr1_mask_v2i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: uniform_masked_load_ptr1_mask_v2i32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -24,8 +24,8 @@ entry: ret <2 x i32> %result } -define <4 x i32> @masked_load_ptr1_mask_v4i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_ptr1_mask_v4i32: +define <4 x i32> @uniform_masked_load_ptr1_mask_v4i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: uniform_masked_load_ptr1_mask_v4i32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -49,8 +49,8 @@ entry: ret <4 x i32> %result } -define <4 x float> @masked_load_ptr1_mask_v4f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_ptr1_mask_v4f32: +define <4 x float> @uniform_masked_load_ptr1_mask_v4f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: uniform_masked_load_ptr1_mask_v4f32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -74,8 +74,8 @@ entry: ret <4 x float> %result } -define <8 x i32> @masked_load_ptr1_mask_v8i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_ptr1_mask_v8i32: +define <8 x i32> @uniform_masked_load_ptr1_mask_v8i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: uniform_masked_load_ptr1_mask_v8i32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -105,8 +105,8 @@ entry: ret <8 x i32> %result } -define <8 x float> @masked_load_ptr1_mask_v8f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_ptr1_mask_v8f32: +define <8 x float> @uniform_masked_load_ptr1_mask_v8f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: uniform_masked_load_ptr1_mask_v8f32: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -136,8 +136,8 @@ entry: ret <8 x float> %result } -define <8 x i16> @masked_load_ptr1_mask_v8i16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_ptr1_mask_v8i16: +define <8 x i16> @uniform_masked_load_ptr1_mask_v8i16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: uniform_masked_load_ptr1_mask_v8i16: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -161,8 +161,8 @@ entry: ret <8 x i16> %result } -define <8 x half> @masked_load_ptr1_mask_v8f16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_ptr1_mask_v8f16: +define <8 x half> @uniform_masked_load_ptr1_mask_v8f16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: uniform_masked_load_ptr1_mask_v8f16: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -186,8 +186,8 @@ entry: ret <8 x half> %result } -define <8 x bfloat> @masked_load_ptr1_mask_v8bf16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_ptr1_mask_v8bf16: +define <8 x bfloat> @uniform_masked_load_ptr1_mask_v8bf16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: uniform_masked_load_ptr1_mask_v8bf16: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0 @@ -211,8 +211,8 @@ entry: ret <8 x bfloat> %result } -define <16 x i8> @masked_load_ptr1_mask_v16i8(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { -; GFX942-LABEL: masked_load_ptr1_mask_v16i8: +define <16 x i8> @uniform_masked_load_ptr1_mask_v16i8(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) { +; GFX942-LABEL: uniform_masked_load_ptr1_mask_v16i8: ; GFX942: ; %bb.0: ; %entry ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_and_b32_e32 v0, 1, v0