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[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. #130302

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Merged
merged 1 commit into from
Mar 8, 2025
Merged

[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. #130302

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34 changes: 19 additions & 15 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -176,9 +176,12 @@ static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize,

// Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
// get register class. Used by SGPR only operands.
#define DECODE_OPERAND_REG_7(RegClass, OpWidth) \
#define DECODE_OPERAND_SREG_7(RegClass, OpWidth) \
DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)

#define DECODE_OPERAND_SREG_8(RegClass, OpWidth) \
DECODE_SrcOp(Decode##RegClass##RegisterClass, 8, OpWidth, Imm, false, 0)

// Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
// Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
Expand Down Expand Up @@ -270,20 +273,21 @@ DECODE_OPERAND_REG_8(VReg_384)
DECODE_OPERAND_REG_8(VReg_512)
DECODE_OPERAND_REG_8(VReg_1024)

DECODE_OPERAND_REG_7(SReg_32, OPW32)
DECODE_OPERAND_REG_7(SReg_32_XM0, OPW32)
DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32)
DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32)
DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32)
DECODE_OPERAND_REG_7(SReg_64, OPW64)
DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64)
DECODE_OPERAND_REG_7(SReg_64_XEXEC_XNULL, OPW64)
DECODE_OPERAND_REG_7(SReg_96, OPW96)
DECODE_OPERAND_REG_7(SReg_128, OPW128)
DECODE_OPERAND_REG_7(SReg_128_XNULL, OPW128)
DECODE_OPERAND_REG_7(SReg_256, OPW256)
DECODE_OPERAND_REG_7(SReg_256_XNULL, OPW256)
DECODE_OPERAND_REG_7(SReg_512, OPW512)
DECODE_OPERAND_SREG_7(SReg_32, OPW32)
DECODE_OPERAND_SREG_7(SReg_32_XM0, OPW32)
DECODE_OPERAND_SREG_7(SReg_32_XEXEC, OPW32)
DECODE_OPERAND_SREG_7(SReg_32_XM0_XEXEC, OPW32)
DECODE_OPERAND_SREG_7(SReg_32_XEXEC_HI, OPW32)
DECODE_OPERAND_SREG_7(SReg_64_XEXEC, OPW64)
DECODE_OPERAND_SREG_7(SReg_64_XEXEC_XNULL, OPW64)
DECODE_OPERAND_SREG_7(SReg_96, OPW96)
DECODE_OPERAND_SREG_7(SReg_128, OPW128)
DECODE_OPERAND_SREG_7(SReg_128_XNULL, OPW128)
DECODE_OPERAND_SREG_7(SReg_256, OPW256)
DECODE_OPERAND_SREG_7(SReg_256_XNULL, OPW256)
DECODE_OPERAND_SREG_7(SReg_512, OPW512)

DECODE_OPERAND_SREG_8(SReg_64, OPW64)

DECODE_OPERAND_REG_8(AGPR_32)
DECODE_OPERAND_REG_8(AReg_64)
Expand Down
3 changes: 3 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_sop1.txt
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Expand Up @@ -2548,6 +2548,9 @@
# GFX11: s_setpc_b64 vcc ; encoding: [0x6a,0x48,0x80,0xbe]
0x6a,0x48,0x80,0xbe

# GFX11: s_setpc_b64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe]
0xcb,0x48,0xf5,0xbe
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@arsenm arsenm Mar 7, 2025

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Maybe test with more operand bit widths? Or I guess only SReg_64 changed?

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@kosarev kosarev Mar 8, 2025

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Yes, it's just SReg_64. I hope to have to time to check other cases more thoroughly, but we need this s_setpc fix as a matter of urgency.


# GFX11: s_sext_i32_i16 exec_hi, s1 ; encoding: [0x01,0x0f,0xff,0xbe]
0x01,0x0f,0xff,0xbe

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3 changes: 3 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -3267,6 +3267,9 @@
# GFX12: s_setpc_b64 vcc ; encoding: [0x6a,0x48,0x80,0xbe]
0x6a,0x48,0x80,0xbe

# GFX12: s_setpc_b64 -11/*Invalid immediate*/ ; encoding: [0xf5,0x48,0x80,0xbe]
0xcb,0x48,0xf5,0xbe

# GFX12: s_sext_i32_i16 exec_hi, s1 ; encoding: [0x01,0x0f,0xff,0xbe]
0x01,0x0f,0xff,0xbe

Expand Down
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