From f67dc021c2db77aa7436eb6c5dde6d7c3e6648ef Mon Sep 17 00:00:00 2001 From: Kostas Alvertis Date: Mon, 10 Mar 2025 19:22:00 +0000 Subject: [PATCH 1/3] To fix violations of code conventions --- .../Target/PowerPC/PPCTargetTransformInfo.cpp | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 26e9b4b9facec..95b114f800fbb 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -457,16 +457,15 @@ unsigned PPCTTIImpl::getNumberOfRegisters(unsigned ClassID) const { unsigned PPCTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const { if (Vector) return ST->hasVSX() ? VSXRC : VRRC; - else if (Ty && (Ty->getScalarType()->isFloatTy() || + if (Ty && (Ty->getScalarType()->isFloatTy() || Ty->getScalarType()->isDoubleTy())) return ST->hasVSX() ? VSXRC : FPRRC; - else if (Ty && (Ty->getScalarType()->isFP128Ty() || + if (Ty && (Ty->getScalarType()->isFP128Ty() || Ty->getScalarType()->isPPC_FP128Ty())) return VRRC; - else if (Ty && Ty->getScalarType()->isHalfTy()) + if (Ty && Ty->getScalarType()->isHalfTy()) return VSXRC; - else - return GPRRC; + return GPRRC; } const char* PPCTTIImpl::getRegisterClassName(unsigned ClassID) const { @@ -695,7 +694,7 @@ InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, return Cost; - } else if (Val->getScalarType()->isIntegerTy()) { + } if (Val->getScalarType()->isIntegerTy()) { unsigned EltSize = Val->getScalarSizeInBits(); // Computing on 1 bit values requires extra mask or compare operations. unsigned MaskCostForOneBitSize = (VecMaskCost && EltSize == 1) ? 1 : 0; @@ -709,7 +708,7 @@ InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (ISD == ISD::INSERT_VECTOR_ELT) { if (ST->hasP10Vector()) return CostFactor + MaskCostForIdx; - else if (Index != -1U) + if (Index != -1U) return 2 * CostFactor; } else if (ISD == ISD::EXTRACT_VECTOR_ELT) { // It's an extract. Maybe we can do a cheap move-from VSR. @@ -717,7 +716,7 @@ InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, // P9 has both mfvsrd and mfvsrld for 64 bit integer. if (EltSize == 64 && Index != -1U) return 1; - else if (EltSize == 32) { + if (EltSize == 32) { unsigned MfvsrwzIndex = ST->isLittleEndian() ? 2 : 1; if (Index == MfvsrwzIndex) return 1; @@ -960,8 +959,7 @@ bool PPCTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1, C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) < std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost); - else - return TargetTransformInfoImplBase::isLSRCostLess(C1, C2); + return TargetTransformInfoImplBase::isLSRCostLess(C1, C2); } bool PPCTTIImpl::isNumRegsMajorCostOfLSR() { From 330e819db072178ac2686bd998475b4c40f2c0c4 Mon Sep 17 00:00:00 2001 From: Kostas Alvertis Date: Mon, 10 Mar 2025 20:15:32 +0000 Subject: [PATCH 2/3] clang-tidy naming conventions --- .../Target/PowerPC/PPCTargetTransformInfo.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 95b114f800fbb..bfd2c383df2d3 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -112,8 +112,8 @@ PPCTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { // Check that all of the elements are integer constants or undefs. bool AllEltsOk = true; - for (unsigned i = 0; i != 16; ++i) { - Constant *Elt = Mask->getAggregateElement(i); + for (unsigned I = 0; I != 16; ++I) { + Constant *Elt = Mask->getAggregateElement(I); if (!Elt || !(isa(Elt) || isa(Elt))) { AllEltsOk = false; break; @@ -132,11 +132,11 @@ PPCTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { Value *ExtractedElts[32]; memset(ExtractedElts, 0, sizeof(ExtractedElts)); - for (unsigned i = 0; i != 16; ++i) { - if (isa(Mask->getAggregateElement(i))) + for (unsigned I = 0; I != 16; ++I) { + if (isa(Mask->getAggregateElement(I))) continue; unsigned Idx = - cast(Mask->getAggregateElement(i))->getZExtValue(); + cast(Mask->getAggregateElement(I))->getZExtValue(); Idx &= 31; // Match the hardware behavior. if (DL.isLittleEndian()) Idx = 31 - Idx; @@ -150,7 +150,7 @@ PPCTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { // Insert this value into the result vector. Result = IC.Builder.CreateInsertElement(Result, ExtractedElts[Idx], - IC.Builder.getInt32(i)); + IC.Builder.getInt32(I)); } return CastInst::Create(Instruction::BitCast, Result, II.getType()); } @@ -846,9 +846,9 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, // stores, loads are expanded using the vector-load + permutation sequence, // which is much less expensive). if (Src->isVectorTy() && Opcode == Instruction::Store) - for (int i = 0, e = cast(Src)->getNumElements(); i < e; - ++i) - Cost += getVectorInstrCost(Instruction::ExtractElement, Src, CostKind, i, + for (int I = 0, E = cast(Src)->getNumElements(); I < E; + ++I) + Cost += getVectorInstrCost(Instruction::ExtractElement, Src, CostKind, I, nullptr, nullptr); return Cost; From 36facc2590f573330df5e0c5d7062ccc324e8699 Mon Sep 17 00:00:00 2001 From: Kostas Alvertis Date: Mon, 10 Mar 2025 22:00:48 +0000 Subject: [PATCH 3/3] clang-format --- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index bfd2c383df2d3..2a5af3e50af26 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -457,15 +457,15 @@ unsigned PPCTTIImpl::getNumberOfRegisters(unsigned ClassID) const { unsigned PPCTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const { if (Vector) return ST->hasVSX() ? VSXRC : VRRC; - if (Ty && (Ty->getScalarType()->isFloatTy() || - Ty->getScalarType()->isDoubleTy())) + if (Ty && + (Ty->getScalarType()->isFloatTy() || Ty->getScalarType()->isDoubleTy())) return ST->hasVSX() ? VSXRC : FPRRC; if (Ty && (Ty->getScalarType()->isFP128Ty() || - Ty->getScalarType()->isPPC_FP128Ty())) + Ty->getScalarType()->isPPC_FP128Ty())) return VRRC; if (Ty && Ty->getScalarType()->isHalfTy()) return VSXRC; - return GPRRC; + return GPRRC; } const char* PPCTTIImpl::getRegisterClassName(unsigned ClassID) const { @@ -693,8 +693,8 @@ InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, return 0; return Cost; - - } if (Val->getScalarType()->isIntegerTy()) { + } + if (Val->getScalarType()->isIntegerTy()) { unsigned EltSize = Val->getScalarSizeInBits(); // Computing on 1 bit values requires extra mask or compare operations. unsigned MaskCostForOneBitSize = (VecMaskCost && EltSize == 1) ? 1 : 0; @@ -959,7 +959,7 @@ bool PPCTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1, C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) < std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost); - return TargetTransformInfoImplBase::isLSRCostLess(C1, C2); + return TargetTransformInfoImplBase::isLSRCostLess(C1, C2); } bool PPCTTIImpl::isNumRegsMajorCostOfLSR() {