From 2ceeb95fa065cf5f2d52899d7fdf99c383628235 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 11 Mar 2025 12:27:14 -0700 Subject: [PATCH] [RISCV] FeatureVendorXwchc should imply FeatureStdExtZca. If we don't do this the binary emission won't set the compressed flag in the ELF header and won't emit alignment NOPs for R_RISCV_ALIGN correctly to support the existence of 2 byte instructions in the stream. --- llvm/lib/Target/RISCV/RISCVFeatures.td | 3 ++- llvm/test/CodeGen/RISCV/attributes.ll | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 544ad14266183..21119f624339c 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1281,7 +1281,8 @@ def HasVendorXMIPSLSP def FeatureVendorXwchc : RISCVExtension<2, 2, - "WCH/QingKe additional compressed opcodes">; + "WCH/QingKe additional compressed opcodes", + [FeatureStdExtZca]>; def HasVendorXwchc : Predicate<"Subtarget->hasVendorXwchc()">, AssemblerPredicate<(all_of FeatureVendorXwchc), diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index eaf54f879df17..5d4d96a52a0fd 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -402,7 +402,7 @@ ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0" ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0" ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0" -; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2" +; RV32XWCHC: .attribute 5, "rv32i2p1_zca1p0_xwchc2p2" ; RV32XQCCMP: .attribute 5, "rv32i2p1_zca1p0_xqccmp0p1" ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p4" ; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3"