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[RISCV] Add combine for shadd family of instructions. #130829

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Merged
merged 10 commits into from
Mar 31, 2025
Merged

[RISCV] Add combine for shadd family of instructions. #130829

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df5bcbf
[RISCV] Add combine for shadd family of instructions.
stefanp-synopsys Mar 11, 2025
38cfa79
Simplified the code as per comments.
stefanp-synopsys Mar 12, 2025
b60ccb8
Fixed a number of nits and added SDPatternMatch
stefanp-synopsys Mar 13, 2025
d452f5d
Fix clang-format.
stefanp-synopsys Mar 13, 2025
107d3d0
Figured out why the test case started failing and fixed it.
stefanp-synopsys Mar 14, 2025
30e5845
Fixed the issues with SDPatternMatch use.
stefanp-synopsys Mar 17, 2025
373f2a8
Fix formatting.
stefanp-synopsys Mar 17, 2025
c76c64e
Added an assert and removed the commutative from the shift.
stefanp-synopsys Mar 17, 2025
a335458
Renamed the helper function to combineShlAddIAddImpl and added all of…
stefanp-synopsys Mar 18, 2025
c54ae87
Added more testcases and fixed the signed / unsigned issue.
stefanp-synopsys Mar 18, 2025
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34 changes: 15 additions & 19 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,6 @@
#include <optional>

using namespace llvm;
using namespace llvm::PatternMatch;

#define DEBUG_TYPE "riscv-lower"

Expand Down Expand Up @@ -14318,35 +14317,36 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
// or 3.
static bool checkAddiForShift(SDValue AddI, int64_t &AddConst,
int64_t &ShlConst) {
using namespace llvm::SDPatternMatch;
// Based on testing it seems that performance degrades if the ADDI has
// more than 2 uses.
if (AddI->use_size() > 2)
return false;

auto *AddConstNode = dyn_cast<ConstantSDNode>(AddI->getOperand(1));
if (!AddConstNode)
return false;
APInt AddVal;
SDValue SHLVal;
sd_match(AddI, m_Add(m_Value(SHLVal), m_ConstInt(AddVal)));

SDValue SHLVal = AddI->getOperand(0);
if (SHLVal->getOpcode() != ISD::SHL)
APInt VShift;
if (!sd_match(SHLVal, m_c_BinOp(ISD::SHL, m_Value(), m_ConstInt(VShift))))
return false;

auto *ShiftNode = dyn_cast<ConstantSDNode>(SHLVal->getOperand(1));
if (!ShiftNode)
if (VShift.slt(1) || VShift.sgt(3))
return false;

if (ShiftNode->getSExtValue() < 1 || ShiftNode->getSExtValue() > 3)
return false;

ShlConst = ShiftNode->getSExtValue();
AddConst = AddConstNode->getSExtValue();
// Set the values at the end when we know that the function will return
// true.
ShlConst = VShift.getSExtValue();
AddConst = AddVal.getSExtValue();
return true;
}

// Optimize (add (add (shl x, c0), c1), y) ->
// (ADDI (SH*ADD y, x), c1), if c0 equals to [1|2|3].
static SDValue combineShlAddIAdd(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
using namespace llvm::SDPatternMatch;

// Perform this optimization only in the zba extension.
if (!ReassocShlAddiAdd || !Subtarget.hasStdExtZba())
return SDValue();
Expand All @@ -14362,12 +14362,8 @@ static SDValue combineShlAddIAdd(SDNode *N, SelectionDAG &DAG,

SDValue AddI = N->getOperand(0);
SDValue Other = N->getOperand(1);
bool LHSIsAddI = SDPatternMatch::sd_match(
AddI, SDPatternMatch::m_Add(SDPatternMatch::m_Value(),
SDPatternMatch::m_ConstInt()));
bool RHSIsAddI = SDPatternMatch::sd_match(
Other, SDPatternMatch::m_Add(SDPatternMatch::m_Value(),
SDPatternMatch::m_ConstInt()));
bool LHSIsAddI = sd_match(AddI, m_Add(m_Value(), m_ConstInt()));
bool RHSIsAddI = sd_match(Other, m_Add(m_Value(), m_ConstInt()));
int64_t AddConst = 0;
int64_t ShlConst = 0;

Expand Down