[RISCV] Xqciint SystemRegs, Final Assembly Insts #130867

lenary · 2025-03-12T00:14:43Z

This adds the Xqciint system registers from the Xqci-0.7 spec, as well as two leftover instructions: qc.c.mret and qc.c.mnret

This adds the Xqciint system registers from the Xqci-0.7 spec, as well as two leftover instructions: `qc.c.mret` and `qc.c.mnret` Co-authored-by: Sudharsan Veeravalli <[email protected]>

llvmbot · 2025-03-12T00:15:15Z

@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-mc

Author: Sam Elliott (lenary)

Changes

This adds the Xqciint system registers from the Xqci-0.7 spec, as well as two leftover instructions: qc.c.mret and qc.c.mnret

Patch is 32.11 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/130867.diff

6 Files Affected:

(modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+33-26)
(modified) llvm/lib/Target/RISCV/RISCVSystemOperands.td (+31)
(added) llvm/test/MC/RISCV/xqciint-csrs-invalid.s (+196)
(added) llvm/test/MC/RISCV/xqciint-csrs-valid.s (+454)
(modified) llvm/test/MC/RISCV/xqciint-invalid.s (+14)
(modified) llvm/test/MC/RISCV/xqciint-valid.s (+10)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 32cfade8697b9..d639859206d0e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -545,38 +545,45 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 } // Predicates = [HasVendorXqcicm, IsRV32]
 
 let Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1 in {
-  let mayLoad = 0, mayStore = 0 in {
-  def QC_C_DIR : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd), (ins),
-                            "qc.c.dir", "$rd"> {
-    bits<5> rd;
 
-    let Inst{12} = 0b1;
-    let Inst{11-7} = rd;
-    let Inst{6-2} = 0b00000;
-  }
+let mayLoad = 0, mayStore = 0 in {
+def QC_C_DIR : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd), (ins),
+                          "qc.c.dir", "$rd"> {
+  bits<5> rd;
+
+  let Inst{12} = 0b1;
+  let Inst{11-7} = rd;
+  let Inst{6-2} = 0b00000;
+}
+
+def QC_SETINTI : QCIInt_IMM<0b0, "qc.setinti">;
+def QC_CLRINTI : QCIInt_IMM<0b1, "qc.clrinti">;
+
+def QC_C_EIR    : QCIRVInst16CI_RS1<0b00001, "qc.c.eir">;
+def QC_C_SETINT : QCIRVInst16CI_RS1<0b00010, "qc.c.setint">;
+def QC_C_CLRINT : QCIRVInst16CI_RS1<0b00011, "qc.c.clrint">;
 
-  def QC_SETINTI : QCIInt_IMM<0b0, "qc.setinti">;
-  def QC_CLRINTI : QCIInt_IMM<0b1, "qc.clrinti">;
+def QC_C_DI     : QCIRVInst16CI_NONE<0b10110, "qc.c.di">;
+def QC_C_EI     : QCIRVInst16CI_NONE<0b10111, "qc.c.ei">;
 
-  def QC_C_EIR    : QCIRVInst16CI_RS1<0b00001, "qc.c.eir">;
-  def QC_C_SETINT : QCIRVInst16CI_RS1<0b00010, "qc.c.setint">;
-  def QC_C_CLRINT : QCIRVInst16CI_RS1<0b00011, "qc.c.clrint">;
+let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
+def QC_C_MRET   : QCIRVInst16CI_NONE<0b10010, "qc.c.mret">;
+def QC_C_MNRET  : QCIRVInst16CI_NONE<0b10011, "qc.c.mnret">;
+} // isBarrier = 1, isReturn = 1, isTerminator = 1
+} // mayLoad = 0, mayStore = 0
 
-  def QC_C_DI     : QCIRVInst16CI_NONE<0b10110, "qc.c.di">;
-  def QC_C_EI     : QCIRVInst16CI_NONE<0b10111, "qc.c.ei">;
-  } // mayLoad = 0, mayStore = 0
+let mayLoad = 0, mayStore = 1,
+  Uses = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31],
+  Defs = [X2, X8] in {
+def QC_C_MIENTER      : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">;
+def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">;
+} // mayLoad = 1, mayStore = 1, Uses = [...], Defs = [...]
 
-  let mayLoad = 0, mayStore = 1,
-    Uses = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31],
-    Defs = [X2, X8] in {
-  def QC_C_MIENTER      : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">;
-  def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">;
-  } // mayLoad = 1, mayStore = 1, Uses = [...], Defs = [...]
+let mayLoad = 1, mayStore = 0, isBarrier = 1, isReturn = 1, isTerminator = 1,
+  Uses = [X2],
+  Defs = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31] in
+def QC_C_MILEAVERET   : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
 
-  let mayLoad = 1, mayStore = 0, isBarrier = 1, isReturn = 1, isTerminator = 1,
-    Uses = [X2],
-    Defs = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31] in
-  def QC_C_MILEAVERET   : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
 } // Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1
 
 let Predicates = [HasVendorXqcilo, IsRV32] in {
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 5b46e7df25fc8..4c7db896e3380 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -471,3 +471,34 @@ def : SysReg<"sctrstatus", 0x14f>;
 def : SysReg<"sctrdepth", 0x15f>;
 def : SysReg<"vsctrctl", 0x24e>;
 def : SysReg<"mctrctl", 0x34e>;
+
+//===-----------------------------------------------
+// Vendor CSRs
+//===-----------------------------------------------
+
+// Xqciint
+let FeaturesRequired = [{ {RISCV::FeatureVendorXqciint} }], isRV32Only = 1 in {
+def : SysReg<"qc.mmcr", 0x7C0>;
+def : SysReg<"qc.mnepc", 0x7C1>;
+def : SysReg<"qc.mncause", 0x7C2>;
+def : SysReg<"qc.mntvec", 0x7C3>;
+def : SysReg<"qc.mstktopaddr", 0x7C4>;
+def : SysReg<"qc.mstkbottomaddr", 0x7C5>;
+def : SysReg<"qc.mthreadptr", 0x7C8>;
+def : SysReg<"qc.mcause", 0x7C9>;
+
+foreach i = 0 - 7 in {
+  def : SysReg<"qc.mclicip" # i, !add(0x7F0, i)>;
+  def : SysReg<"qc.mclicie" # i, !add(0x7F8, i)>;
+}
+
+foreach i = 0 - 31 in {
+  def : SysReg<"qc.mclicilvl" # !if(!lt(i, 10), "0", "") # i, 
+               !add(0xBC0, i)>;
+}
+
+foreach i = 0 - 3 in {
+  def : SysReg<"qc.mwpstartaddr" # i, !add(0x7D0, i)>;
+  def : SysReg<"qc.mwpendaddr" # i,   !add(0x7D4, i)>;
+}
+} // FeatureVendorXqciint, isRV32Only
diff --git a/llvm/test/MC/RISCV/xqciint-csrs-invalid.s b/llvm/test/MC/RISCV/xqciint-csrs-invalid.s
new file mode 100644
index 0000000000000..02244e65194e1
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqciint-csrs-invalid.s
@@ -0,0 +1,196 @@
+# Xqciint - Qualcomm uC Custom CSRs
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciint < %s 2>&1 \
+# RUN:         | FileCheck -check-prefixes=CHECK-FEATURE %s
+
+csrrs t2, qc.mmcr, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mmcr' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mnepc, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mnepc' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mncause, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mncause' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mntvec, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mntvec' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mstktopaddr, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstktopaddr' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mstkbottomaddr, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstkbottomaddr' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mthreadptr, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mthreadptr' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mcause, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mcause' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip0, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip0' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip1, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip1' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip2, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip2' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip3, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip3' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip4, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip4' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip5, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip5' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip6, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip6' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip7, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip7' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie0, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie0' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie1, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie1' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie2, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie2' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie3, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie3' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie4, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie4' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie5, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie5' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie6, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie6' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie7, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie7' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl00, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl00' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl01, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl01' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl02, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl02' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl03, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl03' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl04, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl04' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl05, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl05' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl06, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl06' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl07, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl07' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl08, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl08' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl09, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl09' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl10, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl10' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl11, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl11' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl12, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl12' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl13, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl13' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl14, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl14' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl15, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl15' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl16, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl16' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl17, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl17' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl18, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl18' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl19, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl19' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl20, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl20' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl21, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl21' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl22, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl22' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl23, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl23' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl24, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl24' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl25, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl25' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl26, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl26' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl27, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl27' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl28, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl28' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl29, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl29' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl30, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl30' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl31, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl31' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpstartaddr0, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr0' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpstartaddr1, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr1' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpstartaddr2, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr2' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpstartaddr3, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr3' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpendaddr0, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr0' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpendaddr1, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr1' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpendaddr2, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr2' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpendaddr3, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr3' requires 'experimental-xqciint' to be enabled
+
diff --git a/llvm/test/MC/RISCV/xqciint-csrs-valid.s b/llvm/test/MC/RISCV/xqciint-csrs-valid.s
new file mode 100644
index 0000000000000..ed6ac13d8a7a7
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqciint-csrs-valid.s
@@ -0,0 +1,454 @@
+# Xqciint - Qualcomm uC Custom CSRs
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciint -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC  %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciint < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xqciint -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+csrrs t2, qc.mmcr, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
+// CHECK-INST: csrrs t2, qc.mmcr, zero
+csrrs t2, 0x7C0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
+// CHECK-INST: csrrs t2, qc.mmcr, zero
+
+csrrs t2, qc.mnepc, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
+// CHECK-INST: csrrs    t2, qc.mnepc, zero
+csrrs t2, 0x7C1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
+// CHECK-INST: csrrs    t2, qc.mnepc, zero
+
+csrrs t2, qc.mncause, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7c]
+// CHECK-INST: csrrs    t2, qc.mncause, zero
+csrrs t2, 0x7C2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7c]
+// CHECK-INST: csrrs    t2, qc.mncause, zero
+
+csrrs t2, qc.mntvec, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7c]
+// CHECK-INST: csrrs    t2, qc.mntvec, zero
+csrrs t2, 0x7C3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7c]
+// CHECK-INST: csrrs    t2, qc.mntvec, zero
+
+csrrs t2, qc.mstktopaddr, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7c]
+// CHECK-INST: csrrs    t2, qc.mstktopaddr, zero
+csrrs t2, 0x7C4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7c]
+// CHECK-INST: csrrs    t2, qc.mstktopaddr, zero
+
+csrrs t2, qc.mstkbottomaddr, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7c]
+// CHECK-INST: csrrs    t2, qc.mstkbottomaddr, zero
+csrrs t2, 0x7C5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7c]
+// CHECK-INST: csrrs    t2, qc.mstkbottomaddr, zero
+
+csrrs t2, qc.mthreadptr, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
+// CHECK-INST: csrrs    t2, qc.mthreadptr, zero
+csrrs t2, 0x7C8, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
+// CHECK-INST: csrrs    t2, qc.mthreadptr, zero
+
+csrrs t2, qc.mcause, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0x7c]
+// CHECK-INST: csrrs    t2, qc.mcause, zero
+csrrs t2, 0x7C9, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0x7c]
+// CHECK-INST: csrrs    t2, qc.mcause, zero
+
+csrrs t2, qc.mclicip0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip0, zero
+csrrs t2, 0x7F0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip0, zero
+
+csrrs t2, qc.mclicip1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip1, zero
+csrrs t2, 0x7F1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip1, zero
+
+csrrs t2, qc.mclicip2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip2, zero
+csrrs t2, 0x7F2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip2, zero
+
+csrrs t2, qc.mclicip3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip3, zero
+csrrs t2, 0x7F3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip3, zero
+
+csrrs t2, qc.mclicip4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip4, zero
+csrrs t2, 0x7F4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip4, zero
+
+csrrs t2, qc.mclicip5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip5, zero
+csrrs t2, 0x7F5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip5, zero
+
+csrrs t2, qc.mclicip6, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip6, zero
+csrrs t2, 0x7F6, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip6, zero
+
+csrrs t2, qc.mclicip7, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip7, zero
+csrrs t2, 0x7F7, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicip7, zero
+
+csrrs t2, qc.mclicie0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicie0, zero
+csrrs t2, 0x7F8, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicie0, zero
+
+csrrs t2, qc.mclicie1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicie1, zero
+csrrs t2, 0x7F9, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicie1, zero
+
+csrrs t2, qc.mclicie2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicie2, zero
+csrrs t2, 0x7FA, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicie2, zero
+
+csrrs t2, qc.mclicie3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x7f]
+// CHECK-INST: csrrs    t2, qc.mclicie3, zero
+csrrs t2, 0x7FB, zero
+// CHECK-ENC: encoding: [0xf3,0x2...
[truncated]

svs-quic · 2025-03-18T05:18:35Z

llvm/lib/Target/RISCV/RISCVSystemOperands.td

+// Xqciint
+let FeaturesRequired = [{ {RISCV::FeatureVendorXqciint} }], isRV32Only = 1 in {
+def : SysReg<"qc.mmcr", 0x7C0>;
+def : SysReg<"qc.mnepc", 0x7C1>;


The v0.7 spec removes these two.

From the version history:

Remove CSR registers qc.mncause, qc.mnep

Thanks, done

svs-quic

LGTM!

[RISCV] Xqciint SystemRegs, Final Assembly Insts

ee928c0

This adds the Xqciint system registers from the Xqci-0.7 spec, as well as two leftover instructions: `qc.c.mret` and `qc.c.mnret` Co-authored-by: Sudharsan Veeravalli <[email protected]>

lenary requested review from hchandel, svs-quic and topperc March 12, 2025 00:14

llvmbot added backend:RISC-V llvm:mc Machine (object) code labels Mar 12, 2025

svs-quic reviewed Mar 18, 2025

View reviewed changes

lenary added 2 commits March 18, 2025 10:30

Merge remote-tracking branch 'origin/main' into pr/xqciint-leftovers

bc7e221

fixup! [RISCV] Xqciint SystemRegs, Final Assembly Insts

9973d2e

svs-quic approved these changes Mar 22, 2025

View reviewed changes

lenary merged commit 8a13388 into llvm:main Mar 23, 2025
9 of 11 checks passed

lenary deleted the pr/xqciint-leftovers branch March 23, 2025 19:04

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[RISCV] Xqciint SystemRegs, Final Assembly Insts #130867

[RISCV] Xqciint SystemRegs, Final Assembly Insts #130867

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[RISCV] Xqciint SystemRegs, Final Assembly Insts #130867

[RISCV] Xqciint SystemRegs, Final Assembly Insts #130867

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lenary commented Mar 12, 2025

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llvmbot commented Mar 12, 2025 •

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