[AMDGPU][True16][CodeGen] enable true16 for more codegen test patch 1 #131206

broxigarchen · 2025-03-13T20:18:08Z

This is a NFC patch.

Enable true16 mode for more CodeGen tests

llvmbot · 2025-03-13T20:27:48Z

@llvm/pr-subscribers-backend-amdgpu

Author: Brox Chen (broxigarchen)

Changes

This is a NFC patch.

Enable true16 mode for more CodeGen tests

Patch is 871.65 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/131206.diff

18 Files Affected:

(modified) llvm/test/CodeGen/AMDGPU/abs_i16.ll (+42-20)
(modified) llvm/test/CodeGen/AMDGPU/add.v2i16.ll (+45-21)
(modified) llvm/test/CodeGen/AMDGPU/br_cc.f16.ll (+140-65)
(modified) llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll (+299-147)
(modified) llvm/test/CodeGen/AMDGPU/fabs.f16.ll (+114-53)
(modified) llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll (+742-350)
(modified) llvm/test/CodeGen/AMDGPU/fdiv.f16.ll (+575-276)
(modified) llvm/test/CodeGen/AMDGPU/fma.f16.ll (+334-123)
(modified) llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll (+184-94)
(modified) llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll (+184-94)
(modified) llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll (+1881-813)
(modified) llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll (+3230-928)
(modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll (+125-57)
(modified) llvm/test/CodeGen/AMDGPU/fneg.f16.ll (+129-61)
(modified) llvm/test/CodeGen/AMDGPU/fsub.f16.ll (+119-58)
(modified) llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll (+1000-486)
(modified) llvm/test/CodeGen/AMDGPU/imm16.ll (+539-243)
(modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll (+866-418)

diff --git a/llvm/test/CodeGen/AMDGPU/abs_i16.ll b/llvm/test/CodeGen/AMDGPU/abs_i16.ll
index 0ae2b4f549919..7633ba0eb4f9c 100644
--- a/llvm/test/CodeGen/AMDGPU/abs_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/abs_i16.ll
@@ -4,8 +4,10 @@
 ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
 ; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define i16 @abs_i16(i16 %arg) {
 ; GFX6-LABEL: abs_i16:
@@ -45,25 +47,45 @@ define i16 @abs_i16(i16 %arg) {
 ; GFX10-NEXT:    v_max_i16 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11-LABEL: abs_i16:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_sub_nc_u16 v1, 0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_max_i16 v0, v0, v1
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: abs_i16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_sub_nc_u16 v0.h, 0, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX12-LABEL: abs_i16:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT:    s_wait_expcnt 0x0
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    s_wait_bvhcnt 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_sub_nc_u16 v1, 0, v0
-; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT:    v_max_i16 v0, v0, v1
-; GFX12-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: abs_i16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_sub_nc_u16 v1, 0, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: abs_i16:
+; GFX12-TRUE16:       ; %bb.0:
+; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT:    v_sub_nc_u16 v0.h, 0, v0.l
+; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT:    v_max_i16 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: abs_i16:
+; GFX12-FAKE16:       ; %bb.0:
+; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT:    v_sub_nc_u16 v1, 0, v0
+; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT:    v_max_i16 v0, v0, v1
+; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
   ret i16 %res
 }
diff --git a/llvm/test/CodeGen/AMDGPU/add.v2i16.ll b/llvm/test/CodeGen/AMDGPU/add.v2i16.ll
index f94ec392ee55c..f6d3be1ee17e0 100644
--- a/llvm/test/CodeGen/AMDGPU/add.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/add.v2i16.ll
@@ -2,7 +2,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 ; FIXME: Need to handle non-uniform case for function below (load without gep).
 ; FIXME: VI or should be unnecessary
@@ -753,26 +754,49 @@ define amdgpu_kernel void @v_test_add_v2i16_zext_to_v2i64(ptr addrspace(1) %out,
 ; GFX10-NEXT:    global_store_dwordx4 v1, v[0:3], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: v_test_add_v2i16_zext_to_v2i64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3] glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    global_load_b32 v0, v0, s[4:5] glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_pk_add_u16 v0, v1, v0
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_alignbit_b32 v2, 0, v0, 16
-; GFX11-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v0, 0xffff, v0
-; GFX11-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: v_test_add_v2i16_zext_to_v2i64:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v0, s[2:3] glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v0, s[4:5] glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_pk_add_u16 v0, v1, v0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v2, 0, 16, v2
+; GFX11-TRUE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: v_test_add_v2i16_zext_to_v2i64:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v0, s[2:3] glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v0, s[4:5] glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_pk_add_u16 v0, v1, v0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_alignbit_b32 v2, 0, v0, 16
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    global_store_b128 v1, v[0:3], s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.out = getelementptr inbounds <2 x i64>, ptr addrspace(1) %out, i32 %tid
   %gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
diff --git a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
index 98832aaa3bc25..b27ad26cf97b9 100644
--- a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-FAKE16 %s
 
 define amdgpu_kernel void @br_cc_f16(
 ; SI-LABEL: br_cc_f16:
@@ -60,32 +61,62 @@ define amdgpu_kernel void @br_cc_f16(
 ; VI-NEXT:    buffer_store_short v1, off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: br_cc_f16:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_load_b64 s[8:9], s[4:5], 0x34
-; GFX11-NEXT:    s_mov_b32 s6, -1
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s10, s6
-; GFX11-NEXT:    s_mov_b32 s11, s7
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s4, s2
-; GFX11-NEXT:    s_mov_b32 s5, s3
-; GFX11-NEXT:    buffer_load_u16 v0, off, s[4:7], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    buffer_load_u16 v1, off, s[8:11], 0 glc dlc
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s2, s6
-; GFX11-NEXT:    s_mov_b32 s3, s7
-; GFX11-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX11-NEXT:    s_cbranch_vccnz .LBB0_2
-; GFX11-NEXT:  ; %bb.1: ; %one
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_endpgm
-; GFX11-NEXT:  .LBB0_2: ; %two
-; GFX11-NEXT:    buffer_store_b16 v1, off, s[0:3], 0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: br_cc_f16:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_load_b64 s[8:9], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s10, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s11, s7
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v0, off, s[4:7], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v1, off, s[8:11], 0 glc dlc
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s7
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v2.l, v2.h
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB0_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %one
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
+; GFX11-TRUE16-NEXT:  .LBB0_2: ; %two
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v1, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: br_cc_f16:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_load_b64 s[8:9], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s10, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s11, s7
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v0, off, s[4:7], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v1, off, s[8:11], 0 glc dlc
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s7
+; GFX11-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, v0, v1
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB0_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %one
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
+; GFX11-FAKE16-NEXT:  .LBB0_2: ; %two
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v1, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b) {
@@ -151,25 +182,47 @@ define amdgpu_kernel void @br_cc_f16_imm_a(
 ; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: br_cc_f16_imm_a:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s4, s2
-; GFX11-NEXT:    s_mov_b32 s5, s3
-; GFX11-NEXT:    buffer_load_u16 v0, off, s[4:7], 0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, 0.5, v0
-; GFX11-NEXT:    s_cbranch_vccnz .LBB1_2
-; GFX11-NEXT:  ; %bb.1: ; %one
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0x3800
-; GFX11-NEXT:  .LBB1_2: ; %two
-; GFX11-NEXT:    s_mov_b32 s2, s6
-; GFX11-NEXT:    s_mov_b32 s3, s7
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: br_cc_f16_imm_a:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v0, off, s[4:7], 0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, 0.5, v1.l
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB1_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %one
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0x3800
+; GFX11-TRUE16-NEXT:  .LBB1_2: ; %two
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s7
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: br_cc_f16_imm_a:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v0, off, s[4:7], 0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_nlt_f16_e32 vcc_lo, 0.5, v0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB1_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %one
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x3800
+; GFX11-FAKE16-NEXT:  .LBB1_2: ; %two
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s7
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %b) {
 entry:
@@ -235,25 +288,47 @@ define amdgpu_kernel void @br_cc_f16_imm_b(
 ; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: br_cc_f16_imm_b:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-NEXT:    s_mov_b32 s6, -1
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_mov_b32 s4, s2
-; GFX11-NEXT:    s_mov_b32 s5, s3
-; GFX11-NEXT:    buffer_load_u16 v0, off, s[4:7], 0
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, 0.5, v0
-; GFX11-NEXT:    s_cbranch_vccz .LBB2_2
-; GFX11-NEXT:  ; %bb.1: ; %two
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0x3800
-; GFX11-NEXT:  .LBB2_2: ; %one
-; GFX11-NEXT:    s_mov_b32 s2, s6
-; GFX11-NEXT:    s_mov_b32 s3, s7
-; GFX11-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-NEXT:    s_endpgm
+; GFX11-TRUE16-LABEL: br_cc_f16_imm_b:
+; GFX11-TRUE16:       ; %bb.0: ; %entry
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-TRUE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_mov_b32 s4, s2
+; GFX11-TRUE16-NEXT:    s_mov_b32 s5, s3
+; GFX11-TRUE16-NEXT:    buffer_load_u16 v0, off, s[4:7], 0
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, 0.5, v1.l
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB2_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %two
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0x3800
+; GFX11-TRUE16-NEXT:  .LBB2_2: ; %one
+; GFX11-TRUE16-NEXT:    s_mov_b32 s2, s6
+; GFX11-TRUE16-NEXT:    s_mov_b32 s3, s7
+; GFX11-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: br_cc_f16_imm_b:
+; GFX11-FAKE16:       ; %bb.0: ; %entry
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
+; GFX11-FAKE16-NEXT:    s_mov_b32 s6, -1
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_mov_b32 s4, s2
+; GFX11-FAKE16-NEXT:    s_mov_b32 s5, s3
+; GFX11-FAKE16-NEXT:    buffer_load_u16 v0, off, s[4:7], 0
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_ngt_f16_e32 vcc_lo, 0.5, v0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB2_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %two
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0x3800
+; GFX11-FAKE16-NEXT:  .LBB2_2: ; %one
+; GFX11-FAKE16-NEXT:    s_mov_b32 s2, s6
+; GFX11-FAKE16-NEXT:    s_mov_b32 s3, s7
+; GFX11-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a) {
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
index 1c9a9d16d2be7..14ddf7daad1c6 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define amdgpu_kernel void @extract_vector_elt_v2f16(ptr addrspace(1) %out, ptr addrspace(4) %vec.ptr) #0 {
 ; SI-LABEL: extract_vector_elt_v2f16:
@@ -215,19 +216,34 @@ define amdgpu_kernel void @extract_vector_elt_v3f16(ptr addrspace(1) %out, <3 x
 ; VI-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:2
 ; VI-NEXT:    s_endp...
[truncated]

mikaelholmen · 2025-03-17T08:28:54Z

Hi @broxigarchen
With this patch
CodeGen/AMDGPU/fneg-combines.f16.ll
fails if you've compiled llc with EXPENSIVE_CHECKS.
Then it fails like

# After Instruction Selection
# Machine code for function fneg_fadd_0_f16: IsSSA, TracksLiveness
Function Live Ins: $sgpr0 in %0, $sgpr1 in %1

bb.0..entry:
  liveins: $sgpr0, $sgpr1
  %1:sgpr_32 = COPY $sgpr1
  %0:sgpr_32 = COPY $sgpr0
  %2:vgpr_16 = nofpexcept V_RCP_F16_t16_e64 0, %1:sgpr_32, 0, 0, 0, implicit $mode, implicit $exec
  %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  %5:vgpr_16 = COPY %3:vgpr_32
  %4:vgpr_16 = nofpexcept V_MUL_F16_t16_e64 0, killed %2:vgpr_16, 0, %5:vgpr_16, 0, 0, 0, implicit $mode, implicit $exec
  %7:vgpr_16 = COPY %3:vgpr_32
  %6:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, killed %4:vgpr_16, 0, %7:vgpr_16, 0, 0, 0, implicit $mode, implicit $exec
  %8:sreg_32_xm0_xexec = nofpexcept V_CMP_NLT_F16_t16_e64 0, %6:vgpr_16, 0, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
  %9:sreg_32 = S_MOV_B32 32768
  %20:vgpr_32 = COPY %6:vgpr_16
  %21:vgpr_32 = V_XOR_B32_e64 %20:vgpr_32, killed %9:sreg_32, implicit $exec
  %13:sgpr_lo16 = COPY %0:sgpr_32
  %12:vgpr_16 = V_CNDMASK_B16_t16_e64 0, killed %21:vgpr_32, 0, %13:sgpr_lo16, killed %8:sreg_32_xm0_xexec, 0, implicit $exec
  %15:vgpr_16 = COPY %3:vgpr_32
  %14:sreg_32_xm0_xexec = nofpexcept V_CMP_NGT_F16_t16_e64 0, killed %12:vgpr_16, 0, %15:vgpr_16, 0, 0, implicit $mode, implicit $exec
  %16:vgpr_32 = V_MOV_B32_e32 32256, implicit $exec
  %18:vgpr_16 = COPY %16:vgpr_32
  %19:vgpr_16 = COPY %3:vgpr_32
  %17:vgpr_16 = V_CNDMASK_B16_t16_e64 0, killed %18:vgpr_16, 0, %19:vgpr_16, killed %14:sreg_32_xm0_xexec, 0, implicit $exec
  $vgpr0 = COPY %17:vgpr_16
  SI_RETURN_TO_EPILOG $vgpr0

# End machine code for function fneg_fadd_0_f16.

*** Bad machine code: Illegal virtual register for instruction ***
- function:    fneg_fadd_0_f16
- basic block: %bb.0 .entry (0x562e994ac130)
- instruction: %12:vgpr_16 = V_CNDMASK_B16_t16_e64 0, killed %21:vgpr_32, 0, %13:sgpr_lo16, killed %8:sreg_32_xm0_xexec, 0, implicit $exec
- operand 2:   killed %21:vgpr_32
Expected a VS_16 register, but got a VGPR_32 register

*** Bad machine code: Illegal virtual register for instruction ***
- function:    fneg_fadd_0_f16
- basic block: %bb.0 .entry (0x562e994ac130)
- instruction: %12:vgpr_16 = V_CNDMASK_B16_t16_e64 0, killed %21:vgpr_32, 0, %13:sgpr_lo16, killed %8:sreg_32_xm0_xexec, 0, implicit $exec
- operand 4:   %13:sgpr_lo16
Expected a VS_16 register, but got a SGPR_LO16 register
LLVM ERROR: Found 2 machine code errors.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /repo/uabelho/main-github/llvm/build-all-expensive/bin/llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16
1.	Running pass 'CallGraph Pass Manager' on module '<stdin>'.
2.	Running pass 'Verify generated machine code' on function '@fneg_fadd_0_f16'
 #0 0x0000562e95d9efd6 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/repo/uabelho/main-github/llvm/build-all-expensive/bin/llc+0x7e70fd6)
 #1 0x0000562e95d9ca3e llvm::sys::RunSignalHandlers() (/repo/uabelho/main-github/llvm/build-all-expensive/bin/llc+0x7e6ea3e)
 #2 0x0000562e95d9f699 SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
 #3 0x00007f77a641bd10 __restore_rt (/lib64/libpthread.so.0+0x12d10)
 #4 0x00007f77a3dbb52f raise (/lib64/libc.so.6+0x4e52f)
 #5 0x00007f77a3d8ee65 abort (/lib64/libc.so.6+0x21e65)
 #6 0x0000562e95ce0713 llvm::report_fatal_error(llvm::Twine const&, bool) (/repo/uabelho/main-github/llvm/build-all-expensive/bin/llc+0x7db2713)
 #7 0x0000562e94d95450 llvm::initializeMachineVerifierLegacyPassPass(llvm::PassRegistry&) (/repo/uabelho/main-github/llvm/build-all-expensive/bin/llc+0x6e67450)
 #8 0x0000562e94d96472 (anonymous namespace)::MachineVerifierLegacyPass::runOnMachineFunction(llvm::MachineFunction&) MachineVerifier.cpp:0:0
 #9 0x0000562e94c40657 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/repo/uabelho/main-github/llvm/build-all-expensive/bin/llc+0x6d12657)
#10 0x0000562e9524101e llvm::FPPassManager::runOnFunction(llvm::Function&) (/repo/uabelho/main-github/llvm/build-all-expensive/bin/llc+0x731301e)
#11 0x0000562e9464776a (anonymous namespace)::CGPassManager::runOnModule(llvm::Module&) CallGraphSCCPass.cpp:0:0
#12 0x0000562e95241b46 llvm::legacy::PassManagerImpl::run(llvm::Module&) (/repo/uabelho/main-github/llvm/build-all-expensive/bin/llc+0x7313b46)
#13 0x0000562e92a02587 compileModule(char**, llvm::LLVMContext&) llc.cpp:0:0
#14 0x0000562e929ffb20 main (/repo/uabelho/main-github/llvm/build-all-expensive/bin/llc+0x4ad1b20)
#15 0x00007f77a3da77e5 __libc_start_main (/lib64/libc.so.6+0x3a7e5)
#16 0x0000562e929fef6e _start (/repo/uabelho/main-github/llvm/build-all-expensive/bin/llc+0x4ad0f6e)
/repo/uabelho/main-github/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll:560:28: error: GFX11-SAFE-TRUE16-LABEL: expected string not found in input
; GFX11-SAFE-TRUE16-LABEL: v_fneg_add_multi_use_fneg_x_f16:
                           ^
<stdin>:263:33: note: scanning from here
v_fneg_add_store_use_fneg_x_f16: ; @v_fneg_add_store_use_fneg_x_f16
                                ^
<stdin>:263:37: note: possible intended match here
v_fneg_add_store_use_fneg_x_f16: ; @v_fneg_add_store_use_fneg_x_f16
                                    ^

Input file: <stdin>
Check file: /repo/uabelho/main-github/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
             .
             .
             .
           258:  .long 0 
           259:  .text 
           260:  .globl v_fneg_add_store_use_fneg_x_f16 ; -- Begin function v_fneg_add_store_use_fneg_x_f16 
           261:  .p2align 2 
           262:  .type v_fneg_add_store_use_fneg_x_f16,@function 
           263: v_fneg_add_store_use_fneg_x_f16: ; @v_fneg_add_store_use_fneg_x_f16 
label:560'0                                     X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
label:560'1                                         ?                                possible intended match
           264: ; %bb.0: 
label:560'0     ~~~~~~~~~
           265:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
label:560'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           266:  v_mov_b16_e32 v0.h, v0.l 
label:560'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~
           267:  s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) 
label:560'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           268:  v_sub_f16_e32 v0.l, v1.l, v0.h 
label:560'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
             .
             .
             .
>>>>>>

--

********************
********************
Failed Tests (1):
  LLVM :: CodeGen/AMDGPU/fneg-combines.f16.ll

It also fails with a normal build if you just add "-verify-machineinstrs" like
llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < /repo/uabelho/main-github/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll -verify-machineinstrs

broxigarchen · 2025-03-17T14:10:59Z

It also fails with a normal build if you just add "-verify-machineinstrs" like llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < /repo/uabelho/main-github/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll -verify-machineinstrs

I am looking at this. Thanks for the comments!

broxigarchen · 2025-03-17T16:09:32Z

The fix is up here #131634

broxigarchen · 2025-03-18T17:12:21Z

Previous fix is dropped. A new fix is up here #131859

vvereschaka · 2025-03-20T07:06:48Z

@broxigarchen,
the expensive check builders remain broken because of this PR for more than 5 days. Would you revert these changes as soon as it possible.
https://lab.llvm.org/buildbot/#/builders/187/builds/4835

broxigarchen · 2025-03-20T14:31:21Z

Revert this test change in #132221

This is a NFC change. Revert the failed test case in #131206

…221) This is a NFC change. Revert the failed test case in llvm/llvm-project#131206

broxigarchen force-pushed the main-true16-codegen-more-test branch from 6f480ec to 28dc7ae Compare March 13, 2025 20:22

enable true16 for more codegen test

4d68ddb

broxigarchen force-pushed the main-true16-codegen-more-test branch from 28dc7ae to 4d68ddb Compare March 13, 2025 20:23

broxigarchen changed the title ~~enable true16 for more codegen test~~ [AMDGPU][True16][CodeGen] enable true16 for more codegen test Mar 13, 2025

broxigarchen marked this pull request as ready for review March 13, 2025 20:27

llvmbot added the backend:AMDGPU label Mar 13, 2025

broxigarchen changed the title ~~[AMDGPU][True16][CodeGen] enable true16 for more codegen test~~ [AMDGPU][True16][CodeGen] enable true16 for more codegen test patch 1 Mar 13, 2025

broxigarchen requested review from Sisyph, arsenm, kosarev and shiltian March 14, 2025 02:39

arsenm approved these changes Mar 14, 2025

View reviewed changes

broxigarchen merged commit 0b688f3 into llvm:main Mar 14, 2025
12 of 14 checks passed

broxigarchen mentioned this pull request Mar 20, 2025

[AMDGPU][True16][CodeGen]disable true16 on fneg test #132221

Merged

broxigarchen added a commit that referenced this pull request Mar 20, 2025

[AMDGPU][True16][CodeGen]disable true16 on fneg test (#132221)

55d3a55

This is a NFC change. Revert the failed test case in #131206

llvm-sync bot pushed a commit to arm/arm-toolchain that referenced this pull request Mar 20, 2025

Automerge: [AMDGPU][True16][CodeGen]disable true16 on fneg test (#132…

ef626e0

…221) This is a NFC change. Revert the failed test case in llvm/llvm-project#131206

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broxigarchen commented Mar 13, 2025 •

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