From 9e689bed9d0490d0d2e464cb21dc9799c0fa2603 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Mon, 17 Mar 2025 13:22:25 +0100 Subject: [PATCH 1/3] [AMDGPU] Add sext_trunc in RegBankCombiner --- llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td index d598395d79e8f..e591879060f30 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td @@ -182,5 +182,5 @@ def AMDGPURegBankCombiner : GICombiner< zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain, fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp, identity_combines, redundant_and, constant_fold_cast_op, - cast_of_cast_combines]> { + cast_of_cast_combines, sext_trunc]> { } From 5217b228a048134d22f3560410c266a4855e3178 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Mon, 24 Mar 2025 12:14:01 +0100 Subject: [PATCH 2/3] Add test --- .../AMDGPU/GlobalISel/combine-trunc-sext.mir | 43 +++++++++++++------ 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir index b2277c4e1141b..03f5d940db57e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,PRELEGAL %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,RBCOMB %s --- name: trunc_sext_i32_i16 @@ -65,12 +66,20 @@ body: | bb.0: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-LABEL: name: trunc_sext_v4i32_v4i16 - ; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: {{ $}} - ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s32>) = G_SEXT_INREG [[COPY]], 16 - ; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[SEXT_INREG]](<4 x s32>) + ; PRELEGAL-LABEL: name: trunc_sext_v4i32_v4i16 + ; PRELEGAL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 + ; PRELEGAL-NEXT: {{ $}} + ; PRELEGAL-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + ; PRELEGAL-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s32>) = G_SEXT_INREG [[COPY]], 16 + ; PRELEGAL-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[SEXT_INREG]](<4 x s32>) + ; + ; RBCOMB-LABEL: name: trunc_sext_v4i32_v4i16 + ; RBCOMB: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 + ; RBCOMB-NEXT: {{ $}} + ; RBCOMB-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + ; RBCOMB-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY]](<4 x s32>) + ; RBCOMB-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[TRUNC]](<4 x s16>) + ; RBCOMB-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[SEXT]](<4 x s32>) %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %1:_(<4 x s16>) = G_TRUNC %0 %2:_(<4 x s32>) = G_SEXT %1 @@ -84,12 +93,20 @@ body: | bb.0: liveins: $vgpr0_vgpr1 - ; GCN-LABEL: name: trunc_sext_v4i16_v4i8 - ; GCN: liveins: $vgpr0_vgpr1 - ; GCN-NEXT: {{ $}} - ; GCN-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 - ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s16>) = G_SEXT_INREG [[COPY]], 8 - ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](<4 x s16>) + ; PRELEGAL-LABEL: name: trunc_sext_v4i16_v4i8 + ; PRELEGAL: liveins: $vgpr0_vgpr1 + ; PRELEGAL-NEXT: {{ $}} + ; PRELEGAL-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 + ; PRELEGAL-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s16>) = G_SEXT_INREG [[COPY]], 8 + ; PRELEGAL-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](<4 x s16>) + ; + ; RBCOMB-LABEL: name: trunc_sext_v4i16_v4i8 + ; RBCOMB: liveins: $vgpr0_vgpr1 + ; RBCOMB-NEXT: {{ $}} + ; RBCOMB-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 + ; RBCOMB-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[COPY]](<4 x s16>) + ; RBCOMB-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s16>) = G_SEXT [[TRUNC]](<4 x s8>) + ; RBCOMB-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](<4 x s16>) %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %1:_(<4 x s8>) = G_TRUNC %0 %2:_(<4 x s16>) = G_SEXT %1 From 2f2f6b77ca3e538e5d22f71edff3574e8ac9f93f Mon Sep 17 00:00:00 2001 From: pvanhout Date: Wed, 26 Mar 2025 10:19:44 +0100 Subject: [PATCH 3/3] Drop -verify-machineinstrs --- llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir index 03f5d940db57e..b9e6c36324a9d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,PRELEGAL %s -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,RBCOMB %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck -check-prefixes=GCN,PRELEGAL %s +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck -check-prefixes=GCN,RBCOMB %s --- name: trunc_sext_i32_i16