diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 5ac7779240148..42429ffc279c7 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3420,9 +3420,17 @@ bool RISCVAsmParser::parseDirectiveVariantCC() {
   return false;
 }
 
+static cl::opt<bool> RVDisableInlineAsmCompress(
+    "riscv-disable-inline-asm-compress",
+    cl::desc("disable compressing inline-asm instructions to their compress "
+             "counterpart."),
+    cl::init(false), cl::Hidden);
+
 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
   MCInst CInst;
-  bool Res = RISCVRVC::compress(CInst, Inst, getSTI());
+  bool Res = false;
+  if (!RVDisableInlineAsmCompress)
+    Res = RISCVRVC::compress(CInst, Inst, getSTI());
   if (Res)
     ++RISCVNumInstrsCompressed;
   S.emitInstruction((Res ? CInst : Inst), getSTI());
diff --git a/llvm/test/MC/RISCV/disable-asm-compress.s b/llvm/test/MC/RISCV/disable-asm-compress.s
new file mode 100644
index 0000000000000..41e0ffcf9b588
--- /dev/null
+++ b/llvm/test/MC/RISCV/disable-asm-compress.s
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --llvm-mc-binary bin/llvm-mc --version 5
+# RUN: llvm-mc -triple riscv32 -mattr=+c -assemble -riscv-no-aliases  -show-encoding                                   < %s | FileCheck %s --check-prefix=ENABLED
+# RUN: llvm-mc -triple riscv32 -mattr=+c -assemble -riscv-no-aliases  -show-encoding -riscv-disable-inline-asm-compress < %s | FileCheck %s --check-prefix=DISABLED
+
+	addi	sp, sp, -16
+// ENABLED: c.addi	sp, -16                         # encoding: [0x41,0x11]
+// DISABLED: addi	sp, sp, -16                     # encoding: [0x13,0x01,0x01,0xff]
+	sw	ra, 12(sp)
+// ENABLED: c.swsp	ra, 12(sp)                      # encoding: [0x06,0xc6]
+// DISABLED: sw	ra, 12(sp)                      # encoding: [0x23,0x26,0x11,0x00]
+	sw	s0, 8(sp)
+// ENABLED: c.swsp	s0, 8(sp)                       # encoding: [0x22,0xc4]
+// DISABLED: sw	s0, 8(sp)                       # encoding: [0x23,0x24,0x81,0x00]
+	addi	s0, sp, 16
+// ENABLED: c.addi4spn	s0, sp, 16              # encoding: [0x00,0x08]
+// DISABLED: addi	s0, sp, 16                      # encoding: [0x13,0x04,0x01,0x01]
+	li	a0, 0
+// ENABLED: c.li	a0, 0                           # encoding: [0x01,0x45]
+// DISABLED: addi	a0, zero, 0                     # encoding: [0x13,0x05,0x00,0x00]
+	sw	a0, -12(s0)
+// ENABLED: sw	a0, -12(s0)                     # encoding: [0x23,0x2a,0xa4,0xfe]
+// DISABLED: sw	a0, -12(s0)                     # encoding: [0x23,0x2a,0xa4,0xfe]
+	lw	ra, 12(sp)
+// ENABLED: c.lwsp	ra, 12(sp)                      # encoding: [0xb2,0x40]
+// DISABLED: lw	ra, 12(sp)                      # encoding: [0x83,0x20,0xc1,0x00]
+	lw	s0, 8(sp)
+// ENABLED: c.lwsp	s0, 8(sp)                       # encoding: [0x22,0x44]
+// DISABLED: lw	s0, 8(sp)                       # encoding: [0x03,0x24,0x81,0x00]
+	addi	sp, sp, 16
+// ENABLED: c.addi	sp, 16                          # encoding: [0x41,0x01]
+// DISABLED: addi	sp, sp, 16                      # encoding: [0x13,0x01,0x01,0x01]
+	ret
+// ENABLED: c.jr	ra                              # encoding: [0x82,0x80]
+// DISABLED: jalr	zero, 0(ra)                     # encoding: [0x67,0x80,0x00,0x00]
+
+
+
+