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[RISCV][Xqcili] Implement Load Immediate Support #132496

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Merged
merged 4 commits into from
Mar 25, 2025
Merged

[RISCV][Xqcili] Implement Load Immediate Support #132496

merged 4 commits into from
Mar 25, 2025

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@lenary
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@lenary lenary commented Mar 22, 2025

This is required to support li, but the code is also shared with CodeGen so the compiler will now emit instructions from Xqcili when that extension is enabled during compilation.

Also implemented some missed verifiers in
RISCVInstrInfo::verifyInstruction, some of which are required for this change.

@lenary
[RISCV][Xqcili] Implement Load Immediate Support
8df25da 
This is required to support `li`, but the code is also shared with
CodeGen so the compiler will now emit instructions from Xqcili when that
extension is enabled during compilation.

Also implemented some missed verifiers in
`RISCVInstrInfo::verifyInstruction`, some of which are required for this
change.
@lenary lenary requested review from hchandel, svs-quic and topperc March 22, 2025 00:23
@llvmbot llvmbot added backend:RISC-V llvm:mc Machine (object) code labels Mar 22, 2025
@llvmbot
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llvmbot commented Mar 22, 2025 •
edited
Loading

@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

Changes

This is required to support li, but the code is also shared with CodeGen so the compiler will now emit instructions from Xqcili when that extension is enabled during compilation.

Also implemented some missed verifiers in
RISCVInstrInfo::verifyInstruction, some of which are required for this change.

Patch is 30.85 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/132496.diff

4 Files Affected:

  • (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp (+25)
  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+3)
  • (modified) llvm/test/CodeGen/RISCV/imm.ll (+411)
  • (added) llvm/test/MC/RISCV/xqcili-li.s (+39)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index e40c85abc8b5d..81f25054bf878 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -22,6 +22,10 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
     // Assume instructions that aren't listed aren't compressible.
     bool Compressed = false;
     switch (Instr.getOpcode()) {
+    case RISCV::QC_E_LI:
+      // One 48-bit instruction takes the space of 1.5 regular instructions.
+      Cost += 150;
+      continue;
     case RISCV::SLLI:
     case RISCV::SRLI:
       Compressed = true;
@@ -57,6 +61,25 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
     return;
   }
 
+  if (!IsRV64 && STI.hasFeature(RISCV::FeatureVendorXqcili)) {
+    bool FitsOneStandardInst =
+        ((Val & 0xFFF) == 0) || (((Val + 0x800) & 0xFFFFF000) == 0);
+
+    // 20-bit signed immediates that don't fit into `ADDI` or `LUI` should use
+    // `QC.LI` (a single 32-bit instruction).
+    if (!FitsOneStandardInst && isInt<20>(Val)) {
+      Res.emplace_back(RISCV::QC_LI, Val);
+      return;
+    }
+
+    // 32-bit signed immediates that don't fit into `ADDI`, `LUI` or `QC.LI`
+    // should use `QC.E.LI` (a single 48-bit instruction).
+    if (!FitsOneStandardInst && isInt<32>(Val)) {
+      Res.emplace_back(RISCV::QC_E_LI, Val);
+      return;
+    }
+  }
+
   if (isInt<32>(Val)) {
     // Depending on the active bits in the immediate Value v, the following
     // instruction sequences are emitted:
@@ -523,6 +546,8 @@ OpndKind Inst::getOpndKind() const {
   default:
     llvm_unreachable("Unexpected opcode!");
   case RISCV::LUI:
+  case RISCV::QC_LI:
+  case RISCV::QC_E_LI:
     return RISCVMatInt::Imm;
   case RISCV::ADD_UW:
     return RISCVMatInt::RegX0;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 62f978d64fbb9..687bf85b9031a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2603,8 +2603,11 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
           // clang-format off
         CASE_OPERAND_SIMM(5)
         CASE_OPERAND_SIMM(6)
+        CASE_OPERAND_SIMM(11)
         CASE_OPERAND_SIMM(12)
+        CASE_OPERAND_SIMM(20)
         CASE_OPERAND_SIMM(26)
+        CASE_OPERAND_SIMM(32)
         // clang-format on
         case RISCVOp::OPERAND_SIMM5_PLUS1:
           Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index 830f381b659d1..f324a9bc120ef 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -mattr=+experimental-xqcili \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IXQCILI
 ; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=RV64I,RV64-NOPOOL
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
@@ -31,6 +33,11 @@ define signext i32 @zero() nounwind {
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: zero:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a0, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: zero:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0
@@ -74,6 +81,11 @@ define signext i32 @pos_small() nounwind {
 ; RV32I-NEXT:    li a0, 2047
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: pos_small:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a0, 2047
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: pos_small:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 2047
@@ -117,6 +129,11 @@ define signext i32 @neg_small() nounwind {
 ; RV32I-NEXT:    li a0, -2048
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: neg_small:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a0, -2048
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: neg_small:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, -2048
@@ -161,6 +178,11 @@ define signext i32 @pos_i32() nounwind {
 ; RV32I-NEXT:    addi a0, a0, -1297
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: pos_i32:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 1735928559
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: pos_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 423811
@@ -212,6 +234,11 @@ define signext i32 @neg_i32() nounwind {
 ; RV32I-NEXT:    addi a0, a0, -273
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: neg_i32:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, -559038737
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: neg_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 912092
@@ -262,6 +289,11 @@ define signext i32 @pos_i32_hi20_only() nounwind {
 ; RV32I-NEXT:    lui a0, 16
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: pos_i32_hi20_only:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    lui a0, 16
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: pos_i32_hi20_only:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 16
@@ -305,6 +337,11 @@ define signext i32 @neg_i32_hi20_only() nounwind {
 ; RV32I-NEXT:    lui a0, 1048560
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: neg_i32_hi20_only:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    lui a0, 1048560
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: neg_i32_hi20_only:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 1048560
@@ -351,6 +388,11 @@ define signext i32 @imm_left_shifted_addi() nounwind {
 ; RV32I-NEXT:    addi a0, a0, -64
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_left_shifted_addi:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.li a0, 131008
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_left_shifted_addi:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 32
@@ -404,6 +446,11 @@ define signext i32 @imm_right_shifted_addi() nounwind {
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_right_shifted_addi:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 2147483647
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_right_shifted_addi:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 524288
@@ -457,6 +504,11 @@ define signext i32 @imm_right_shifted_lui() nounwind {
 ; RV32I-NEXT:    addi a0, a0, 580
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_right_shifted_lui:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.li a0, 229956
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_right_shifted_lui:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 56
@@ -508,6 +560,12 @@ define i64 @imm64_1() nounwind {
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm64_1:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    lui a0, 524288
+; RV32IXQCILI-NEXT:    li a1, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm64_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
@@ -558,6 +616,12 @@ define i64 @imm64_2() nounwind {
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm64_2:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a0, -1
+; RV32IXQCILI-NEXT:    li a1, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm64_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, -1
@@ -609,6 +673,12 @@ define i64 @imm64_3() nounwind {
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm64_3:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a1, 1
+; RV32IXQCILI-NEXT:    li a0, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm64_3:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
@@ -659,6 +729,12 @@ define i64 @imm64_4() nounwind {
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm64_4:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    lui a1, 524288
+; RV32IXQCILI-NEXT:    li a0, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm64_4:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, -1
@@ -709,6 +785,12 @@ define i64 @imm64_5() nounwind {
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm64_5:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    lui a1, 524288
+; RV32IXQCILI-NEXT:    li a0, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm64_5:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, -1
@@ -760,6 +842,12 @@ define i64 @imm64_6() nounwind {
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm64_6:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a1, 305419896
+; RV32IXQCILI-NEXT:    li a0, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm64_6:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 9321
@@ -819,6 +907,12 @@ define i64 @imm64_7() nounwind {
 ; RV32I-NEXT:    lui a1, 458752
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm64_7:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 184549391
+; RV32IXQCILI-NEXT:    lui a1, 458752
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm64_7:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 7
@@ -893,6 +987,12 @@ define i64 @imm64_8() nounwind {
 ; RV32I-NEXT:    addi a1, a1, 1656
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm64_8:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, -1698898192
+; RV32IXQCILI-NEXT:    qc.e.li a1, 305419896
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64-NOPOOL-LABEL: imm64_8:
 ; RV64-NOPOOL:       # %bb.0:
 ; RV64-NOPOOL-NEXT:    lui a0, 583
@@ -987,6 +1087,12 @@ define i64 @imm64_9() nounwind {
 ; RV32I-NEXT:    li a1, -1
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm64_9:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a0, -1
+; RV32IXQCILI-NEXT:    li a1, -1
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm64_9:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, -1
@@ -1035,6 +1141,12 @@ define i64 @imm_left_shifted_lui_1() nounwind {
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_left_shifted_lui_1:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    lui a0, 524290
+; RV32IXQCILI-NEXT:    li a1, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_left_shifted_lui_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 262145
@@ -1086,6 +1198,12 @@ define i64 @imm_left_shifted_lui_2() nounwind {
 ; RV32I-NEXT:    li a1, 1
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_left_shifted_lui_2:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    lui a0, 4
+; RV32IXQCILI-NEXT:    li a1, 1
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_left_shifted_lui_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 262145
@@ -1138,6 +1256,12 @@ define i64 @imm_left_shifted_lui_3() nounwind {
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_left_shifted_lui_3:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.li a1, 4097
+; RV32IXQCILI-NEXT:    li a0, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_left_shifted_lui_3:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 4097
@@ -1195,6 +1319,12 @@ define i64 @imm_right_shifted_lui_1() nounwind {
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_right_shifted_lui_1:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.li a0, -4095
+; RV32IXQCILI-NEXT:    qc.li a1, 65535
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_right_shifted_lui_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 983056
@@ -1249,6 +1379,12 @@ define i64 @imm_right_shifted_lui_2() nounwind {
 ; RV32I-NEXT:    li a1, 255
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_right_shifted_lui_2:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.li a0, -4095
+; RV32IXQCILI-NEXT:    li a1, 255
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_right_shifted_lui_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 1044481
@@ -1310,6 +1446,12 @@ define i64 @imm_decoupled_lui_addi() nounwind {
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_decoupled_lui_addi:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a0, -3
+; RV32IXQCILI-NEXT:    lui a1, 1
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_decoupled_lui_addi:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 4097
@@ -1370,6 +1512,12 @@ define i64 @imm_end_xori_1() nounwind {
 ; RV32I-NEXT:    lui a1, 917504
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_end_xori_1:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 33554431
+; RV32IXQCILI-NEXT:    lui a1, 917504
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_end_xori_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 983040
@@ -1432,6 +1580,12 @@ define i64 @imm_end_2addi_1() nounwind {
 ; RV32I-NEXT:    addi a1, a1, 127
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_end_2addi_1:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.li a0, -2049
+; RV32IXQCILI-NEXT:    qc.li a1, -262017
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_end_2addi_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, -2047
@@ -1501,6 +1655,12 @@ define i64 @imm_2reg_1() nounwind {
 ; RV32I-NEXT:    lui a1, 983040
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_2reg_1:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 305419896
+; RV32IXQCILI-NEXT:    lui a1, 983040
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_2reg_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 74565
@@ -1565,6 +1725,12 @@ define void @imm_store_i8_neg1(ptr %p) nounwind {
 ; RV32I-NEXT:    sb a1, 0(a0)
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_store_i8_neg1:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a1, -1
+; RV32IXQCILI-NEXT:    sb a1, 0(a0)
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_store_i8_neg1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, -1
@@ -1617,6 +1783,12 @@ define void @imm_store_i16_neg1(ptr %p) nounwind {
 ; RV32I-NEXT:    sh a1, 0(a0)
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_store_i16_neg1:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a1, -1
+; RV32IXQCILI-NEXT:    sh a1, 0(a0)
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_store_i16_neg1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, -1
@@ -1669,6 +1841,12 @@ define void @imm_store_i32_neg1(ptr %p) nounwind {
 ; RV32I-NEXT:    sw a1, 0(a0)
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_store_i32_neg1:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    li a1, -1
+; RV32IXQCILI-NEXT:    sw a1, 0(a0)
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_store_i32_neg1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, -1
@@ -1722,6 +1900,12 @@ define i64 @imm_5372288229() {
 ; RV32I-NEXT:    li a1, 1
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_5372288229:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 1077320933
+; RV32IXQCILI-NEXT:    li a1, 1
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_5372288229:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 160
@@ -1785,6 +1969,12 @@ define i64 @imm_neg_5372288229() {
 ; RV32I-NEXT:    li a1, -2
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_neg_5372288229:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, -1077320933
+; RV32IXQCILI-NEXT:    li a1, -2
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_neg_5372288229:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 1048416
@@ -1848,6 +2038,12 @@ define i64 @imm_8953813715() {
 ; RV32I-NEXT:    li a1, 2
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_8953813715:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 363879123
+; RV32IXQCILI-NEXT:    li a1, 2
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_8953813715:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 267
@@ -1911,6 +2107,12 @@ define i64 @imm_neg_8953813715() {
 ; RV32I-NEXT:    li a1, -3
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_neg_8953813715:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, -363879123
+; RV32IXQCILI-NEXT:    li a1, -3
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_neg_8953813715:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 1048309
@@ -1974,6 +2176,12 @@ define i64 @imm_16116864687() {
 ; RV32I-NEXT:    li a1, 3
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_16116864687:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, -1063004497
+; RV32IXQCILI-NEXT:    li a1, 3
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_16116864687:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 961
@@ -2038,6 +2246,12 @@ define i64 @imm_neg_16116864687() {
 ; RV32I-NEXT:    li a1, -4
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_neg_16116864687:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 1063004497
+; RV32IXQCILI-NEXT:    li a1, -4
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_neg_16116864687:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 1047615
@@ -2102,6 +2316,12 @@ define i64 @imm_2344336315() {
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_2344336315:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, -1950630981
+; RV32IXQCILI-NEXT:    li a1, 0
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_2344336315:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 143087
@@ -2161,6 +2381,12 @@ define i64 @imm_70370820078523() {
 ; RV32I-NEXT:    lui a1, 4
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_70370820078523:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 2075900859
+; RV32IXQCILI-NEXT:    lui a1, 4
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64-NOPOOL-LABEL: imm_70370820078523:
 ; RV64-NOPOOL:       # %bb.0:
 ; RV64-NOPOOL-NEXT:    lui a0, 256
@@ -2241,6 +2467,12 @@ define i64 @imm_neg_9223372034778874949() {
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_neg_9223372034778874949:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 2075900859
+; RV32IXQCILI-NEXT:    lui a1, 524288
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_neg_9223372034778874949:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 506812
@@ -2305,6 +2537,12 @@ define i64 @imm_neg_9223301666034697285() {
 ; RV32I-NEXT:    lui a1, 524292
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_neg_9223301666034697285:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 2075900859
+; RV32IXQCILI-NEXT:    lui a1, 524292
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64-NOPOOL-LABEL: imm_neg_9223301666034697285:
 ; RV64-NOPOOL:       # %bb.0:
 ; RV64-NOPOOL-NEXT:    lui a0, 917505
@@ -2391,6 +2629,12 @@ define i64 @imm_neg_2219066437() {
 ; RV32I-NEXT:    li a1, -1
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_neg_2219066437:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, 2075900859
+; RV32IXQCILI-NEXT:    li a1, -1
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_neg_2219066437:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 913135
@@ -2451,6 +2695,12 @@ define i64 @imm_neg_8798043653189() {
 ; RV32I-NEXT:    addi a1, a1, 2047
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_neg_8798043653189:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, -1950630981
+; RV32IXQCILI-NEXT:    qc.li a1, -2049
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_neg_8798043653189:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 917475
@@ -2517,6 +2767,12 @@ define i64 @imm_9223372034904144827() {
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_9223372034904144827:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, -1950630981
+; RV32IXQCILI-NEXT:    qc.e.li a1, 2147483647
+; RV32IXQCILI-NEXT:    ret
+;
 ; RV64I-LABEL: imm_9223372034904144827:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 572348
@@ -2583,6 +2839,12 @@ define i64 @imm_neg_9223354442718100411() {
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    ret
 ;
+; RV32IXQCILI-LABEL: imm_neg_9223354442718100411:
+; RV32IXQCILI:       # %bb.0:
+; RV32IXQCILI-NEXT:    qc.e.li a0, -1950630981
+; RV32IXQCILI-NEXT:    qc.e.li a1, 2147479551
+; RV32IXQCILI-NEXT:    ret
+;
 ;...
[truncated]

svs-quic
svs-quic approved these changes Mar 22, 2025
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LGTM but please wait for someone else to take a look as well.

topperc
topperc reviewed Mar 22, 2025
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llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp Outdated

if (!IsRV64 && STI.hasFeature(RISCV::FeatureVendorXqcili)) {
bool FitsOneStandardInst =
((Val & 0xFFF) == 0) || (((Val + 0x800) & 0xFFFFF000) == 0);
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@topperc topperc Mar 22, 2025

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Can we do

return ((Val & 0xFFF) == 0) || isInt<12>(Val);

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@lenary lenary Mar 24, 2025

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Yes, done.

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svs-quic commented Mar 24, 2025

Do you also want to add to the Release Notes that we are doing some code generation for Xqcili?

@lenary
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lenary commented Mar 24, 2025

Do you also want to add to the Release Notes that we are doing some code generation for Xqcili?

Yes, added.

topperc
topperc approved these changes Mar 24, 2025
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LGTM

@lenary lenary merged commit 629ff2d into llvm:main Mar 25, 2025
6 of 10 checks passed
@lenary lenary deleted the pr/riscv-xqcili-li branch March 25, 2025 15:00
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@topperc topperc topperc approved these changes

@svs-quic svs-quic svs-quic approved these changes

@hchandel hchandel Awaiting requested review from hchandel

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@lenary @llvmbot @svs-quic @topperc