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[llvm] Construct SmallVector with ArrayRef (NFC) #132560

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Merged
merged 1 commit into from
Mar 22, 2025
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[llvm] Construct SmallVector with ArrayRef (NFC) #132560

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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -183,7 +183,7 @@ void LegalizerHelper::insertParts(Register DstReg,
// Merge sub-vectors with different number of elements and insert into DstReg.
if (ResultTy.isVector()) {
assert(LeftoverRegs.size() == 1 && "Expected one leftover register");
SmallVector<Register, 8> AllRegs(PartRegs.begin(), PartRegs.end());
SmallVector<Register, 8> AllRegs(PartRegs);
AllRegs.append(LeftoverRegs.begin(), LeftoverRegs.end());
return mergeMixedSubvectors(DstReg, AllRegs);
}
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3 changes: 1 addition & 2 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Expand Up @@ -17651,8 +17651,7 @@ bool AArch64TargetLowering::lowerInterleaveIntrinsicToStore(
Builder.CreateVectorSplat(StTy->getElementCount(), Builder.getTrue());

auto ExtractedValues = InterleavedValues;
SmallVector<Value *, 4> StoreOperands(InterleavedValues.begin(),
InterleavedValues.end());
SmallVector<Value *, 4> StoreOperands(InterleavedValues);
if (UseScalable)
StoreOperands.push_back(Pred);
StoreOperands.push_back(BaseAddr);
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3 changes: 1 addition & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -23255,8 +23255,7 @@ bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(
SI->getModule(), FixedVssegIntrIds[Factor - 2],
{InVTy, SI->getPointerOperandType(), XLenTy});

SmallVector<Value *, 10> Ops(InterleaveValues.begin(),
InterleaveValues.end());
SmallVector<Value *, 10> Ops(InterleaveValues);
Value *VL = ConstantInt::get(XLenTy, FVTy->getNumElements());
Ops.append({SI->getPointerOperand(), VL});

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