diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index e732bbcf525e9..37acaa2be0a1b 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2103,9 +2103,7 @@ void CodeGenRegBank::computeRegUnitSets() {
 
   // For each register class, list the UnitSets that are supersets.
   RegClassUnitSets.resize(RegClasses.size());
-  int RCIdx = -1;
   for (auto &RC : RegClasses) {
-    ++RCIdx;
     if (!RC.Allocatable)
       continue;
 
@@ -2127,12 +2125,13 @@ void CodeGenRegBank::computeRegUnitSets() {
          ++USIdx) {
       if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) {
         LLVM_DEBUG(dbgs() << " " << USIdx);
-        RegClassUnitSets[RCIdx].push_back(USIdx);
+        RegClassUnitSets[RC.EnumValue].push_back(USIdx);
       }
     }
     LLVM_DEBUG(dbgs() << "\n");
-    assert((!RegClassUnitSets[RCIdx].empty() || !RC.GeneratePressureSet) &&
-           "missing unit set for regclass");
+    assert(
+        (!RegClassUnitSets[RC.EnumValue].empty() || !RC.GeneratePressureSet) &&
+        "missing unit set for regclass");
   }
 
   // For each register unit, ensure that we have the list of UnitSets that