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[RISCV][MC] Enable printing of zext.b alias #133502

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Merged
asb merged 1 commit into from
Mar 28, 2025
Merged

[RISCV][MC] Enable printing of zext.b alias #133502

asb merged 1 commit into from
Mar 28, 2025

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@asb
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@asb asb commented Mar 28, 2025

The comment shows that at the time we were worried about producing the alias in assembly that might be ingested by a binutils version that doesn't yet support it. binutils gained support over 4 years ago https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c2137f55ad04e451d834048d4bfec1de2daea20e. With all the changes in areas such as ELF attributes, if you tried to use LLVM's RISC-V assembler output with a binutils that old then zext.b would be the least of your worries.

@asb
[RISCV][MC] Enable printing of zext.b alias
48200cc 
The comment shows that at the time we were worried about producing the
alias in assembly that might be ingested by a binutils version that
doesn't yet support it. binutils gained support over 4 years ago
<https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c2137f55ad04e451d834048d4bfec1de2daea20e>,
and with all the changes in areas such as ELF attributes, if you tried
to use LLVM's RISC-V assembler output with a binutils that old zext.b
would be the least of your worries.
@llvmbot
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llvmbot commented Mar 28, 2025 •
edited
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@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-mc

Author: Alex Bradbury (asb)

Changes

The comment shows that at the time we were worried about producing the alias in assembly that might be ingested by a binutils version that doesn't yet support it. binutils gained support over 4 years ago <https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c2137f55ad04e451d834048d4bfec1de2daea20e>. With all the changes in areas such as ELF attributes, if you tried to use LLVM's RISC-V assembler output with a binutils that old then zext.b would be the least of your worries.

Patch is 339.66 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/133502.diff

63 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1-4)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll (+4-4)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll (+3-3)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll (+3-3)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll (+9-9)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll (+10-10)
  • (modified) llvm/test/CodeGen/RISCV/abdu-neg.ll (+28-28)
  • (modified) llvm/test/CodeGen/RISCV/abdu.ll (+33-33)
  • (modified) llvm/test/CodeGen/RISCV/alu8.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll (+16-16)
  • (modified) llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll (+128-128)
  • (modified) llvm/test/CodeGen/RISCV/atomic-rmw.ll (+275-275)
  • (modified) llvm/test/CodeGen/RISCV/atomic-signext.ll (+34-34)
  • (modified) llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll (+18-18)
  • (modified) llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll (+20-20)
  • (modified) llvm/test/CodeGen/RISCV/avgceilu.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/avgflooru.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll (+4-4)
  • (modified) llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/csr-first-use-cost.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll (+18-18)
  • (modified) llvm/test/CodeGen/RISCV/div-by-constant.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/div.ll (+16-16)
  • (modified) llvm/test/CodeGen/RISCV/double-convert.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/float-convert.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/fold-mem-offset.ll (+10-10)
  • (modified) llvm/test/CodeGen/RISCV/half-convert.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/machine-combiner.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/memset-inline.ll (+22-22)
  • (modified) llvm/test/CodeGen/RISCV/overflow-intrinsics.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/pr65025.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rem.ll (+12-12)
  • (modified) llvm/test/CodeGen/RISCV/rv32zbkb.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/rv64zbkb.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll (+4-4)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll (+24-24)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll (+68-68)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll (+64-64)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/memset-inline.ll (+10-10)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll (+14-14)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/sext-zext-trunc.ll (+12-12)
  • (modified) llvm/test/CodeGen/RISCV/simplify-condbr.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/split-store.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/typepromotion-overflow.ll (+3-3)
  • (modified) llvm/test/CodeGen/RISCV/uadd_sat_plus.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/usub_sat_plus.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll (+1-1)
  • (modified) llvm/test/MC/RISCV/rv32i-aliases-valid.s (+1-1)
  • (modified) llvm/test/MC/RISCV/rv64i-aliases-valid.s (+1-1)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index b61992298ca95..49068780f697d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1118,10 +1118,7 @@ def : MnemonicAlias<"move", "mv">;
 def : MnemonicAlias<"scall", "ecall">;
 def : MnemonicAlias<"sbreak", "ebreak">;
 
-// This alias was added to the spec in December 2020. Don't print it by default
-// to allow assembly we print to be compatible with versions of GNU assembler
-// that don't support this alias.
-def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>;
+def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
 
 let Predicates = [HasStdExtZicfilp] in {
 def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
index f1c0fccb78a36..1632f92e96b50 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
@@ -49,15 +49,15 @@ entry:
 define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) {
 ; RV32IM-LABEL: add_i8_zeroext_i32:
 ; RV32IM:       # %bb.0: # %entry
-; RV32IM-NEXT:    andi a0, a0, 255
-; RV32IM-NEXT:    andi a1, a1, 255
+; RV32IM-NEXT:    zext.b a0, a0
+; RV32IM-NEXT:    zext.b a1, a1
 ; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: add_i8_zeroext_i32:
 ; RV64IM:       # %bb.0: # %entry
-; RV64IM-NEXT:    andi a0, a0, 255
-; RV64IM-NEXT:    andi a1, a1, 255
+; RV64IM-NEXT:    zext.b a0, a0
+; RV64IM-NEXT:    zext.b a1, a1
 ; RV64IM-NEXT:    addw a0, a0, a1
 ; RV64IM-NEXT:    ret
 entry:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll b/llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
index f62902cdd14d9..9c46e6792e8d8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
@@ -227,7 +227,7 @@ define i64 @udiv64_constant_add(i64 %a) nounwind {
 define i8 @udiv8_constant_no_add(i8 %a) nounwind {
 ; RV32-LABEL: udiv8_constant_no_add:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    andi a0, a0, 255
+; RV32-NEXT:    zext.b a0, a0
 ; RV32-NEXT:    li a1, 205
 ; RV32-NEXT:    mul a0, a0, a1
 ; RV32-NEXT:    srli a0, a0, 10
@@ -235,7 +235,7 @@ define i8 @udiv8_constant_no_add(i8 %a) nounwind {
 ;
 ; RV64-LABEL: udiv8_constant_no_add:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    andi a0, a0, 255
+; RV64-NEXT:    zext.b a0, a0
 ; RV64-NEXT:    li a1, 205
 ; RV64-NEXT:    mul a0, a0, a1
 ; RV64-NEXT:    srli a0, a0, 10
@@ -248,28 +248,28 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
 ; RV32-LABEL: udiv8_constant_add:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    li a1, 37
-; RV32-NEXT:    andi a2, a0, 255
+; RV32-NEXT:    zext.b a2, a0
 ; RV32-NEXT:    mul a1, a2, a1
 ; RV32-NEXT:    srli a1, a1, 8
 ; RV32-NEXT:    sub a0, a0, a1
-; RV32-NEXT:    andi a0, a0, 255
+; RV32-NEXT:    zext.b a0, a0
 ; RV32-NEXT:    srli a0, a0, 1
 ; RV32-NEXT:    add a0, a0, a1
-; RV32-NEXT:    andi a0, a0, 255
+; RV32-NEXT:    zext.b a0, a0
 ; RV32-NEXT:    srli a0, a0, 2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: udiv8_constant_add:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    li a1, 37
-; RV64-NEXT:    andi a2, a0, 255
+; RV64-NEXT:    zext.b a2, a0
 ; RV64-NEXT:    mul a1, a2, a1
 ; RV64-NEXT:    srli a1, a1, 8
 ; RV64-NEXT:    subw a0, a0, a1
-; RV64-NEXT:    andi a0, a0, 255
+; RV64-NEXT:    zext.b a0, a0
 ; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    add a0, a0, a1
-; RV64-NEXT:    andi a0, a0, 255
+; RV64-NEXT:    zext.b a0, a0
 ; RV64-NEXT:    srli a0, a0, 2
 ; RV64-NEXT:    ret
   %1 = udiv i8 %a, 7
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
index aeed219d99555..a49e94f4bc910 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
@@ -855,7 +855,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
 ; CHECKIFD-LABEL: fcvt_wu_s_i8:
 ; CHECKIFD:       # %bb.0:
 ; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; CHECKIFD-NEXT:    andi a0, a0, 255
+; CHECKIFD-NEXT:    zext.b a0, a0
 ; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_i8:
@@ -863,7 +863,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunsdfsi
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
@@ -873,7 +873,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixunsdfsi
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
index 1820ecf3b5056..fa093623dd6f8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
@@ -790,7 +790,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
 ; CHECKIF-LABEL: fcvt_wu_s_i8:
 ; CHECKIF:       # %bb.0:
 ; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; CHECKIF-NEXT:    andi a0, a0, 255
+; CHECKIF-NEXT:    zext.b a0, a0
 ; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_i8:
@@ -798,7 +798,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
@@ -808,7 +808,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixunssfsi
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll b/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
index e29c450c26cb4..ae9b6cc8948f5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
@@ -469,7 +469,7 @@ define fp128 @uitofp_i8(i8 %x) nounwind {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    call __floatunsitf
 ; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
index ababec16f7f8f..da95481a5e588 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
@@ -327,7 +327,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
 define i8 @srli_i8(i8 %a) nounwind {
 ; CHECK-LABEL: srli_i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    srli a0, a0, 6
 ; CHECK-NEXT:    ret
   %1 = lshr i8 %a, 6
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
index b214cf68ddce8..55cb95413ae24 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
@@ -110,7 +110,7 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: packh_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a2, 16
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    addi a2, a2, -256
 ; CHECK-NEXT:    slli a1, a1, 8
 ; CHECK-NEXT:    and a1, a1, a2
@@ -126,8 +126,8 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind {
 define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: packh_i32_2:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    andi a1, a1, 255
+; RV32I-NEXT:    zext.b a0, a0
+; RV32I-NEXT:    zext.b a1, a1
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
@@ -148,7 +148,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: packh_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, 16
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    addi a1, a1, -256
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    and a1, a2, a1
@@ -166,8 +166,8 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: packh_i64_2:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    andi a1, a2, 255
+; RV32I-NEXT:    zext.b a0, a0
+; RV32I-NEXT:    zext.b a1, a2
 ; RV32I-NEXT:    slli a2, a1, 8
 ; RV32I-NEXT:    srli a1, a1, 24
 ; RV32I-NEXT:    or a0, a2, a0
@@ -175,7 +175,7 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
 ;
 ; RV32ZBKB-LABEL: packh_i64_2:
 ; RV32ZBKB:       # %bb.0:
-; RV32ZBKB-NEXT:    andi a1, a2, 255
+; RV32ZBKB-NEXT:    zext.b a1, a2
 ; RV32ZBKB-NEXT:    srli a1, a1, 24
 ; RV32ZBKB-NEXT:    packh a0, a0, a2
 ; RV32ZBKB-NEXT:    ret
@@ -210,7 +210,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
 ; RV32I-LABEL: packh_i16_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    slli a0, a0, 8
 ; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    ret
@@ -232,7 +232,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
 ; RV32I-LABEL: packh_i16_3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    slli a0, a0, 8
 ; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    sh a0, 0(a3)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
index 79d08772e8853..1eddb8fc2797e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
@@ -405,7 +405,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
 define i8 @srli_i8(i8 %a) nounwind {
 ; CHECK-LABEL: srli_i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    srli a0, a0, 6
 ; CHECK-NEXT:    ret
   %1 = lshr i8 %a, 6
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
index 558424b53be95..f413abffcdccc 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
@@ -140,7 +140,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: packh_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 16
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    and a1, a1, a2
@@ -150,7 +150,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64ZBKB-LABEL: packh_i32:
 ; RV64ZBKB:       # %bb.0:
 ; RV64ZBKB-NEXT:    lui a2, 16
-; RV64ZBKB-NEXT:    andi a0, a0, 255
+; RV64ZBKB-NEXT:    zext.b a0, a0
 ; RV64ZBKB-NEXT:    addiw a2, a2, -256
 ; RV64ZBKB-NEXT:    slli a1, a1, 8
 ; RV64ZBKB-NEXT:    and a1, a1, a2
@@ -166,8 +166,8 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
 define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
 ; RV64I-LABEL: packh_i32_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    andi a1, a1, 255
+; RV64I-NEXT:    zext.b a0, a0
+; RV64I-NEXT:    zext.b a1, a1
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
@@ -188,7 +188,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: packh_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 16
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    and a1, a1, a2
@@ -198,7 +198,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 ; RV64ZBKB-LABEL: packh_i64:
 ; RV64ZBKB:       # %bb.0:
 ; RV64ZBKB-NEXT:    lui a2, 16
-; RV64ZBKB-NEXT:    andi a0, a0, 255
+; RV64ZBKB-NEXT:    zext.b a0, a0
 ; RV64ZBKB-NEXT:    addiw a2, a2, -256
 ; RV64ZBKB-NEXT:    slli a1, a1, 8
 ; RV64ZBKB-NEXT:    and a1, a1, a2
@@ -214,8 +214,8 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: packh_i64_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    andi a1, a1, 255
+; RV64I-NEXT:    zext.b a0, a0
+; RV64I-NEXT:    zext.b a1, a1
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
@@ -253,7 +253,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
 ; RV64I-LABEL: packh_i16_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    slli a0, a0, 8
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    ret
@@ -275,7 +275,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
 ; RV64I-LABEL: packh_i16_3:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    slli a0, a0, 8
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    sh a0, 0(a3)
diff --git a/llvm/test/CodeGen/RISCV/abdu-neg.ll b/llvm/test/CodeGen/RISCV/abdu-neg.ll
index 9e41cde7ae181..9fa142ee2aa1e 100644
--- a/llvm/test/CodeGen/RISCV/abdu-neg.ll
+++ b/llvm/test/CodeGen/RISCV/abdu-neg.ll
@@ -11,8 +11,8 @@
 define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ; RV32I-LABEL: abd_ext_i8:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a1, a1, 255
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a1, a1
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    xor a0, a0, a1
@@ -21,8 +21,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: abd_ext_i8:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    andi a1, a1, 255
+; RV64I-NEXT:    zext.b a0, a0
+; RV64I-NEXT:    zext.b a1, a1
 ; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    xor a0, a0, a1
@@ -31,8 +31,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ;
 ; RV32ZBB-LABEL: abd_ext_i8:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    andi a1, a1, 255
-; RV32ZBB-NEXT:    andi a0, a0, 255
+; RV32ZBB-NEXT:    zext.b a1, a1
+; RV32ZBB-NEXT:    zext.b a0, a0
 ; RV32ZBB-NEXT:    maxu a2, a0, a1
 ; RV32ZBB-NEXT:    minu a0, a0, a1
 ; RV32ZBB-NEXT:    sub a0, a0, a2
@@ -40,8 +40,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ;
 ; RV64ZBB-LABEL: abd_ext_i8:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    andi a0, a0, 255
-; RV64ZBB-NEXT:    andi a1, a1, 255
+; RV64ZBB-NEXT:    zext.b a0, a0
+; RV64ZBB-NEXT:    zext.b a1, a1
 ; RV64ZBB-NEXT:    sub a0, a0, a1
 ; RV64ZBB-NEXT:    neg a1, a0
 ; RV64ZBB-NEXT:    min a0, a0, a1
@@ -60,7 +60,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a1, 16
 ; RV32I-NEXT:    srli a1, a1, 16
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    xor a0, a0, a1
@@ -69,7 +69,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: abd_ext_i8_i16:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    slli a1, a1, 48
 ; RV64I-NEXT:    srli a1, a1, 48
 ; RV64I-NEXT:    sub a0, a0, a1
@@ -81,7 +81,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 ; RV32ZBB-LABEL: abd_ext_i8_i16:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    zext.h a1, a1
-; RV32ZBB-NEXT:    andi a0, a0, 255
+; RV32ZBB-NEXT:    zext.b a0, a0
 ; RV32ZBB-NEXT:    maxu a2, a0, a1
 ; RV32ZBB-NEXT:    minu a0, a0, a1
 ; RV32ZBB-NEXT:    sub a0, a0, a2
@@ -89,7 +89,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 ;
 ; RV64ZBB-LABEL: abd_ext_i8_i16:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    andi a0, a0, 255
+; RV64ZBB-NEXT:    zext.b a0, a0
 ; RV64ZBB-NEXT:    zext.h a1, a1
 ; RV64ZBB-NEXT:    sub a0, a0, a1
 ; RV64ZBB-NEXT:    neg a1, a0
@@ -107,8 +107,8 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
 ; RV32I-LABEL: abd_ext_i8_undef:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a1, a1, 255
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a1, a1
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    xor a0, a0, a1
@@ -117,8 +117,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: abd_ext_i8_undef:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    andi a1, a1, 255
+; RV64I-NEXT:    zext.b a0, a0
+; RV64I-NEXT:    zext.b a1, a1
 ; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    xor a0, a0, a1
@@ -127,8 +127,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
 ;
 ; RV32ZBB-LABEL: abd_ext_i8_undef:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    andi a1, a1, 255
-; RV32ZBB-NEXT:    andi a0, a0, 255
+; RV32ZBB-NEXT:    zext.b a1, a1
+; RV32ZBB-NEXT:    zext.b a0, a0
 ; RV32ZBB-NEXT:    maxu a2, a0, a1
 ; RV32ZBB-NEXT:    minu a0, a0, a1
 ; RV32ZBB-NEXT:    sub a0, a0, a2
@@ -136,8 +136,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
 ;
 ; RV64ZBB-LABEL: abd_ext_i8_undef:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    andi a0, a0, 255
-; RV64ZBB-NEXT:    andi a1, a1, 255
+; RV64ZBB-NEXT:    zext.b a0, a0
+; RV64ZBB-NEXT:    zext.b a1, a1
 ; RV64ZBB-NEXT:    sub a0, a0, a1
 ; RV64ZBB-NEXT:    neg a1, a0
 ; RV64ZBB-NEXT:    min a0, a0, a1
@@ -1094,8 +1094,8 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
 define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
 ; NOZBB-LABEL: abd_minmax_i8:
 ; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    andi a1, a1, 255
-; NOZBB-NEXT:    andi a0, a0, 255
+; NOZBB-NEXT:    zext.b a1, a1
+; NOZBB-NEXT:    zext.b a0, a0
 ; NOZBB-NEXT:    mv a2, a0
 ; NOZBB-NEXT:    bgeu a0, a1, .LBB13_3
 ; NOZBB-NEXT:  # %bb.1:
@@ -1112,8 +1112,8 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
 ;
 ; ZBB-LABEL: abd_minmax_i8:
 ; ZBB:       # %bb.0:
-; ZBB-NEXT:    andi a1, a1, 255
-; ZBB-NEXT:    andi a0, a0, 255
+; ZBB-NEXT:    zext.b a1, a1
+; ZBB-NEXT:    zext.b a0, a0
 ; ZBB-NEXT:    minu a2, a0, a1
 ; ZBB-NEXT:    maxu a0, a0, a1
 ; ZBB-NEXT:    sub a0, a2, a0
@@ -1599,8 +1599,8 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
 define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
 ; NOZBB-LABEL: abd_cmp_i8:
 ; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    andi a2, a0, 255
-; NOZBB-NEXT:    andi a3, a1, 255
+; NOZBB-NEXT:    zext.b a2, a0
+; NOZBB-NEXT:    zext.b a3, a1
 ; NOZBB-NEXT:    bgeu a3, a2, .LBB18_2
 ; NOZBB-NEXT:  # %bb.1:
 ; NOZBB-NEXT:    sub a0, a1, a0
@@ -1611,8 +1611,8 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
 ;
 ; ZBB-LABEL: abd_cmp_i8:
 ; ZBB:       # %bb.0:
-; ZBB-NEXT:    andi a2, a0, 255
-; ZBB-NEXT:    andi a3, a1, 255
+; ZBB-NEXT:    zext.b a2, a0
+; ZBB-NEXT:    zext.b a3, a1
 ; ZBB-NEXT:    bgeu a3, a2, .LBB18_2
 ; ZBB-NEXT:  # %bb.1:
 ; ZBB-NEXT:    sub a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/abdu.ll b/llvm/test/CodeGen/RISCV/abdu.ll
index 7c8638cb461e2..614d9c20ac574 100644
--- a/llvm/test/CodeGen/RISCV/abdu.ll
+++ b/llvm/test/CodeGen/RISCV/abdu.ll
@@ -11,8 +11,8 @@
 define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ; RV32I-LABEL: abd_ext_i8:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a1, a1, 255
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a1, a1
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-N...
[truncated]

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llvmbot commented Mar 28, 2025

@llvm/pr-subscribers-llvm-globalisel

Author: Alex Bradbury (asb)

Changes

The comment shows that at the time we were worried about producing the alias in assembly that might be ingested by a binutils version that doesn't yet support it. binutils gained support over 4 years ago <https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c2137f55ad04e451d834048d4bfec1de2daea20e>. With all the changes in areas such as ELF attributes, if you tried to use LLVM's RISC-V assembler output with a binutils that old then zext.b would be the least of your worries.

Patch is 339.66 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/133502.diff

63 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1-4)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll (+4-4)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll (+3-3)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll (+3-3)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll (+9-9)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll (+10-10)
  • (modified) llvm/test/CodeGen/RISCV/abdu-neg.ll (+28-28)
  • (modified) llvm/test/CodeGen/RISCV/abdu.ll (+33-33)
  • (modified) llvm/test/CodeGen/RISCV/alu8.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll (+16-16)
  • (modified) llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll (+128-128)
  • (modified) llvm/test/CodeGen/RISCV/atomic-rmw.ll (+275-275)
  • (modified) llvm/test/CodeGen/RISCV/atomic-signext.ll (+34-34)
  • (modified) llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll (+18-18)
  • (modified) llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll (+20-20)
  • (modified) llvm/test/CodeGen/RISCV/avgceilu.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/avgflooru.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll (+4-4)
  • (modified) llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/csr-first-use-cost.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll (+18-18)
  • (modified) llvm/test/CodeGen/RISCV/div-by-constant.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/div.ll (+16-16)
  • (modified) llvm/test/CodeGen/RISCV/double-convert.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/float-convert.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/fold-mem-offset.ll (+10-10)
  • (modified) llvm/test/CodeGen/RISCV/half-convert.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/intrinsic-cttz-elts.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/machine-combiner.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/memset-inline.ll (+22-22)
  • (modified) llvm/test/CodeGen/RISCV/overflow-intrinsics.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/pr65025.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rem.ll (+12-12)
  • (modified) llvm/test/CodeGen/RISCV/rv32zbkb.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/rv64zbkb.ll (+6-6)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll (+4-4)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll (+24-24)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll (+68-68)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll (+64-64)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/memset-inline.ll (+10-10)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll (+14-14)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/sext-zext-trunc.ll (+12-12)
  • (modified) llvm/test/CodeGen/RISCV/simplify-condbr.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/split-store.ll (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/typepromotion-overflow.ll (+3-3)
  • (modified) llvm/test/CodeGen/RISCV/uadd_sat_plus.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/usub_sat_plus.ll (+8-8)
  • (modified) llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll (+1-1)
  • (modified) llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll (+1-1)
  • (modified) llvm/test/MC/RISCV/rv32i-aliases-valid.s (+1-1)
  • (modified) llvm/test/MC/RISCV/rv64i-aliases-valid.s (+1-1)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index b61992298ca95..49068780f697d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1118,10 +1118,7 @@ def : MnemonicAlias<"move", "mv">;
 def : MnemonicAlias<"scall", "ecall">;
 def : MnemonicAlias<"sbreak", "ebreak">;
 
-// This alias was added to the spec in December 2020. Don't print it by default
-// to allow assembly we print to be compatible with versions of GNU assembler
-// that don't support this alias.
-def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>;
+def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
 
 let Predicates = [HasStdExtZicfilp] in {
 def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
index f1c0fccb78a36..1632f92e96b50 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
@@ -49,15 +49,15 @@ entry:
 define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) {
 ; RV32IM-LABEL: add_i8_zeroext_i32:
 ; RV32IM:       # %bb.0: # %entry
-; RV32IM-NEXT:    andi a0, a0, 255
-; RV32IM-NEXT:    andi a1, a1, 255
+; RV32IM-NEXT:    zext.b a0, a0
+; RV32IM-NEXT:    zext.b a1, a1
 ; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: add_i8_zeroext_i32:
 ; RV64IM:       # %bb.0: # %entry
-; RV64IM-NEXT:    andi a0, a0, 255
-; RV64IM-NEXT:    andi a1, a1, 255
+; RV64IM-NEXT:    zext.b a0, a0
+; RV64IM-NEXT:    zext.b a1, a1
 ; RV64IM-NEXT:    addw a0, a0, a1
 ; RV64IM-NEXT:    ret
 entry:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll b/llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
index f62902cdd14d9..9c46e6792e8d8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
@@ -227,7 +227,7 @@ define i64 @udiv64_constant_add(i64 %a) nounwind {
 define i8 @udiv8_constant_no_add(i8 %a) nounwind {
 ; RV32-LABEL: udiv8_constant_no_add:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    andi a0, a0, 255
+; RV32-NEXT:    zext.b a0, a0
 ; RV32-NEXT:    li a1, 205
 ; RV32-NEXT:    mul a0, a0, a1
 ; RV32-NEXT:    srli a0, a0, 10
@@ -235,7 +235,7 @@ define i8 @udiv8_constant_no_add(i8 %a) nounwind {
 ;
 ; RV64-LABEL: udiv8_constant_no_add:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    andi a0, a0, 255
+; RV64-NEXT:    zext.b a0, a0
 ; RV64-NEXT:    li a1, 205
 ; RV64-NEXT:    mul a0, a0, a1
 ; RV64-NEXT:    srli a0, a0, 10
@@ -248,28 +248,28 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
 ; RV32-LABEL: udiv8_constant_add:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    li a1, 37
-; RV32-NEXT:    andi a2, a0, 255
+; RV32-NEXT:    zext.b a2, a0
 ; RV32-NEXT:    mul a1, a2, a1
 ; RV32-NEXT:    srli a1, a1, 8
 ; RV32-NEXT:    sub a0, a0, a1
-; RV32-NEXT:    andi a0, a0, 255
+; RV32-NEXT:    zext.b a0, a0
 ; RV32-NEXT:    srli a0, a0, 1
 ; RV32-NEXT:    add a0, a0, a1
-; RV32-NEXT:    andi a0, a0, 255
+; RV32-NEXT:    zext.b a0, a0
 ; RV32-NEXT:    srli a0, a0, 2
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: udiv8_constant_add:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    li a1, 37
-; RV64-NEXT:    andi a2, a0, 255
+; RV64-NEXT:    zext.b a2, a0
 ; RV64-NEXT:    mul a1, a2, a1
 ; RV64-NEXT:    srli a1, a1, 8
 ; RV64-NEXT:    subw a0, a0, a1
-; RV64-NEXT:    andi a0, a0, 255
+; RV64-NEXT:    zext.b a0, a0
 ; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    add a0, a0, a1
-; RV64-NEXT:    andi a0, a0, 255
+; RV64-NEXT:    zext.b a0, a0
 ; RV64-NEXT:    srli a0, a0, 2
 ; RV64-NEXT:    ret
   %1 = udiv i8 %a, 7
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
index aeed219d99555..a49e94f4bc910 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
@@ -855,7 +855,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
 ; CHECKIFD-LABEL: fcvt_wu_s_i8:
 ; CHECKIFD:       # %bb.0:
 ; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
-; CHECKIFD-NEXT:    andi a0, a0, 255
+; CHECKIFD-NEXT:    zext.b a0, a0
 ; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_i8:
@@ -863,7 +863,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunsdfsi
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
@@ -873,7 +873,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixunsdfsi
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
index 1820ecf3b5056..fa093623dd6f8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
@@ -790,7 +790,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
 ; CHECKIF-LABEL: fcvt_wu_s_i8:
 ; CHECKIF:       # %bb.0:
 ; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
-; CHECKIF-NEXT:    andi a0, a0, 255
+; CHECKIF-NEXT:    zext.b a0, a0
 ; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_i8:
@@ -798,7 +798,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
@@ -808,7 +808,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixunssfsi
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll b/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
index e29c450c26cb4..ae9b6cc8948f5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
@@ -469,7 +469,7 @@ define fp128 @uitofp_i8(i8 %x) nounwind {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    call __floatunsitf
 ; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
index ababec16f7f8f..da95481a5e588 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
@@ -327,7 +327,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
 define i8 @srli_i8(i8 %a) nounwind {
 ; CHECK-LABEL: srli_i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    srli a0, a0, 6
 ; CHECK-NEXT:    ret
   %1 = lshr i8 %a, 6
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
index b214cf68ddce8..55cb95413ae24 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
@@ -110,7 +110,7 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: packh_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a2, 16
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    addi a2, a2, -256
 ; CHECK-NEXT:    slli a1, a1, 8
 ; CHECK-NEXT:    and a1, a1, a2
@@ -126,8 +126,8 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind {
 define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: packh_i32_2:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    andi a1, a1, 255
+; RV32I-NEXT:    zext.b a0, a0
+; RV32I-NEXT:    zext.b a1, a1
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
@@ -148,7 +148,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: packh_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a1, 16
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    addi a1, a1, -256
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    and a1, a2, a1
@@ -166,8 +166,8 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: packh_i64_2:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    andi a1, a2, 255
+; RV32I-NEXT:    zext.b a0, a0
+; RV32I-NEXT:    zext.b a1, a2
 ; RV32I-NEXT:    slli a2, a1, 8
 ; RV32I-NEXT:    srli a1, a1, 24
 ; RV32I-NEXT:    or a0, a2, a0
@@ -175,7 +175,7 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
 ;
 ; RV32ZBKB-LABEL: packh_i64_2:
 ; RV32ZBKB:       # %bb.0:
-; RV32ZBKB-NEXT:    andi a1, a2, 255
+; RV32ZBKB-NEXT:    zext.b a1, a2
 ; RV32ZBKB-NEXT:    srli a1, a1, 24
 ; RV32ZBKB-NEXT:    packh a0, a0, a2
 ; RV32ZBKB-NEXT:    ret
@@ -210,7 +210,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
 ; RV32I-LABEL: packh_i16_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    slli a0, a0, 8
 ; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    ret
@@ -232,7 +232,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
 ; RV32I-LABEL: packh_i16_3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a0, a1, a0
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    slli a0, a0, 8
 ; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    sh a0, 0(a3)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
index 79d08772e8853..1eddb8fc2797e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
@@ -405,7 +405,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
 define i8 @srli_i8(i8 %a) nounwind {
 ; CHECK-LABEL: srli_i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andi a0, a0, 255
+; CHECK-NEXT:    zext.b a0, a0
 ; CHECK-NEXT:    srli a0, a0, 6
 ; CHECK-NEXT:    ret
   %1 = lshr i8 %a, 6
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
index 558424b53be95..f413abffcdccc 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
@@ -140,7 +140,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: packh_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 16
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    and a1, a1, a2
@@ -150,7 +150,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64ZBKB-LABEL: packh_i32:
 ; RV64ZBKB:       # %bb.0:
 ; RV64ZBKB-NEXT:    lui a2, 16
-; RV64ZBKB-NEXT:    andi a0, a0, 255
+; RV64ZBKB-NEXT:    zext.b a0, a0
 ; RV64ZBKB-NEXT:    addiw a2, a2, -256
 ; RV64ZBKB-NEXT:    slli a1, a1, 8
 ; RV64ZBKB-NEXT:    and a1, a1, a2
@@ -166,8 +166,8 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
 define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
 ; RV64I-LABEL: packh_i32_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    andi a1, a1, 255
+; RV64I-NEXT:    zext.b a0, a0
+; RV64I-NEXT:    zext.b a1, a1
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
@@ -188,7 +188,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: packh_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, 16
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    and a1, a1, a2
@@ -198,7 +198,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 ; RV64ZBKB-LABEL: packh_i64:
 ; RV64ZBKB:       # %bb.0:
 ; RV64ZBKB-NEXT:    lui a2, 16
-; RV64ZBKB-NEXT:    andi a0, a0, 255
+; RV64ZBKB-NEXT:    zext.b a0, a0
 ; RV64ZBKB-NEXT:    addiw a2, a2, -256
 ; RV64ZBKB-NEXT:    slli a1, a1, 8
 ; RV64ZBKB-NEXT:    and a1, a1, a2
@@ -214,8 +214,8 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
 define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: packh_i64_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    andi a1, a1, 255
+; RV64I-NEXT:    zext.b a0, a0
+; RV64I-NEXT:    zext.b a1, a1
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
@@ -253,7 +253,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
 ; RV64I-LABEL: packh_i16_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    slli a0, a0, 8
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    ret
@@ -275,7 +275,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
 ; RV64I-LABEL: packh_i16_3:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    slli a0, a0, 8
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    sh a0, 0(a3)
diff --git a/llvm/test/CodeGen/RISCV/abdu-neg.ll b/llvm/test/CodeGen/RISCV/abdu-neg.ll
index 9e41cde7ae181..9fa142ee2aa1e 100644
--- a/llvm/test/CodeGen/RISCV/abdu-neg.ll
+++ b/llvm/test/CodeGen/RISCV/abdu-neg.ll
@@ -11,8 +11,8 @@
 define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ; RV32I-LABEL: abd_ext_i8:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a1, a1, 255
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a1, a1
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    xor a0, a0, a1
@@ -21,8 +21,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: abd_ext_i8:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    andi a1, a1, 255
+; RV64I-NEXT:    zext.b a0, a0
+; RV64I-NEXT:    zext.b a1, a1
 ; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    xor a0, a0, a1
@@ -31,8 +31,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ;
 ; RV32ZBB-LABEL: abd_ext_i8:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    andi a1, a1, 255
-; RV32ZBB-NEXT:    andi a0, a0, 255
+; RV32ZBB-NEXT:    zext.b a1, a1
+; RV32ZBB-NEXT:    zext.b a0, a0
 ; RV32ZBB-NEXT:    maxu a2, a0, a1
 ; RV32ZBB-NEXT:    minu a0, a0, a1
 ; RV32ZBB-NEXT:    sub a0, a0, a2
@@ -40,8 +40,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ;
 ; RV64ZBB-LABEL: abd_ext_i8:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    andi a0, a0, 255
-; RV64ZBB-NEXT:    andi a1, a1, 255
+; RV64ZBB-NEXT:    zext.b a0, a0
+; RV64ZBB-NEXT:    zext.b a1, a1
 ; RV64ZBB-NEXT:    sub a0, a0, a1
 ; RV64ZBB-NEXT:    neg a1, a0
 ; RV64ZBB-NEXT:    min a0, a0, a1
@@ -60,7 +60,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a1, 16
 ; RV32I-NEXT:    srli a1, a1, 16
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    xor a0, a0, a1
@@ -69,7 +69,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 ;
 ; RV64I-LABEL: abd_ext_i8_i16:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    zext.b a0, a0
 ; RV64I-NEXT:    slli a1, a1, 48
 ; RV64I-NEXT:    srli a1, a1, 48
 ; RV64I-NEXT:    sub a0, a0, a1
@@ -81,7 +81,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 ; RV32ZBB-LABEL: abd_ext_i8_i16:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    zext.h a1, a1
-; RV32ZBB-NEXT:    andi a0, a0, 255
+; RV32ZBB-NEXT:    zext.b a0, a0
 ; RV32ZBB-NEXT:    maxu a2, a0, a1
 ; RV32ZBB-NEXT:    minu a0, a0, a1
 ; RV32ZBB-NEXT:    sub a0, a0, a2
@@ -89,7 +89,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 ;
 ; RV64ZBB-LABEL: abd_ext_i8_i16:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    andi a0, a0, 255
+; RV64ZBB-NEXT:    zext.b a0, a0
 ; RV64ZBB-NEXT:    zext.h a1, a1
 ; RV64ZBB-NEXT:    sub a0, a0, a1
 ; RV64ZBB-NEXT:    neg a1, a0
@@ -107,8 +107,8 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
 define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
 ; RV32I-LABEL: abd_ext_i8_undef:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a1, a1, 255
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a1, a1
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    xor a0, a0, a1
@@ -117,8 +117,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
 ;
 ; RV64I-LABEL: abd_ext_i8_undef:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    andi a1, a1, 255
+; RV64I-NEXT:    zext.b a0, a0
+; RV64I-NEXT:    zext.b a1, a1
 ; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    xor a0, a0, a1
@@ -127,8 +127,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
 ;
 ; RV32ZBB-LABEL: abd_ext_i8_undef:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    andi a1, a1, 255
-; RV32ZBB-NEXT:    andi a0, a0, 255
+; RV32ZBB-NEXT:    zext.b a1, a1
+; RV32ZBB-NEXT:    zext.b a0, a0
 ; RV32ZBB-NEXT:    maxu a2, a0, a1
 ; RV32ZBB-NEXT:    minu a0, a0, a1
 ; RV32ZBB-NEXT:    sub a0, a0, a2
@@ -136,8 +136,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
 ;
 ; RV64ZBB-LABEL: abd_ext_i8_undef:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    andi a0, a0, 255
-; RV64ZBB-NEXT:    andi a1, a1, 255
+; RV64ZBB-NEXT:    zext.b a0, a0
+; RV64ZBB-NEXT:    zext.b a1, a1
 ; RV64ZBB-NEXT:    sub a0, a0, a1
 ; RV64ZBB-NEXT:    neg a1, a0
 ; RV64ZBB-NEXT:    min a0, a0, a1
@@ -1094,8 +1094,8 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
 define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
 ; NOZBB-LABEL: abd_minmax_i8:
 ; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    andi a1, a1, 255
-; NOZBB-NEXT:    andi a0, a0, 255
+; NOZBB-NEXT:    zext.b a1, a1
+; NOZBB-NEXT:    zext.b a0, a0
 ; NOZBB-NEXT:    mv a2, a0
 ; NOZBB-NEXT:    bgeu a0, a1, .LBB13_3
 ; NOZBB-NEXT:  # %bb.1:
@@ -1112,8 +1112,8 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
 ;
 ; ZBB-LABEL: abd_minmax_i8:
 ; ZBB:       # %bb.0:
-; ZBB-NEXT:    andi a1, a1, 255
-; ZBB-NEXT:    andi a0, a0, 255
+; ZBB-NEXT:    zext.b a1, a1
+; ZBB-NEXT:    zext.b a0, a0
 ; ZBB-NEXT:    minu a2, a0, a1
 ; ZBB-NEXT:    maxu a0, a0, a1
 ; ZBB-NEXT:    sub a0, a2, a0
@@ -1599,8 +1599,8 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
 define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
 ; NOZBB-LABEL: abd_cmp_i8:
 ; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    andi a2, a0, 255
-; NOZBB-NEXT:    andi a3, a1, 255
+; NOZBB-NEXT:    zext.b a2, a0
+; NOZBB-NEXT:    zext.b a3, a1
 ; NOZBB-NEXT:    bgeu a3, a2, .LBB18_2
 ; NOZBB-NEXT:  # %bb.1:
 ; NOZBB-NEXT:    sub a0, a1, a0
@@ -1611,8 +1611,8 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
 ;
 ; ZBB-LABEL: abd_cmp_i8:
 ; ZBB:       # %bb.0:
-; ZBB-NEXT:    andi a2, a0, 255
-; ZBB-NEXT:    andi a3, a1, 255
+; ZBB-NEXT:    zext.b a2, a0
+; ZBB-NEXT:    zext.b a3, a1
 ; ZBB-NEXT:    bgeu a3, a2, .LBB18_2
 ; ZBB-NEXT:  # %bb.1:
 ; ZBB-NEXT:    sub a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/abdu.ll b/llvm/test/CodeGen/RISCV/abdu.ll
index 7c8638cb461e2..614d9c20ac574 100644
--- a/llvm/test/CodeGen/RISCV/abdu.ll
+++ b/llvm/test/CodeGen/RISCV/abdu.ll
@@ -11,8 +11,8 @@
 define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
 ; RV32I-LABEL: abd_ext_i8:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a1, a1, 255
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    zext.b a1, a1
+; RV32I-NEXT:    zext.b a0, a0
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-N...
[truncated]

topperc
topperc approved these changes Mar 28, 2025
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LGTM

@asb asb merged commit 4e4cb43 into llvm:main Mar 28, 2025
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@lenary lenary lenary approved these changes

@topperc topperc topperc approved these changes

@preames preames Awaiting requested review from preames

@kito-cheng kito-cheng Awaiting requested review from kito-cheng

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@asb @llvmbot @lenary @topperc