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[RISCV][MC] Enable printing of zext.b alias #133502

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asb merged 1 commit into from
Mar 28, 2025
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[RISCV][MC] Enable printing of zext.b alias #133502

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5 changes: 1 addition & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -1118,10 +1118,7 @@ def : MnemonicAlias<"move", "mv">;
def : MnemonicAlias<"scall", "ecall">;
def : MnemonicAlias<"sbreak", "ebreak">;

// This alias was added to the spec in December 2020. Don't print it by default
// to allow assembly we print to be compatible with versions of GNU assembler
// that don't support this alias.
def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>;
def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;

let Predicates = [HasStdExtZicfilp] in {
def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>;
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
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Expand Up @@ -49,15 +49,15 @@ entry:
define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) {
; RV32IM-LABEL: add_i8_zeroext_i32:
; RV32IM: # %bb.0: # %entry
; RV32IM-NEXT: andi a0, a0, 255
; RV32IM-NEXT: andi a1, a1, 255
; RV32IM-NEXT: zext.b a0, a0
; RV32IM-NEXT: zext.b a1, a1
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64IM-LABEL: add_i8_zeroext_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: andi a0, a0, 255
; RV64IM-NEXT: andi a1, a1, 255
; RV64IM-NEXT: zext.b a0, a0
; RV64IM-NEXT: zext.b a1, a1
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
entry:
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
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Expand Up @@ -227,15 +227,15 @@ define i64 @udiv64_constant_add(i64 %a) nounwind {
define i8 @udiv8_constant_no_add(i8 %a) nounwind {
; RV32-LABEL: udiv8_constant_no_add:
; RV32: # %bb.0:
; RV32-NEXT: andi a0, a0, 255
; RV32-NEXT: zext.b a0, a0
; RV32-NEXT: li a1, 205
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: srli a0, a0, 10
; RV32-NEXT: ret
;
; RV64-LABEL: udiv8_constant_no_add:
; RV64: # %bb.0:
; RV64-NEXT: andi a0, a0, 255
; RV64-NEXT: zext.b a0, a0
; RV64-NEXT: li a1, 205
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: srli a0, a0, 10
Expand All @@ -248,28 +248,28 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
; RV32-LABEL: udiv8_constant_add:
; RV32: # %bb.0:
; RV32-NEXT: li a1, 37
; RV32-NEXT: andi a2, a0, 255
; RV32-NEXT: zext.b a2, a0
; RV32-NEXT: mul a1, a2, a1
; RV32-NEXT: srli a1, a1, 8
; RV32-NEXT: sub a0, a0, a1
; RV32-NEXT: andi a0, a0, 255
; RV32-NEXT: zext.b a0, a0
; RV32-NEXT: srli a0, a0, 1
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: andi a0, a0, 255
; RV32-NEXT: zext.b a0, a0
; RV32-NEXT: srli a0, a0, 2
; RV32-NEXT: ret
;
; RV64-LABEL: udiv8_constant_add:
; RV64: # %bb.0:
; RV64-NEXT: li a1, 37
; RV64-NEXT: andi a2, a0, 255
; RV64-NEXT: zext.b a2, a0
; RV64-NEXT: mul a1, a2, a1
; RV64-NEXT: srli a1, a1, 8
; RV64-NEXT: subw a0, a0, a1
; RV64-NEXT: andi a0, a0, 255
; RV64-NEXT: zext.b a0, a0
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: andi a0, a0, 255
; RV64-NEXT: zext.b a0, a0
; RV64-NEXT: srli a0, a0, 2
; RV64-NEXT: ret
%1 = udiv i8 %a, 7
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
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Expand Up @@ -855,15 +855,15 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
; CHECKIFD-LABEL: fcvt_wu_s_i8:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
; CHECKIFD-NEXT: andi a0, a0, 255
; CHECKIFD-NEXT: zext.b a0, a0
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __fixunsdfsi
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -873,7 +873,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunsdfsi
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
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Expand Up @@ -790,15 +790,15 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
; CHECKIF-LABEL: fcvt_wu_s_i8:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
; CHECKIF-NEXT: andi a0, a0, 255
; CHECKIF-NEXT: zext.b a0, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_i8:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __fixunssfsi
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -808,7 +808,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunssfsi
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
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Expand Up @@ -469,7 +469,7 @@ define fp128 @uitofp_i8(i8 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: zext.b a0, a0
; CHECK-NEXT: call __floatunsitf
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
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Expand Up @@ -327,7 +327,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
define i8 @srli_i8(i8 %a) nounwind {
; CHECK-LABEL: srli_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: zext.b a0, a0
; CHECK-NEXT: srli a0, a0, 6
; CHECK-NEXT: ret
%1 = lshr i8 %a, 6
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18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
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Expand Up @@ -110,7 +110,7 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: packh_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a2, 16
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: zext.b a0, a0
; CHECK-NEXT: addi a2, a2, -256
; CHECK-NEXT: slli a1, a1, 8
; CHECK-NEXT: and a1, a1, a2
Expand All @@ -126,8 +126,8 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind {
define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: packh_i32_2:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: andi a1, a1, 255
; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: zext.b a1, a1
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
Expand All @@ -148,7 +148,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: packh_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 16
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: zext.b a0, a0
; CHECK-NEXT: addi a1, a1, -256
; CHECK-NEXT: slli a2, a2, 8
; CHECK-NEXT: and a1, a2, a1
Expand All @@ -166,16 +166,16 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packh_i64_2:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: andi a1, a2, 255
; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: zext.b a1, a2
; RV32I-NEXT: slli a2, a1, 8
; RV32I-NEXT: srli a1, a1, 24
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: ret
;
; RV32ZBKB-LABEL: packh_i64_2:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: andi a1, a2, 255
; RV32ZBKB-NEXT: zext.b a1, a2
; RV32ZBKB-NEXT: srli a1, a1, 24
; RV32ZBKB-NEXT: packh a0, a0, a2
; RV32ZBKB-NEXT: ret
Expand Down Expand Up @@ -210,7 +210,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
; RV32I-LABEL: packh_i16_2:
; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: ret
Expand All @@ -232,7 +232,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
; RV32I-LABEL: packh_i16_3:
; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: zext.b a0, a0
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: sh a0, 0(a3)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
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Expand Up @@ -405,7 +405,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
define i8 @srli_i8(i8 %a) nounwind {
; CHECK-LABEL: srli_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 255
; CHECK-NEXT: zext.b a0, a0
; CHECK-NEXT: srli a0, a0, 6
; CHECK-NEXT: ret
%1 = lshr i8 %a, 6
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20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
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Expand Up @@ -140,7 +140,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: packh_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: and a1, a1, a2
Expand All @@ -150,7 +150,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64ZBKB-LABEL: packh_i32:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: lui a2, 16
; RV64ZBKB-NEXT: andi a0, a0, 255
; RV64ZBKB-NEXT: zext.b a0, a0
; RV64ZBKB-NEXT: addiw a2, a2, -256
; RV64ZBKB-NEXT: slli a1, a1, 8
; RV64ZBKB-NEXT: and a1, a1, a2
Expand All @@ -166,8 +166,8 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: packh_i32_2:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: andi a1, a1, 255
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: zext.b a1, a1
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
Expand All @@ -188,7 +188,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: packh_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: and a1, a1, a2
Expand All @@ -198,7 +198,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV64ZBKB-LABEL: packh_i64:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: lui a2, 16
; RV64ZBKB-NEXT: andi a0, a0, 255
; RV64ZBKB-NEXT: zext.b a0, a0
; RV64ZBKB-NEXT: addiw a2, a2, -256
; RV64ZBKB-NEXT: slli a1, a1, 8
; RV64ZBKB-NEXT: and a1, a1, a2
Expand All @@ -214,8 +214,8 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: packh_i64_2:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: andi a1, a1, 255
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: zext.b a1, a1
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
Expand Down Expand Up @@ -253,7 +253,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
; RV64I-LABEL: packh_i16_2:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: slli a0, a0, 8
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: ret
Expand All @@ -275,7 +275,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
; RV64I-LABEL: packh_i16_3:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: zext.b a0, a0
; RV64I-NEXT: slli a0, a0, 8
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: sh a0, 0(a3)
Expand Down
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