diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 275d0193452a5..50ba7134f5a44 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -2103,7 +2103,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, getActionDefinitionsBuilder({G_MEMCPY, G_MEMCPY_INLINE, G_MEMMOVE, G_MEMSET}) .lower(); - getActionDefinitionsBuilder({G_TRAP, G_DEBUGTRAP}).custom(); + getActionDefinitionsBuilder({G_TRAP, G_DEBUGTRAP, G_UBSANTRAP}).custom(); getActionDefinitionsBuilder({G_VASTART, G_VAARG, G_BRJT, G_JUMP_TABLE, G_INDEXED_LOAD, G_INDEXED_SEXTLOAD, @@ -2221,7 +2221,9 @@ bool AMDGPULegalizerInfo::legalizeCustom( case TargetOpcode::G_TRAP: return legalizeTrap(MI, MRI, B); case TargetOpcode::G_DEBUGTRAP: - return legalizeDebugTrap(MI, MRI, B); + return legalizeDebugUbsanTrap(MI, MRI, B, TargetOpcode::G_DEBUGTRAP); + case TargetOpcode::G_UBSANTRAP: + return legalizeDebugUbsanTrap(MI, MRI, B, TargetOpcode::G_UBSANTRAP); default: return false; } @@ -7023,22 +7025,26 @@ bool AMDGPULegalizerInfo::legalizeTrapHsa(MachineInstr &MI, return true; } -bool AMDGPULegalizerInfo::legalizeDebugTrap(MachineInstr &MI, - MachineRegisterInfo &MRI, - MachineIRBuilder &B) const { +bool AMDGPULegalizerInfo::legalizeDebugUbsanTrap(MachineInstr &MI, + MachineRegisterInfo &MRI, + MachineIRBuilder &B, + unsigned int Opcode) const { // Is non-HSA path or trap-handler disabled? Then, report a warning // accordingly if (!ST.isTrapHandlerEnabled() || ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) { - DiagnosticInfoUnsupported NoTrap(B.getMF().getFunction(), - "debugtrap handler not supported", - MI.getDebugLoc(), DS_Warning); + DiagnosticInfoUnsupported NoTrap( + B.getMF().getFunction(), "debugtrap/ubsantrap handler not supported", + MI.getDebugLoc(), DS_Warning); LLVMContext &Ctx = B.getMF().getFunction().getContext(); Ctx.diagnose(NoTrap); - } else { + } else if (Opcode == TargetOpcode::G_DEBUGTRAP) { // Insert debug-trap instruction B.buildInstr(AMDGPU::S_TRAP) .addImm(static_cast(GCNSubtarget::TrapID::LLVMAMDHSADebugTrap)); + } else if (Opcode == TargetOpcode::G_UBSANTRAP) { + B.buildInstr(AMDGPU::S_TRAP) + .addImm(static_cast(GCNSubtarget::TrapID::LLVMAMDHSATrap)); } MI.eraseFromParent(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h index 1f4e02b0d600a..b745562ff6a3a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h @@ -241,8 +241,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo { MachineIRBuilder &B) const; bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const; - bool legalizeDebugTrap(MachineInstr &MI, MachineRegisterInfo &MRI, - MachineIRBuilder &B) const; + bool legalizeDebugUbsanTrap(MachineInstr &MI, MachineRegisterInfo &MRI, + MachineIRBuilder &B, unsigned int Opcode) const; bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 21f8c7cfeec1f..07da7c121befc 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -7283,9 +7283,9 @@ SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const { if (!Subtarget->isTrapHandlerEnabled() || Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) { - DiagnosticInfoUnsupported NoTrap(MF.getFunction(), - "debugtrap handler not supported", - Op.getDebugLoc(), DS_Warning); + DiagnosticInfoUnsupported NoTrap( + MF.getFunction(), "debugtrap/ubsantrap handler not supported", + Op.getDebugLoc(), DS_Warning); LLVMContext &Ctx = MF.getFunction().getContext(); Ctx.diagnose(NoTrap); return Chain; diff --git a/llvm/test/CodeGen/AMDGPU/trap-abis.ll b/llvm/test/CodeGen/AMDGPU/trap-abis.ll index b8f0d7617167e..dcdf9962d2ffe 100644 --- a/llvm/test/CodeGen/AMDGPU/trap-abis.ll +++ b/llvm/test/CodeGen/AMDGPU/trap-abis.ll @@ -8,6 +8,7 @@ declare void @llvm.trap() #0 declare void @llvm.debugtrap() #1 +declare void @llvm.ubsantrap(i8) #2 define amdgpu_kernel void @trap(ptr addrspace(1) nocapture readonly %arg0) { ; NOHSA-TRAP-GFX900-LABEL: trap: @@ -482,6 +483,134 @@ define amdgpu_kernel void @debugtrap(ptr addrspace(1) nocapture readonly %arg0) ret void } +define void @ubsan_trap(ptr addrspace(1) nocapture readonly %arg0) { +; CHECK-LABEL: ubsan_trap: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_trap 2 +; CHECK-NEXT: s_setpc_b64 s[30:31] +; NOHSA-TRAP-GFX900-LABEL: ubsan_trap: +; NOHSA-TRAP-GFX900: ; %bb.0: +; NOHSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; NOHSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 1 +; NOHSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off +; NOHSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) +; NOHSA-TRAP-GFX900-NEXT: s_cbranch_execnz .LBB4_2 +; NOHSA-TRAP-GFX900-NEXT: ; %bb.1: +; NOHSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 2 +; NOHSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off +; NOHSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) +; NOHSA-TRAP-GFX900-NEXT: s_setpc_b64 s[30:31] +; NOHSA-TRAP-GFX900-NEXT: .LBB4_2: +; NOHSA-TRAP-GFX900-NEXT: s_endpgm +; +; HSA-TRAP-GFX803-LABEL: ubsan_trap: +; HSA-TRAP-GFX803: ; %bb.0: +; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v2, 1 +; HSA-TRAP-GFX803-NEXT: flat_store_dword v[0:1], v2 +; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0) +; HSA-TRAP-GFX803-NEXT: v_mov_b32_e32 v2, 2 +; HSA-TRAP-GFX803-NEXT: s_mov_b64 s[0:1], s[6:7] +; HSA-TRAP-GFX803-NEXT: s_trap 2 +; HSA-TRAP-GFX803-NEXT: flat_store_dword v[0:1], v2 +; HSA-TRAP-GFX803-NEXT: s_waitcnt vmcnt(0) +; HSA-TRAP-GFX803-NEXT: s_setpc_b64 s[30:31] +; +; HSA-TRAP-GFX900-LABEL: ubsan_trap: +; HSA-TRAP-GFX900: ; %bb.0: +; HSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 1 +; HSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off +; HSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) +; HSA-TRAP-GFX900-NEXT: v_mov_b32_e32 v2, 2 +; HSA-TRAP-GFX900-NEXT: s_trap 2 +; HSA-TRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off +; HSA-TRAP-GFX900-NEXT: s_waitcnt vmcnt(0) +; HSA-TRAP-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; HSA-NOTRAP-GFX900-LABEL: ubsan_trap: +; HSA-NOTRAP-GFX900: ; %bb.0: +; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-NOTRAP-GFX900-NEXT: v_mov_b32_e32 v2, 1 +; HSA-NOTRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off +; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0) +; HSA-NOTRAP-GFX900-NEXT: s_cbranch_execnz .LBB4_2 +; HSA-NOTRAP-GFX900-NEXT: ; %bb.1: +; HSA-NOTRAP-GFX900-NEXT: v_mov_b32_e32 v2, 2 +; HSA-NOTRAP-GFX900-NEXT: global_store_dword v[0:1], v2, off +; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0) +; HSA-NOTRAP-GFX900-NEXT: s_setpc_b64 s[30:31] +; HSA-NOTRAP-GFX900-NEXT: .LBB4_2: +; HSA-NOTRAP-GFX900-NEXT: s_endpgm +; +; HSA-TRAP-GFX1100-LABEL: ubsan_trap: +; HSA-TRAP-GFX1100: ; %bb.0: +; HSA-TRAP-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-TRAP-GFX1100-NEXT: v_mov_b32_e32 v2, 1 +; HSA-TRAP-GFX1100-NEXT: global_store_b32 v[0:1], v2, off dlc +; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-NEXT: s_cbranch_execnz .LBB4_2 +; HSA-TRAP-GFX1100-NEXT: ; %bb.1: +; HSA-TRAP-GFX1100-NEXT: v_mov_b32_e32 v2, 2 +; HSA-TRAP-GFX1100-NEXT: global_store_b32 v[0:1], v2, off dlc +; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-NEXT: s_setpc_b64 s[30:31] +; HSA-TRAP-GFX1100-NEXT: .LBB4_2: +; HSA-TRAP-GFX1100-NEXT: s_trap 2 +; HSA-TRAP-GFX1100-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL) +; HSA-TRAP-GFX1100-NEXT: s_mov_b32 ttmp2, m0 +; HSA-TRAP-GFX1100-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-NEXT: s_and_b32 s0, s0, 0x3ff +; HSA-TRAP-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; HSA-TRAP-GFX1100-NEXT: s_bitset1_b32 s0, 10 +; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, s0 +; HSA-TRAP-GFX1100-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT) +; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, ttmp2 +; HSA-TRAP-GFX1100-NEXT: .LBB4_3: ; =>This Inner Loop Header: Depth=1 +; HSA-TRAP-GFX1100-NEXT: s_sethalt 5 +; HSA-TRAP-GFX1100-NEXT: s_branch .LBB4_3 +; +; HSA-TRAP-GFX1100-O0-LABEL: ubsan_trap: +; HSA-TRAP-GFX1100-O0: ; %bb.0: +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, v1 +; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr0 +; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr0 +; HSA-TRAP-GFX1100-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec +; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v1, v2 +; HSA-TRAP-GFX1100-O0-NEXT: scratch_store_b64 off, v[0:1], s32 ; 8-byte Folded Spill +; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr0_sgpr1 +; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, 1 +; HSA-TRAP-GFX1100-O0-NEXT: global_store_b32 v[0:1], v2, off dlc +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-O0-NEXT: s_cbranch_execnz .LBB4_2 +; HSA-TRAP-GFX1100-O0-NEXT: ; %bb.1: +; HSA-TRAP-GFX1100-O0-NEXT: scratch_load_b64 v[0:1], off, s32 ; 8-byte Folded Reload +; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, 2 +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt vmcnt(0) +; HSA-TRAP-GFX1100-O0-NEXT: global_store_b32 v[0:1], v2, off dlc +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-O0-NEXT: s_setpc_b64 s[30:31] +; HSA-TRAP-GFX1100-O0-NEXT: .LBB4_2: +; HSA-TRAP-GFX1100-O0-NEXT: s_trap 2 +; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL) +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 ttmp2, m0 +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-O0-NEXT: s_and_b32 s0, s0, 0x3ff +; HSA-TRAP-GFX1100-O0-NEXT: s_or_b32 s0, s0, 0x400 +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, s0 +; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT) +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, ttmp2 +; HSA-TRAP-GFX1100-O0-NEXT: .LBB4_3: ; =>This Inner Loop Header: Depth=1 +; HSA-TRAP-GFX1100-O0-NEXT: s_sethalt 5 +; HSA-TRAP-GFX1100-O0-NEXT: s_branch .LBB4_3 + store volatile i32 1, ptr addrspace(1) %arg0 + call void @llvm.ubsantrap(i8 0) + store volatile i32 2, ptr addrspace(1) %arg0 + ret void +} + attributes #0 = { nounwind noreturn } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll index 9bab3e6fcf8c4..259d0646c4caa 100644 --- a/llvm/test/CodeGen/AMDGPU/trap.ll +++ b/llvm/test/CodeGen/AMDGPU/trap.ll @@ -23,11 +23,12 @@ ; RUN: llc -global-isel=0 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s ; RUN: llc -global-isel=1 -mtriple=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s -; GCN-WARNING: warning: :0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap handler not supported +; GCN-WARNING: warning: :0:0: in function hsa_debugtrap void (ptr addrspace(1)): debugtrap/ubsantrap handler not supported declare void @llvm.trap() #0 declare void @llvm.debugtrap() #1 +declare void @llvm.ubsantrap(i8) #2 ; MESA-TRAP: .section .AMDGPU.config ; MESA-TRAP: .long 47180 @@ -83,6 +84,32 @@ define amdgpu_kernel void @hsa_debugtrap(ptr addrspace(1) nocapture readonly %ar ret void } +; MESA-TRAP: .section .AMDGPU.config +; MESA-TRAP: .long 47180 +; MESA-TRAP-NEXT: .long 5080 + +; NOMESA-TRAP: .section .AMDGPU.config +; NOMESA-TRAP: .long 47180 +; NOMESA-TRAP-NEXT: .long 5016 + +; GCN-LABEL: {{^}}ubsantrap: +; HSA-TRAP: s_trap 2 +; HSA-TRAP: flat_store_dword v[0:1], v3 +; HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 + +; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction +; NO-HSA-TRAP: s_endpgm + +; TRAP-BIT: enable_trap_handler = 1 +; NO-TRAP-BIT: enable_trap_handler = 0 +; NO-MESA-TRAP: s_endpgm +define amdgpu_kernel void @ubsantrap(ptr addrspace(1) nocapture readonly %arg0) { + store volatile i32 1, ptr addrspace(1) %arg0 + call void @llvm.ubsantrap(i8 0) + store volatile i32 2, ptr addrspace(1) %arg0 + ret void +} + ; For non-HSA path ; GCN-LABEL: {{^}}trap: ; TRAP-BIT: enable_trap_handler = 1