From 52e39310fe8101e642ab8f40f5ad4a7b13ea8ea7 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Fri, 11 Apr 2025 11:51:50 +0800 Subject: [PATCH 1/2] [RISCV] Add TuneNoDefaultUnroll to generic CPUs Almost all CPUs have added this. We may enable it by default and remove this feature. Fixes #134272. --- llvm/lib/Target/RISCV/RISCVProcessors.td | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 32f4ab607a34c..64d15a78f2508 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -86,7 +86,8 @@ class RISCVTuneProcessorModel f = []> : ProcessorModel; -defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore]; +defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore, + TuneNoDefaultUnroll]; def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32", NoSchedModel, From b45bf775c56640ab7b6d67c35c37c562ae9b93ae Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Mon, 14 Apr 2025 19:41:49 +0800 Subject: [PATCH 2/2] Set DefaultUnrollRuntimeCount to 4 for in-oder --- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 0093c92ea5ef0..51029a3592d64 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -2652,6 +2652,10 @@ void RISCVTTIImpl::getUnrollingPreferences( // taken cost of the backedge. if (Cost < 12) UP.Force = true; + + // Set a lower runtime unrolling count for in-order models. + if (!ST->getSchedModel().isOutOfOrder()) + UP.DefaultUnrollRuntimeCount = 4; } void RISCVTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,