From 5810a47933c6e5b05aa5e7cfcf08821f69419907 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Tue, 15 Apr 2025 07:45:42 +0700 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?= =?UTF-8?q?anges=20to=20main=20this=20commit=20is=20based=20on?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.5 [skip ci] --- llvm/lib/Target/Sparc/SparcISelLowering.cpp | 11 ++ llvm/lib/Target/Sparc/SparcISelLowering.h | 3 + llvm/lib/Target/Sparc/SparcInstr64Bit.td | 2 + llvm/lib/Target/Sparc/SparcInstrVIS.td | 22 +++- llvm/test/CodeGen/SPARC/2011-01-11-CC.ll | 118 ++++++++++++++++++++ llvm/test/CodeGen/SPARC/float-constants.ll | 115 +++++++++++++++++++ 6 files changed, 269 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 85b8750d40f46..098e5f22834f4 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1737,6 +1737,11 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SUBC, MVT::i32, Legal); setOperationAction(ISD::SUBE, MVT::i32, Legal); + if (Subtarget->isVIS3()) { + setOperationAction(ISD::ADDC, MVT::i64, Legal); + setOperationAction(ISD::ADDE, MVT::i64, Legal); + } + if (Subtarget->is64Bit()) { setOperationAction(ISD::BITCAST, MVT::f64, Expand); setOperationAction(ISD::BITCAST, MVT::i64, Expand); @@ -3560,6 +3565,12 @@ bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const { return true; } +bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, + bool ForCodeSize) const { + return Subtarget->isVIS() && (VT == MVT::f32 || VT == MVT::f64) && + Imm.isZero(); +} + // Override to disable global variable loading on Linux. void SparcTargetLowering::insertSSPDeclarations(Module &M) const { if (!Subtarget->isTargetLinux()) diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h index 1bee5f4cfe84d..c09e465f5d05e 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.h +++ b/llvm/lib/Target/Sparc/SparcISelLowering.h @@ -207,6 +207,9 @@ namespace llvm { return VT != MVT::f128; } + bool isFPImmLegal(const APFloat &Imm, EVT VT, + bool ForCodeSize) const override; + bool shouldInsertFencesForAtomic(const Instruction *I) const override { // FIXME: We insert fences for each atomics and generate // sub-optimal code for PSO/TSO. (Approximately nobody uses any diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td index 56fab2f26a19e..000612534e89d 100644 --- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -157,9 +157,11 @@ def : Pat<(and i64:$lhs, (not i64:$rhs)), (ANDNrr $lhs, $rhs)>; def : Pat<(or i64:$lhs, (not i64:$rhs)), (ORNrr $lhs, $rhs)>; def : Pat<(not (xor i64:$lhs, i64:$rhs)), (XNORrr $lhs, $rhs)>; +def : Pat<(addc i64:$lhs, i64:$rhs), (ADDCCrr $lhs, $rhs)>, Requires<[HasVIS3]>; def : Pat<(add i64:$lhs, i64:$rhs), (ADDrr $lhs, $rhs)>; def : Pat<(sub i64:$lhs, i64:$rhs), (SUBrr $lhs, $rhs)>; +def : Pat<(addc i64:$lhs, (i64 simm13:$rhs)), (ADDCCri $lhs, imm:$rhs)>, Requires<[HasVIS3]>; def : Pat<(add i64:$lhs, (i64 simm13:$rhs)), (ADDri $lhs, imm:$rhs)>; def : Pat<(sub i64:$lhs, (i64 simm13:$rhs)), (SUBri $lhs, imm:$rhs)>; diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td index 8ce8f37f34040..0e3d9fc8b6da4 100644 --- a/llvm/lib/Target/Sparc/SparcInstrVIS.td +++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td @@ -45,10 +45,10 @@ class VISInst2 opfval, string OpcStr, RegisterClass RC = DFPRegs> !strconcat(OpcStr, " $rs2, $rd")>; // For VIS Instructions with only rd operand. -let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in +let rs1 = 0, rs2 = 0 in class VISInstD opfval, string OpcStr, RegisterClass RC = DFPRegs> : VISInstFormat; // VIS 1 Instructions @@ -277,3 +277,21 @@ def UMULXHI : VISInst<0b000010110, "umulxhi", I64Regs>; def XMULX : VISInst<0b100010101, "xmulx", I64Regs>; def XMULXHI : VISInst<0b100010110, "xmulxhi", I64Regs>; } // Predicates = [IsVIS3] + +// FP immediate patterns. +def fpimm0 : PatLeaf<(fpimm), [{return N->isExactlyValue(+0.0);}]>; +def fpnegimm0 : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>; + +// VIS instruction patterns. +let Predicates = [HasVIS] in { +// Zero immediate. +def : Pat<(f64 fpimm0), (FZERO)>; +def : Pat<(f32 fpimm0), (FZEROS)>; +def : Pat<(f64 fpnegimm0), (FNEGD (FZERO))>; +def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>; +} // Predicates = [HasVIS] + +// VIS3 instruction patterns. +let Predicates = [HasVIS3] in { +def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>; +} // Predicates = [HasVIS3] diff --git a/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll b/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll index 1560bc687b7dd..e05c47bfee766 100644 --- a/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll +++ b/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll @@ -2,6 +2,7 @@ ; RUN: llc -mtriple=sparc %s -o - | FileCheck %s -check-prefix=V8 ; RUN: llc -mtriple=sparc -mattr=v9 %s -o - | FileCheck %s -check-prefix=V9 ; RUN: llc -mtriple=sparc64-unknown-linux %s -o - | FileCheck %s -check-prefix=SPARC64 +; RUN: llc -mtriple=sparc64-unknown-linux -mattr=vis3 %s -o - | FileCheck %s -check-prefix=SPARC64-VIS3 define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind { ; V8-LABEL: test_addx: @@ -60,6 +61,15 @@ define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind { ; SPARC64-NEXT: movgu %xcc, 1, %o3 ; SPARC64-NEXT: retl ; SPARC64-NEXT: srl %o3, 0, %o0 +; +; SPARC64-VIS3-LABEL: test_addx: +; SPARC64-VIS3: ! %bb.0: ! %entry +; SPARC64-VIS3-NEXT: mov %g0, %o3 +; SPARC64-VIS3-NEXT: add %o0, %o1, %o0 +; SPARC64-VIS3-NEXT: cmp %o0, %o2 +; SPARC64-VIS3-NEXT: movgu %xcc, 1, %o3 +; SPARC64-VIS3-NEXT: retl +; SPARC64-VIS3-NEXT: srl %o3, 0, %o0 entry: %0 = add i64 %a, %b %1 = icmp ugt i64 %0, %c @@ -92,6 +102,13 @@ define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind { ; SPARC64-NEXT: move %icc, %o1, %o2 ; SPARC64-NEXT: retl ; SPARC64-NEXT: mov %o2, %o0 +; +; SPARC64-VIS3-LABEL: test_select_int_icc: +; SPARC64-VIS3: ! %bb.0: ! %entry +; SPARC64-VIS3-NEXT: cmp %o0, 0 +; SPARC64-VIS3-NEXT: move %icc, %o1, %o2 +; SPARC64-VIS3-NEXT: retl +; SPARC64-VIS3-NEXT: mov %o2, %o0 entry: %0 = icmp eq i32 %a, 0 %1 = select i1 %0, i32 %b, i32 %c @@ -133,6 +150,13 @@ define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind { ; SPARC64-NEXT: cmp %o0, 0 ; SPARC64-NEXT: retl ; SPARC64-NEXT: fmovse %icc, %f3, %f0 +; +; SPARC64-VIS3-LABEL: test_select_fp_icc: +; SPARC64-VIS3: ! %bb.0: ! %entry +; SPARC64-VIS3-NEXT: fmovs %f5, %f0 +; SPARC64-VIS3-NEXT: cmp %o0, 0 +; SPARC64-VIS3-NEXT: retl +; SPARC64-VIS3-NEXT: fmovse %icc, %f3, %f0 entry: %0 = icmp eq i32 %a, 0 %1 = select i1 %0, float %f1, float %f2 @@ -182,6 +206,13 @@ define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind { ; SPARC64-NEXT: cmp %o0, 0 ; SPARC64-NEXT: retl ; SPARC64-NEXT: fmovde %icc, %f2, %f0 +; +; SPARC64-VIS3-LABEL: test_select_dfp_icc: +; SPARC64-VIS3: ! %bb.0: ! %entry +; SPARC64-VIS3-NEXT: fmovd %f4, %f0 +; SPARC64-VIS3-NEXT: cmp %o0, 0 +; SPARC64-VIS3-NEXT: retl +; SPARC64-VIS3-NEXT: fmovde %icc, %f2, %f0 entry: %0 = icmp eq i32 %a, 0 %1 = select i1 %0, double %f1, double %f2 @@ -229,6 +260,17 @@ define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind { ; SPARC64-NEXT: fcmps %fcc0, %f1, %f0 ; SPARC64-NEXT: retl ; SPARC64-NEXT: movne %fcc0, %o1, %o0 +; +; SPARC64-VIS3-LABEL: test_select_int_fcc: +; SPARC64-VIS3: ! %bb.0: ! %entry +; SPARC64-VIS3-NEXT: sethi %h44(.LCPI4_0), %o0 +; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI4_0), %o0 +; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0 +; SPARC64-VIS3-NEXT: ld [%o0+%l44(.LCPI4_0)], %f0 +; SPARC64-VIS3-NEXT: mov %o2, %o0 +; SPARC64-VIS3-NEXT: fcmps %fcc0, %f1, %f0 +; SPARC64-VIS3-NEXT: retl +; SPARC64-VIS3-NEXT: movne %fcc0, %o1, %o0 entry: %0 = fcmp une float %f, 0.000000e+00 %a.b = select i1 %0, i32 %a, i32 %b @@ -284,6 +326,17 @@ define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind { ; SPARC64-NEXT: fcmps %fcc0, %f1, %f2 ; SPARC64-NEXT: retl ; SPARC64-NEXT: fmovsne %fcc0, %f3, %f0 +; +; SPARC64-VIS3-LABEL: test_select_fp_fcc: +; SPARC64-VIS3: ! %bb.0: ! %entry +; SPARC64-VIS3-NEXT: sethi %h44(.LCPI5_0), %o0 +; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI5_0), %o0 +; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0 +; SPARC64-VIS3-NEXT: ld [%o0+%l44(.LCPI5_0)], %f2 +; SPARC64-VIS3-NEXT: fmovs %f5, %f0 +; SPARC64-VIS3-NEXT: fcmps %fcc0, %f1, %f2 +; SPARC64-VIS3-NEXT: retl +; SPARC64-VIS3-NEXT: fmovsne %fcc0, %f3, %f0 entry: %0 = fcmp une float %f, 0.000000e+00 %1 = select i1 %0, float %f1, float %f2 @@ -352,6 +405,18 @@ define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind { ; SPARC64-NEXT: fmovd %f4, %f0 ; SPARC64-NEXT: retl ; SPARC64-NEXT: nop +; +; SPARC64-VIS3-LABEL: test_select_dfp_fcc: +; SPARC64-VIS3: ! %bb.0: ! %entry +; SPARC64-VIS3-NEXT: sethi %h44(.LCPI6_0), %o0 +; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI6_0), %o0 +; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0 +; SPARC64-VIS3-NEXT: ldd [%o0+%l44(.LCPI6_0)], %f6 +; SPARC64-VIS3-NEXT: fcmpd %fcc0, %f0, %f6 +; SPARC64-VIS3-NEXT: fmovdne %fcc0, %f2, %f4 +; SPARC64-VIS3-NEXT: fmovd %f4, %f0 +; SPARC64-VIS3-NEXT: retl +; SPARC64-VIS3-NEXT: nop entry: %0 = fcmp une double %f, 0.000000e+00 %1 = select i1 %0, double %f1, double %f2 @@ -453,6 +518,31 @@ define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) nounwind { ; SPARC64-NEXT: ! %bb.4: ! %exit.0 ; SPARC64-NEXT: retl ; SPARC64-NEXT: mov %g0, %o0 +; +; SPARC64-VIS3-LABEL: test_float_cc: +; SPARC64-VIS3: ! %bb.0: ! %entry +; SPARC64-VIS3-NEXT: sethi %h44(.LCPI7_0), %o0 +; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI7_0), %o0 +; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0 +; SPARC64-VIS3-NEXT: ldd [%o0+%l44(.LCPI7_0)], %f4 +; SPARC64-VIS3-NEXT: fcmpd %fcc0, %f0, %f4 +; SPARC64-VIS3-NEXT: fbuge %fcc0, .LBB7_3 +; SPARC64-VIS3-NEXT: nop +; SPARC64-VIS3-NEXT: ! %bb.1: ! %loop.2 +; SPARC64-VIS3-NEXT: fcmpd %fcc0, %f2, %f4 +; SPARC64-VIS3-NEXT: fbule %fcc0, .LBB7_3 +; SPARC64-VIS3-NEXT: nop +; SPARC64-VIS3-NEXT: ! %bb.2: ! %exit.1 +; SPARC64-VIS3-NEXT: retl +; SPARC64-VIS3-NEXT: mov 1, %o0 +; SPARC64-VIS3-NEXT: .LBB7_3: ! %loop +; SPARC64-VIS3-NEXT: ! =>This Inner Loop Header: Depth=1 +; SPARC64-VIS3-NEXT: cmp %o2, 10 +; SPARC64-VIS3-NEXT: be %icc, .LBB7_3 +; SPARC64-VIS3-NEXT: nop +; SPARC64-VIS3-NEXT: ! %bb.4: ! %exit.0 +; SPARC64-VIS3-NEXT: retl +; SPARC64-VIS3-NEXT: mov %g0, %o0 entry: %0 = fcmp uge double %a, 0.000000e+00 br i1 %0, label %loop, label %loop.2 @@ -558,6 +648,34 @@ define void @test_adde_sube(ptr %a, ptr %b, ptr %sum, ptr %diff) nounwind { ; SPARC64-NEXT: stx %i0, [%i3] ; SPARC64-NEXT: ret ; SPARC64-NEXT: restore +; +; SPARC64-VIS3-LABEL: test_adde_sube: +; SPARC64-VIS3: .register %g2, #scratch +; SPARC64-VIS3-NEXT: ! %bb.0: ! %entry +; SPARC64-VIS3-NEXT: save %sp, -128, %sp +; SPARC64-VIS3-NEXT: ldx [%i0+8], %i4 +; SPARC64-VIS3-NEXT: ldx [%i0], %i5 +; SPARC64-VIS3-NEXT: ldx [%i1+8], %g2 +; SPARC64-VIS3-NEXT: ldx [%i1], %i1 +; SPARC64-VIS3-NEXT: addcc %i4, %g2, %g2 +; SPARC64-VIS3-NEXT: addxccc %i5, %i1, %i1 +; SPARC64-VIS3-NEXT: stx %i1, [%i2] +; SPARC64-VIS3-NEXT: stx %g2, [%i2+8] +; SPARC64-VIS3-NEXT: !APP +; SPARC64-VIS3-NEXT: !NO_APP +; SPARC64-VIS3-NEXT: ldx [%i0+8], %i1 +; SPARC64-VIS3-NEXT: mov %g0, %i2 +; SPARC64-VIS3-NEXT: ldx [%i0], %i0 +; SPARC64-VIS3-NEXT: cmp %i4, %i1 +; SPARC64-VIS3-NEXT: movcs %xcc, 1, %i2 +; SPARC64-VIS3-NEXT: srl %i2, 0, %i2 +; SPARC64-VIS3-NEXT: sub %i5, %i0, %i0 +; SPARC64-VIS3-NEXT: sub %i0, %i2, %i0 +; SPARC64-VIS3-NEXT: sub %i4, %i1, %i1 +; SPARC64-VIS3-NEXT: stx %i1, [%i3+8] +; SPARC64-VIS3-NEXT: stx %i0, [%i3] +; SPARC64-VIS3-NEXT: ret +; SPARC64-VIS3-NEXT: restore entry: %0 = bitcast ptr %a to ptr %1 = bitcast ptr %b to ptr diff --git a/llvm/test/CodeGen/SPARC/float-constants.ll b/llvm/test/CodeGen/SPARC/float-constants.ll index b04ec68ed3d7e..440c75bfca9f9 100644 --- a/llvm/test/CodeGen/SPARC/float-constants.ll +++ b/llvm/test/CodeGen/SPARC/float-constants.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc < %s -mtriple=sparc | FileCheck %s ; RUN: llc < %s -mtriple=sparcel | FileCheck %s --check-prefix=CHECK-LE +; RUN: llc < %s -mtriple=sparcv9 -mattr=+vis | FileCheck %s --check-prefix=CHECK-VIS ;; Bitcast should not do a runtime conversion, but rather emit a ;; constant into integer registers directly. @@ -17,6 +18,12 @@ define <2 x i32> @bitcast() nounwind { ; CHECK-LE-NEXT: sethi 1049856, %o1 ; CHECK-LE-NEXT: retl ; CHECK-LE-NEXT: mov %g0, %o0 +; +; CHECK-VIS-LABEL: bitcast: +; CHECK-VIS: ! %bb.0: +; CHECK-VIS-NEXT: sethi 1049856, %o0 +; CHECK-VIS-NEXT: retl +; CHECK-VIS-NEXT: mov %g0, %o1 %1 = bitcast double 5.0 to <2 x i32> ret <2 x i32> %1 } @@ -43,6 +50,17 @@ define void @test_call() nounwind { ; CHECK-LE-NEXT: mov %g0, %o0 ; CHECK-LE-NEXT: ret ; CHECK-LE-NEXT: restore +; +; CHECK-VIS-LABEL: test_call: +; CHECK-VIS: ! %bb.0: +; CHECK-VIS-NEXT: save %sp, -176, %sp +; CHECK-VIS-NEXT: sethi %h44(.LCPI1_0), %i0 +; CHECK-VIS-NEXT: add %i0, %m44(.LCPI1_0), %i0 +; CHECK-VIS-NEXT: sllx %i0, 12, %i0 +; CHECK-VIS-NEXT: call a +; CHECK-VIS-NEXT: ldd [%i0+%l44(.LCPI1_0)], %f0 +; CHECK-VIS-NEXT: ret +; CHECK-VIS-NEXT: restore call void @a(double 5.0) ret void } @@ -75,6 +93,103 @@ define double @test_intrins_call() nounwind { ; CHECK-LE-NEXT: mov %o1, %o3 ; CHECK-LE-NEXT: ret ; CHECK-LE-NEXT: restore +; +; CHECK-VIS-LABEL: test_intrins_call: +; CHECK-VIS: ! %bb.0: +; CHECK-VIS-NEXT: save %sp, -176, %sp +; CHECK-VIS-NEXT: sethi %h44(.LCPI2_0), %i0 +; CHECK-VIS-NEXT: add %i0, %m44(.LCPI2_0), %i0 +; CHECK-VIS-NEXT: sllx %i0, 12, %i0 +; CHECK-VIS-NEXT: ldd [%i0+%l44(.LCPI2_0)], %f0 +; CHECK-VIS-NEXT: fmovd %f0, %f2 +; CHECK-VIS-NEXT: call pow +; CHECK-VIS-NEXT: nop +; CHECK-VIS-NEXT: ret +; CHECK-VIS-NEXT: restore %1 = call double @llvm.pow.f64(double 2.0, double 2.0) ret double %1 } + +;; When we have VIS, f32/f64 zero constant should be materialized from fzero/fzeros. + +define double @pos_zero_double() nounwind { +; CHECK-LABEL: pos_zero_double: +; CHECK: ! %bb.0: +; CHECK-NEXT: sethi %hi(.LCPI3_0), %o0 +; CHECK-NEXT: retl +; CHECK-NEXT: ldd [%o0+%lo(.LCPI3_0)], %f0 +; +; CHECK-LE-LABEL: pos_zero_double: +; CHECK-LE: ! %bb.0: +; CHECK-LE-NEXT: sethi %hi(.LCPI3_0), %o0 +; CHECK-LE-NEXT: retl +; CHECK-LE-NEXT: ldd [%o0+%lo(.LCPI3_0)], %f0 +; +; CHECK-VIS-LABEL: pos_zero_double: +; CHECK-VIS: ! %bb.0: +; CHECK-VIS-NEXT: retl +; CHECK-VIS-NEXT: fzero %f0 + ret double +0.0 +} + +define double @neg_zero_double() nounwind { +; CHECK-LABEL: neg_zero_double: +; CHECK: ! %bb.0: +; CHECK-NEXT: sethi %hi(.LCPI4_0), %o0 +; CHECK-NEXT: retl +; CHECK-NEXT: ldd [%o0+%lo(.LCPI4_0)], %f0 +; +; CHECK-LE-LABEL: neg_zero_double: +; CHECK-LE: ! %bb.0: +; CHECK-LE-NEXT: sethi %hi(.LCPI4_0), %o0 +; CHECK-LE-NEXT: retl +; CHECK-LE-NEXT: ldd [%o0+%lo(.LCPI4_0)], %f0 +; +; CHECK-VIS-LABEL: neg_zero_double: +; CHECK-VIS: ! %bb.0: +; CHECK-VIS-NEXT: fzero %f0 +; CHECK-VIS-NEXT: retl +; CHECK-VIS-NEXT: fnegd %f0, %f0 + ret double -0.0 +} + +define float @pos_zero_float() nounwind { +; CHECK-LABEL: pos_zero_float: +; CHECK: ! %bb.0: +; CHECK-NEXT: sethi %hi(.LCPI5_0), %o0 +; CHECK-NEXT: retl +; CHECK-NEXT: ld [%o0+%lo(.LCPI5_0)], %f0 +; +; CHECK-LE-LABEL: pos_zero_float: +; CHECK-LE: ! %bb.0: +; CHECK-LE-NEXT: sethi %hi(.LCPI5_0), %o0 +; CHECK-LE-NEXT: retl +; CHECK-LE-NEXT: ld [%o0+%lo(.LCPI5_0)], %f0 +; +; CHECK-VIS-LABEL: pos_zero_float: +; CHECK-VIS: ! %bb.0: +; CHECK-VIS-NEXT: retl +; CHECK-VIS-NEXT: fzeros %f0 + ret float +0.0 +} + +define float @neg_zero_float() nounwind { +; CHECK-LABEL: neg_zero_float: +; CHECK: ! %bb.0: +; CHECK-NEXT: sethi %hi(.LCPI6_0), %o0 +; CHECK-NEXT: retl +; CHECK-NEXT: ld [%o0+%lo(.LCPI6_0)], %f0 +; +; CHECK-LE-LABEL: neg_zero_float: +; CHECK-LE: ! %bb.0: +; CHECK-LE-NEXT: sethi %hi(.LCPI6_0), %o0 +; CHECK-LE-NEXT: retl +; CHECK-LE-NEXT: ld [%o0+%lo(.LCPI6_0)], %f0 +; +; CHECK-VIS-LABEL: neg_zero_float: +; CHECK-VIS: ! %bb.0: +; CHECK-VIS-NEXT: fzeros %f0 +; CHECK-VIS-NEXT: retl +; CHECK-VIS-NEXT: fnegs %f0, %f0 + ret float -0.0 +} From 326408514c723db5309026a6b2f26e73f1d4f473 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Wed, 16 Apr 2025 01:01:45 +0700 Subject: [PATCH 2/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?= =?UTF-8?q?anges=20introduced=20through=20rebase?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.5 [skip ci] --- llvm/lib/Target/Sparc/SparcInstrVIS.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td index 0e3d9fc8b6da4..ee24d8a54fe8e 100644 --- a/llvm/lib/Target/Sparc/SparcInstrVIS.td +++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td @@ -279,8 +279,8 @@ def XMULXHI : VISInst<0b100010110, "xmulxhi", I64Regs>; } // Predicates = [IsVIS3] // FP immediate patterns. -def fpimm0 : PatLeaf<(fpimm), [{return N->isExactlyValue(+0.0);}]>; -def fpnegimm0 : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>; +def fpimm0 : FPImmLeaf; +def fpnegimm0 : FPImmLeaf; // VIS instruction patterns. let Predicates = [HasVIS] in {