diff --git a/llvm/include/llvm/CodeGen/CFIInstBuilder.h b/llvm/include/llvm/CodeGen/CFIInstBuilder.h new file mode 100644 index 0000000000000..e799b47a0c974 --- /dev/null +++ b/llvm/include/llvm/CodeGen/CFIInstBuilder.h @@ -0,0 +1,88 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_CFIINSTBUILDER_H +#define LLVM_CODEGEN_CFIINSTBUILDER_H + +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/MC/MCDwarf.h" + +namespace llvm { + +/// Helper class for creating CFI instructions and inserting them into MIR. +class CFIInstBuilder { + MachineFunction &MF; + MachineBasicBlock &MBB; + MachineBasicBlock::iterator InsertPt; + + /// MIFlag to set on a MachineInstr. Typically, FrameSetup or FrameDestroy. + MachineInstr::MIFlag MIFlag; + + /// Selects DWARF register numbering: debug or exception handling. Should be + /// consistent with the choice of the ELF section (.debug_frame or .eh_frame) + /// where CFI will be encoded. + bool IsEH; + + // Cache frequently used variables. + const TargetRegisterInfo &TRI; + const MCInstrDesc &CFIID; + const MIMetadata MIMD; // Default-initialized, no debug location desired. + +public: + CFIInstBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, + MachineInstr::MIFlag MIFlag, bool IsEH = true) + : MF(*MBB.getParent()), MBB(MBB), MIFlag(MIFlag), IsEH(IsEH), + TRI(*MF.getSubtarget().getRegisterInfo()), + CFIID(MF.getSubtarget().getInstrInfo()->get( + TargetOpcode::CFI_INSTRUCTION)) { + setInsertPoint(InsertPt); + } + + void setInsertPoint(MachineBasicBlock::iterator IP) { InsertPt = IP; } + + void insertCFIInst(const MCCFIInstruction &CFIInst) const { + BuildMI(MBB, InsertPt, MIMD, CFIID) + .addCFIIndex(MF.addFrameInst(CFIInst)) + .setMIFlag(MIFlag); + } + + void buildDefCFA(MCRegister Reg, int64_t Offset) const { + insertCFIInst(MCCFIInstruction::cfiDefCfa( + nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); + } + + void buildDefCFARegister(MCRegister Reg) const { + insertCFIInst(MCCFIInstruction::createDefCfaRegister( + nullptr, TRI.getDwarfRegNum(Reg, IsEH))); + } + + void buildDefCFAOffset(int64_t Offset) const { + insertCFIInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); + } + + void buildOffset(MCRegister Reg, int64_t Offset) const { + insertCFIInst(MCCFIInstruction::createOffset( + nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); + } + + void buildRestore(MCRegister Reg) const { + insertCFIInst(MCCFIInstruction::createRestore( + nullptr, TRI.getDwarfRegNum(Reg, IsEH))); + } + + void buildEscape(StringRef Bytes, StringRef Comment = "") const { + insertCFIInst( + MCCFIInstruction::createEscape(nullptr, Bytes, SMLoc(), Comment)); + } +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_CFIINSTBUILDER_H diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index c7b2b781422d1..cefe7a732519d 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -14,6 +14,7 @@ #include "RISCVMachineFunctionInfo.h" #include "RISCVSubtarget.h" #include "llvm/BinaryFormat/Dwarf.h" +#include "llvm/CodeGen/CFIInstBuilder.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -28,64 +29,6 @@ using namespace llvm; -namespace { - -class CFISaveRegisterEmitter { - MachineFunction &MF; - MachineFrameInfo &MFI; - -public: - CFISaveRegisterEmitter(MachineFunction &MF) - : MF{MF}, MFI{MF.getFrameInfo()} {}; - - void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, - const DebugLoc &DL, const CalleeSavedInfo &CS) const { - int FrameIdx = CS.getFrameIdx(); - int64_t Offset = MFI.getObjectOffset(FrameIdx); - MCRegister Reg = CS.getReg(); - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, RI.getDwarfRegNum(Reg, true), Offset)); - BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - } -}; - -class CFIRestoreRegisterEmitter { - MachineFunction &MF; - -public: - CFIRestoreRegisterEmitter(MachineFunction &MF) : MF{MF} {}; - - void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, - const DebugLoc &DL, const CalleeSavedInfo &CS) const { - MCRegister Reg = CS.getReg(); - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true))); - BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } -}; - -} // namespace - -template -void RISCVFrameLowering::emitCFIForCSI( - MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - const SmallVector &CSI) const { - MachineFunction *MF = MBB.getParent(); - const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); - DebugLoc DL = MBB.findDebugLoc(MBBI); - - Emitter E{*MF}; - for (const auto &CS : CSI) - E.emit(MBB, MBBI, *RI, *TII, DL, CS); -} - static Align getABIStackAlignment(RISCVABI::ABI ABI) { if (ABI == RISCVABI::ABI_ILP32E) return Align(4); @@ -209,11 +152,8 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, Offset, // addend (sleb128) }; - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createEscape( - nullptr, StringRef(CFIInst, sizeof(CFIInst)))); - BuildMI(MBB, MI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); + CFIInstBuilder(MBB, MI, MachineInstr::FrameSetup) + .buildEscape(StringRef(CFIInst, sizeof(CFIInst))); } static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, @@ -257,11 +197,7 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, .addImm(-SlotSize) .setMIFlag(MachineInstr::FrameDestroy); // Restore the SCS pointer - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore( - nullptr, STI.getRegisterInfo()->getDwarfRegNum(SCSPReg, /*IsEH*/ true))); - BuildMI(MBB, MI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameDestroy); + CFIInstBuilder(MBB, MI, MachineInstr::FrameDestroy).buildRestore(SCSPReg); } // Get the ID of the libcall used for spilling and restoring callee saved @@ -531,14 +467,10 @@ void RISCVFrameLowering::allocateAndProbeStackForRVV( .setMIFlag(Flag); TII->mulImm(MF, MBB, MBBI, DL, TargetReg, NumOfVReg, Flag); + CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup); if (EmitCFI) { // Set the CFA register to TargetReg. - unsigned Reg = STI.getRegisterInfo()->getDwarfRegNum(TargetReg, true); - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, Reg, -Amount)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); + CFIBuilder.buildDefCFA(TargetReg, -Amount); } // It will be expanded to a probe loop in `inlineStackProbe`. @@ -548,12 +480,7 @@ void RISCVFrameLowering::allocateAndProbeStackForRVV( if (EmitCFI) { // Set the CFA register back to SP. - unsigned Reg = STI.getRegisterInfo()->getDwarfRegNum(SPReg, true); - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); + CFIBuilder.buildDefCFARegister(SPReg); } // SUB SP, SP, T1 @@ -665,20 +592,15 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, const RISCVRegisterInfo *RI = STI.getRegisterInfo(); const RISCVInstrInfo *TII = STI.getInstrInfo(); bool IsRV64 = STI.is64Bit(); + CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup); // Simply allocate the stack if it's not big enough to require a probe. if (!NeedProbe || Offset <= ProbeSize) { RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Offset), MachineInstr::FrameSetup, getStackAlign()); - if (EmitCFI) { - // Emit ".cfi_def_cfa_offset RealStackSize" - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - } + if (EmitCFI) + CFIBuilder.buildDefCFAOffset(RealStackSize); if (NeedProbe && DynAllocation) { // s[d|w] zero, 0(sp) @@ -707,14 +629,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, .setMIFlags(MachineInstr::FrameSetup); CurrentOffset += ProbeSize; - if (EmitCFI) { - // Emit ".cfi_def_cfa_offset CurrentOffset" - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, CurrentOffset)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - } + if (EmitCFI) + CFIBuilder.buildDefCFAOffset(CurrentOffset); } uint64_t Residual = Offset - CurrentOffset; @@ -722,14 +638,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Residual), MachineInstr::FrameSetup, getStackAlign()); - if (EmitCFI) { - // Emit ".cfi_def_cfa_offset Offset" - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - } + if (EmitCFI) + CFIBuilder.buildDefCFAOffset(Offset); if (DynAllocation) { // s[d|w] zero, 0(sp) @@ -756,12 +666,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, if (EmitCFI) { // Set the CFA register to TargetReg. - unsigned Reg = STI.getRegisterInfo()->getDwarfRegNum(TargetReg, true); - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, Reg, RoundedSize)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); + CFIBuilder.buildDefCFA(TargetReg, RoundedSize); } // It will be expanded to a probe loop in `inlineStackProbe`. @@ -771,12 +676,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, if (EmitCFI) { // Set the CFA register back to SP. - unsigned Reg = STI.getRegisterInfo()->getDwarfRegNum(SPReg, true); - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); + CFIBuilder.buildDefCFARegister(SPReg); } if (Residual) { @@ -792,14 +692,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, } } - if (EmitCFI) { - // Emit ".cfi_def_cfa_offset Offset" - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); - } + if (EmitCFI) + CFIBuilder.buildDefCFAOffset(Offset); } static bool isPush(unsigned Opcode) { @@ -855,7 +749,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo(); const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); Register BPReg = RISCVABI::getBPReg(); @@ -888,6 +781,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // callee-saved register. MBBI = std::prev(MBBI, getRVVCalleeSavedInfo(MF, CSI).size() + getUnmanagedCSI(MF, CSI).size()); + CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup); // If libcalls are used to spill and restore callee-saved registers, the frame // has two sections; the opaque section managed by the libcalls, and the @@ -915,14 +809,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign()); RVFI->setLibCallStackSize(LibCallFrameSize); - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, LibCallFrameSize)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - - emitCFIForCSI(MBB, MBBI, - getPushOrLibCallsSavedInfo(MF, CSI)); + CFIBuilder.buildDefCFAOffset(LibCallFrameSize); + for (const CalleeSavedInfo &CS : getPushOrLibCallsSavedInfo(MF, CSI)) + CFIBuilder.buildOffset(CS.getReg(), + MFI.getObjectOffset(CS.getFrameIdx())); } // FIXME (note copied from Lanai): This appears to be overallocating. Needs @@ -949,13 +839,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, } if (RVFI->useQCIInterrupt(MF)) { - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, QCIInterruptPushAmount)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - - emitCFIForCSI(MBB, MBBI, getQCISavedInfo(MF, CSI)); + CFIBuilder.buildDefCFAOffset(QCIInterruptPushAmount); + for (const CalleeSavedInfo &CS : getQCISavedInfo(MF, CSI)) + CFIBuilder.buildOffset(CS.getReg(), + MFI.getObjectOffset(CS.getFrameIdx())); } else if (RVFI->isPushable(MF) && FirstFrameSetup != MBB.end() && isPush(FirstFrameSetup->getOpcode())) { // Use available stack adjustment in push instruction to allocate additional @@ -967,14 +854,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, FirstFrameSetup->getOperand(1).setImm(StackAdj); StackSize -= StackAdj; - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize - StackSize)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - - emitCFIForCSI(MBB, MBBI, - getPushOrLibCallsSavedInfo(MF, CSI)); + CFIBuilder.buildDefCFAOffset(RealStackSize - StackSize); + for (const CalleeSavedInfo &CS : getPushOrLibCallsSavedInfo(MF, CSI)) + CFIBuilder.buildOffset(CS.getReg(), + MFI.getObjectOffset(CS.getFrameIdx())); } // Allocate space on the stack if necessary. @@ -995,10 +878,12 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // FIXME: assumes exactly one instruction is used to save each callee-saved // register. std::advance(MBBI, getUnmanagedCSI(MF, CSI).size()); + CFIBuilder.setInsertPoint(MBBI); // Iterate over list of callee-saved registers and emit .cfi_offset // directives. - emitCFIForCSI(MBB, MBBI, getUnmanagedCSI(MF, CSI)); + for (const CalleeSavedInfo &CS : getUnmanagedCSI(MF, CSI)) + CFIBuilder.buildOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); // Generate new FP. if (hasFP(MF)) { @@ -1017,12 +902,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MachineInstr::FrameSetup, getStackAlign()); } - // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()" - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( - nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize())); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); + CFIBuilder.buildDefCFA(FPReg, RVFI->getVarArgsSaveSize()); } uint64_t SecondSPAdjustAmount = 0; @@ -1052,11 +932,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, if (!hasFP(MF)) { // Emit .cfi_def_cfa_expression "sp + StackSize + RVVStackSize * vlenb". - unsigned CFIIndex = MF.addFrameInst(createDefCFAExpression( + CFIBuilder.insertCFIInst(createDefCFAExpression( *RI, SPReg, getStackSizeWithRVVPadding(MF), RVVStackSize / 8)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); } std::advance(MBBI, getRVVCalleeSavedInfo(MF, CSI).size()); @@ -1122,17 +999,13 @@ void RISCVFrameLowering::deallocateStack(MachineFunction &MF, uint64_t &StackSize, int64_t CFAOffset) const { const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize), MachineInstr::FrameDestroy, getStackAlign()); StackSize = 0; - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); + CFIInstBuilder(MBB, MBBI, MachineInstr::FrameDestroy) + .buildDefCFAOffset(CFAOffset); } void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, @@ -1140,7 +1013,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, const RISCVRegisterInfo *RI = STI.getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); // All calls are tail calls in GHC calling conv, and functions have no // prologue/epilogue. @@ -1171,6 +1043,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, // callee-saved register. auto FirstScalarCSRRestoreInsn = std::next(MBBI, getRVVCalleeSavedInfo(MF, CSI).size()); + CFIInstBuilder CFIBuilder(MBB, FirstScalarCSRRestoreInsn, + MachineInstr::FrameDestroy); uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF); uint64_t RealStackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount @@ -1191,14 +1065,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, StackOffset::getScalable(RVVStackSize), MachineInstr::FrameDestroy, getStackAlign()); - if (!hasFP(MF)) { - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( - nullptr, RI->getDwarfRegNum(SPReg, true), RealStackSize)); - BuildMI(MBB, FirstScalarCSRRestoreInsn, DL, - TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } + if (!hasFP(MF)) + CFIBuilder.buildDefCFA(SPReg, RealStackSize); emitCalleeSavedRVVEpilogCFI(MBB, FirstScalarCSRRestoreInsn); } @@ -1216,14 +1084,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, StackOffset::getFixed(SecondSPAdjustAmount), MachineInstr::FrameDestroy, getStackAlign()); - if (!hasFP(MF)) { - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, FirstSPAdjustAmount)); - BuildMI(MBB, FirstScalarCSRRestoreInsn, DL, - TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } + if (!hasFP(MF)) + CFIBuilder.buildDefCFAOffset(FirstSPAdjustAmount); } // Restore the stack pointer using the value of the frame pointer. Only @@ -1243,19 +1105,14 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, getStackAlign()); } - if (hasFP(MF)) { - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( - nullptr, RI->getDwarfRegNum(SPReg, true), RealStackSize)); - BuildMI(MBB, FirstScalarCSRRestoreInsn, DL, - TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } + if (hasFP(MF)) + CFIBuilder.buildDefCFA(SPReg, RealStackSize); // Skip to after the restores of scalar callee-saved registers // FIXME: assumes exactly one instruction is used to restore each // callee-saved register. MBBI = std::next(FirstScalarCSRRestoreInsn, getUnmanagedCSI(MF, CSI).size()); + CFIBuilder.setInsertPoint(MBBI); if (getLibCallID(MF, CSI) != -1) { // tail __riscv_restore_[0-12] instruction is considered as a terminator, @@ -1271,7 +1128,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, } // Recover callee-saved registers. - emitCFIForCSI(MBB, MBBI, getUnmanagedCSI(MF, CSI)); + for (const CalleeSavedInfo &CS : getUnmanagedCSI(MF, CSI)) + CFIBuilder.buildRestore(CS.getReg()); if (RVFI->isPushable(MF) && MBBI != MBB.end() && isPop(MBBI->getOpcode())) { // Use available stack adjustment in pop instruction to deallocate stack @@ -1290,17 +1148,14 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, auto NextI = next_nodbg(MBBI, MBB.end()); if (NextI == MBB.end() || NextI->getOpcode() != RISCV::PseudoRET) { ++MBBI; + CFIBuilder.setInsertPoint(MBBI); - emitCFIForCSI( - MBB, MBBI, getPushOrLibCallsSavedInfo(MF, CSI)); + for (const CalleeSavedInfo &CS : getPushOrLibCallsSavedInfo(MF, CSI)) + CFIBuilder.buildRestore(CS.getReg()); // Update CFA offset. After CM_POP SP should be equal to CFA, so CFA // offset should be a zero. - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); + CFIBuilder.buildDefCFAOffset(0); } } @@ -2052,9 +1907,7 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI( MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = MF->getFrameInfo(); RISCVMachineFunctionInfo *RVFI = MF->getInfo(); - const TargetInstrInfo &TII = *STI.getInstrInfo(); const RISCVRegisterInfo &TRI = *STI.getRegisterInfo(); - DebugLoc DL = MBB.findDebugLoc(MI); const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo()); if (RVVCSI.empty()) @@ -2068,17 +1921,15 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI( FixedSize -= ScalarLocalVarSize; } + CFIInstBuilder CFIBuilder(MBB, MI, MachineInstr::FrameSetup); for (auto &CS : RVVCSI) { // Insert the spill to the stack frame. int FI = CS.getFrameIdx(); MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg()); unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg()); for (unsigned i = 0; i < NumRegs; ++i) { - unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset( + CFIBuilder.insertCFIInst(createDefCFAOffset( TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i)); - BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); } } } @@ -2087,22 +1938,15 @@ void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = MF->getFrameInfo(); - const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - const TargetInstrInfo &TII = *STI.getInstrInfo(); const RISCVRegisterInfo &TRI = *STI.getRegisterInfo(); - DebugLoc DL = MBB.findDebugLoc(MI); + CFIInstBuilder CFIHelper(MBB, MI, MachineInstr::FrameDestroy); const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo()); for (auto &CS : RVVCSI) { MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg()); unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg()); - for (unsigned i = 0; i < NumRegs; ++i) { - unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore( - nullptr, RI->getDwarfRegNum(BaseReg + i, true))); - BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } + for (unsigned i = 0; i < NumRegs; ++i) + CFIHelper.buildRestore(BaseReg + i); } }