From eba9383be0ca1b8954f9639db8bb97bb96f0ab9a Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 16 Apr 2025 01:31:22 +0300 Subject: [PATCH 1/5] [CodeGen][RISCV] Add helper class for emitting CFI instructions into MIR --- .../llvm/CodeGen/CFIInstEmitterHelper.h | 88 ++++++ llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 256 ++++-------------- 2 files changed, 141 insertions(+), 203 deletions(-) create mode 100644 llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h diff --git a/llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h b/llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h new file mode 100644 index 0000000000000..bcc4c2667d081 --- /dev/null +++ b/llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h @@ -0,0 +1,88 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_CFIINSTREMITTERHELPER_H +#define LLVM_CODEGEN_CFIINSTREMITTERHELPER_H + +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/MC/MCDwarf.h" + +namespace llvm { + +/// Helper class for emitting CFI instructions into Machine IR. +class CFIInstEmitterHelper { + MachineFunction &MF; + MachineBasicBlock &MBB; + MachineBasicBlock::iterator InsertPt; + + /// MIflag to set on a MachineInstr. Typically, FrameSetup or FrameDestroy. + MachineInstr::MIFlag MIFlag; + + /// Selects DWARF register numbering: debug or exception handling. Should be + /// consistent with the choice of the ELF section (.debug_frame or .eh_frame) + /// where CFI will be encoded. + bool IsEH; + + // Cache frequently used variables. + const TargetRegisterInfo &TRI; + const MCInstrDesc &CFIID; + const MIMetadata MIMD; // Default-initialized, no debug location desired. + + void emitCFIInstr(const MCCFIInstruction &CFIInst) const { + BuildMI(MBB, InsertPt, MIMD, CFIID) + .addCFIIndex(MF.addFrameInst(CFIInst)) + .setMIFlag(MIFlag); + } + +public: + CFIInstEmitterHelper(MachineBasicBlock &MBB, + MachineBasicBlock::iterator InsertPt, + MachineInstr::MIFlag MIFlag, bool IsEH = true) + : MF(*MBB.getParent()), MBB(MBB), MIFlag(MIFlag), IsEH(IsEH), + TRI(*MF.getSubtarget().getRegisterInfo()), + CFIID(MF.getSubtarget().getInstrInfo()->get( + TargetOpcode::CFI_INSTRUCTION)) { + setInsertPoint(InsertPt); + } + + void setInsertPoint(MachineBasicBlock::iterator IP) { InsertPt = IP; } + + void emitDefCFA(MCRegister Reg, int64_t Offset) const { + emitCFIInstr(MCCFIInstruction::cfiDefCfa( + nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); + } + + void emitDefCFARegister(MCRegister Reg) const { + emitCFIInstr(MCCFIInstruction::createDefCfaRegister( + nullptr, TRI.getDwarfRegNum(Reg, IsEH))); + } + + void emitDefCFAOffset(int64_t Offset) const { + emitCFIInstr(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); + } + + void emitOffset(MCRegister Reg, int64_t Offset) const { + emitCFIInstr(MCCFIInstruction::createOffset( + nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); + } + + void emitRestore(MCRegister Reg) const { + emitCFIInstr(MCCFIInstruction::createRestore( + nullptr, TRI.getDwarfRegNum(Reg, IsEH))); + } + + void emitEscape(StringRef Bytes) const { + emitCFIInstr(MCCFIInstruction::createEscape(nullptr, Bytes)); + } +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_CFIINSTREMITTERHELPER_H diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index c7b2b781422d1..c8ddcc2e46633 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -14,6 +14,7 @@ #include "RISCVMachineFunctionInfo.h" #include "RISCVSubtarget.h" #include "llvm/BinaryFormat/Dwarf.h" +#include "llvm/CodeGen/CFIInstEmitterHelper.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -28,64 +29,6 @@ using namespace llvm; -namespace { - -class CFISaveRegisterEmitter { - MachineFunction &MF; - MachineFrameInfo &MFI; - -public: - CFISaveRegisterEmitter(MachineFunction &MF) - : MF{MF}, MFI{MF.getFrameInfo()} {}; - - void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, - const DebugLoc &DL, const CalleeSavedInfo &CS) const { - int FrameIdx = CS.getFrameIdx(); - int64_t Offset = MFI.getObjectOffset(FrameIdx); - MCRegister Reg = CS.getReg(); - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( - nullptr, RI.getDwarfRegNum(Reg, true), Offset)); - BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - } -}; - -class CFIRestoreRegisterEmitter { - MachineFunction &MF; - -public: - CFIRestoreRegisterEmitter(MachineFunction &MF) : MF{MF} {}; - - void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, - const DebugLoc &DL, const CalleeSavedInfo &CS) const { - MCRegister Reg = CS.getReg(); - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true))); - BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } -}; - -} // namespace - -template -void RISCVFrameLowering::emitCFIForCSI( - MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - const SmallVector &CSI) const { - MachineFunction *MF = MBB.getParent(); - const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); - DebugLoc DL = MBB.findDebugLoc(MBBI); - - Emitter E{*MF}; - for (const auto &CS : CSI) - E.emit(MBB, MBBI, *RI, *TII, DL, CS); -} - static Align getABIStackAlignment(RISCVABI::ABI ABI) { if (ABI == RISCVABI::ABI_ILP32E) return Align(4); @@ -209,11 +152,8 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, Offset, // addend (sleb128) }; - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createEscape( - nullptr, StringRef(CFIInst, sizeof(CFIInst)))); - BuildMI(MBB, MI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); + CFIInstEmitterHelper(MBB, MI, MachineInstr::FrameSetup) + .emitEscape(StringRef(CFIInst, sizeof(CFIInst))); } static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, @@ -257,11 +197,8 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, .addImm(-SlotSize) .setMIFlag(MachineInstr::FrameDestroy); // Restore the SCS pointer - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore( - nullptr, STI.getRegisterInfo()->getDwarfRegNum(SCSPReg, /*IsEH*/ true))); - BuildMI(MBB, MI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameDestroy); + CFIInstEmitterHelper(MBB, MI, MachineInstr::FrameDestroy) + .emitRestore(SCSPReg); } // Get the ID of the libcall used for spilling and restoring callee saved @@ -531,14 +468,10 @@ void RISCVFrameLowering::allocateAndProbeStackForRVV( .setMIFlag(Flag); TII->mulImm(MF, MBB, MBBI, DL, TargetReg, NumOfVReg, Flag); + CFIInstEmitterHelper CFIHelper(MBB, MBBI, MachineInstr::FrameDestroy); if (EmitCFI) { // Set the CFA register to TargetReg. - unsigned Reg = STI.getRegisterInfo()->getDwarfRegNum(TargetReg, true); - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, Reg, -Amount)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); + CFIHelper.emitDefCFA(TargetReg, -Amount); } // It will be expanded to a probe loop in `inlineStackProbe`. @@ -548,12 +481,7 @@ void RISCVFrameLowering::allocateAndProbeStackForRVV( if (EmitCFI) { // Set the CFA register back to SP. - unsigned Reg = STI.getRegisterInfo()->getDwarfRegNum(SPReg, true); - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); + CFIHelper.emitDefCFARegister(SPReg); } // SUB SP, SP, T1 @@ -665,20 +593,15 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, const RISCVRegisterInfo *RI = STI.getRegisterInfo(); const RISCVInstrInfo *TII = STI.getInstrInfo(); bool IsRV64 = STI.is64Bit(); + CFIInstEmitterHelper CFIHelper(MBB, MBBI, MachineInstr::FrameSetup); // Simply allocate the stack if it's not big enough to require a probe. if (!NeedProbe || Offset <= ProbeSize) { RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Offset), MachineInstr::FrameSetup, getStackAlign()); - if (EmitCFI) { - // Emit ".cfi_def_cfa_offset RealStackSize" - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - } + if (EmitCFI) + CFIHelper.emitDefCFAOffset(RealStackSize); if (NeedProbe && DynAllocation) { // s[d|w] zero, 0(sp) @@ -707,14 +630,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, .setMIFlags(MachineInstr::FrameSetup); CurrentOffset += ProbeSize; - if (EmitCFI) { - // Emit ".cfi_def_cfa_offset CurrentOffset" - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, CurrentOffset)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - } + if (EmitCFI) + CFIHelper.emitDefCFAOffset(CurrentOffset); } uint64_t Residual = Offset - CurrentOffset; @@ -722,14 +639,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Residual), MachineInstr::FrameSetup, getStackAlign()); - if (EmitCFI) { - // Emit ".cfi_def_cfa_offset Offset" - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - } + if (EmitCFI) + CFIHelper.emitDefCFAOffset(Offset); if (DynAllocation) { // s[d|w] zero, 0(sp) @@ -756,12 +667,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, if (EmitCFI) { // Set the CFA register to TargetReg. - unsigned Reg = STI.getRegisterInfo()->getDwarfRegNum(TargetReg, true); - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, Reg, RoundedSize)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); + CFIHelper.emitDefCFA(TargetReg, RoundedSize); } // It will be expanded to a probe loop in `inlineStackProbe`. @@ -771,12 +677,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, if (EmitCFI) { // Set the CFA register back to SP. - unsigned Reg = STI.getRegisterInfo()->getDwarfRegNum(SPReg, true); - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); + CFIHelper.emitDefCFARegister(SPReg); } if (Residual) { @@ -792,14 +693,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, } } - if (EmitCFI) { - // Emit ".cfi_def_cfa_offset Offset" - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlags(MachineInstr::FrameSetup); - } + if (EmitCFI) + CFIHelper.emitDefCFAOffset(Offset); } static bool isPush(unsigned Opcode) { @@ -888,6 +783,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // callee-saved register. MBBI = std::prev(MBBI, getRVVCalleeSavedInfo(MF, CSI).size() + getUnmanagedCSI(MF, CSI).size()); + CFIInstEmitterHelper CFIHelper(MBB, MBBI, MachineInstr::FrameSetup); // If libcalls are used to spill and restore callee-saved registers, the frame // has two sections; the opaque section managed by the libcalls, and the @@ -915,14 +811,9 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign()); RVFI->setLibCallStackSize(LibCallFrameSize); - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, LibCallFrameSize)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - - emitCFIForCSI(MBB, MBBI, - getPushOrLibCallsSavedInfo(MF, CSI)); + CFIHelper.emitDefCFAOffset(LibCallFrameSize); + for (const CalleeSavedInfo &CS : getPushOrLibCallsSavedInfo(MF, CSI)) + CFIHelper.emitOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); } // FIXME (note copied from Lanai): This appears to be overallocating. Needs @@ -949,13 +840,9 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, } if (RVFI->useQCIInterrupt(MF)) { - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, QCIInterruptPushAmount)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - - emitCFIForCSI(MBB, MBBI, getQCISavedInfo(MF, CSI)); + CFIHelper.emitDefCFAOffset(QCIInterruptPushAmount); + for (const CalleeSavedInfo &CS : getQCISavedInfo(MF, CSI)) + CFIHelper.emitOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); } else if (RVFI->isPushable(MF) && FirstFrameSetup != MBB.end() && isPush(FirstFrameSetup->getOpcode())) { // Use available stack adjustment in push instruction to allocate additional @@ -967,14 +854,9 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, FirstFrameSetup->getOperand(1).setImm(StackAdj); StackSize -= StackAdj; - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize - StackSize)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - - emitCFIForCSI(MBB, MBBI, - getPushOrLibCallsSavedInfo(MF, CSI)); + CFIHelper.emitDefCFAOffset(RealStackSize - StackSize); + for (const CalleeSavedInfo &CS : getPushOrLibCallsSavedInfo(MF, CSI)) + CFIHelper.emitOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); } // Allocate space on the stack if necessary. @@ -995,10 +877,12 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // FIXME: assumes exactly one instruction is used to save each callee-saved // register. std::advance(MBBI, getUnmanagedCSI(MF, CSI).size()); + CFIHelper.setInsertPoint(MBBI); // Iterate over list of callee-saved registers and emit .cfi_offset // directives. - emitCFIForCSI(MBB, MBBI, getUnmanagedCSI(MF, CSI)); + for (const CalleeSavedInfo &CS : getUnmanagedCSI(MF, CSI)) + CFIHelper.emitOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); // Generate new FP. if (hasFP(MF)) { @@ -1017,12 +901,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MachineInstr::FrameSetup, getStackAlign()); } - // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()" - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( - nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize())); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); + CFIHelper.emitDefCFA(FPReg, RVFI->getVarArgsSaveSize()); } uint64_t SecondSPAdjustAmount = 0; @@ -1122,17 +1001,13 @@ void RISCVFrameLowering::deallocateStack(MachineFunction &MF, uint64_t &StackSize, int64_t CFAOffset) const { const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize), MachineInstr::FrameDestroy, getStackAlign()); StackSize = 0; - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); + CFIInstEmitterHelper(MBB, MBBI, MachineInstr::FrameDestroy) + .emitDefCFAOffset(CFAOffset); } void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, @@ -1140,7 +1015,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, const RISCVRegisterInfo *RI = STI.getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); // All calls are tail calls in GHC calling conv, and functions have no // prologue/epilogue. @@ -1171,6 +1045,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, // callee-saved register. auto FirstScalarCSRRestoreInsn = std::next(MBBI, getRVVCalleeSavedInfo(MF, CSI).size()); + CFIInstEmitterHelper CFIHelper(MBB, FirstScalarCSRRestoreInsn, + MachineInstr::FrameDestroy); uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF); uint64_t RealStackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount @@ -1191,14 +1067,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, StackOffset::getScalable(RVVStackSize), MachineInstr::FrameDestroy, getStackAlign()); - if (!hasFP(MF)) { - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( - nullptr, RI->getDwarfRegNum(SPReg, true), RealStackSize)); - BuildMI(MBB, FirstScalarCSRRestoreInsn, DL, - TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } + if (!hasFP(MF)) + CFIHelper.emitDefCFA(SPReg, RealStackSize); emitCalleeSavedRVVEpilogCFI(MBB, FirstScalarCSRRestoreInsn); } @@ -1216,14 +1086,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, StackOffset::getFixed(SecondSPAdjustAmount), MachineInstr::FrameDestroy, getStackAlign()); - if (!hasFP(MF)) { - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::cfiDefCfaOffset(nullptr, FirstSPAdjustAmount)); - BuildMI(MBB, FirstScalarCSRRestoreInsn, DL, - TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } + if (!hasFP(MF)) + CFIHelper.emitDefCFAOffset(FirstSPAdjustAmount); } // Restore the stack pointer using the value of the frame pointer. Only @@ -1243,19 +1107,14 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, getStackAlign()); } - if (hasFP(MF)) { - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( - nullptr, RI->getDwarfRegNum(SPReg, true), RealStackSize)); - BuildMI(MBB, FirstScalarCSRRestoreInsn, DL, - TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } + if (hasFP(MF)) + CFIHelper.emitDefCFA(SPReg, RealStackSize); // Skip to after the restores of scalar callee-saved registers // FIXME: assumes exactly one instruction is used to restore each // callee-saved register. MBBI = std::next(FirstScalarCSRRestoreInsn, getUnmanagedCSI(MF, CSI).size()); + CFIHelper.setInsertPoint(MBBI); if (getLibCallID(MF, CSI) != -1) { // tail __riscv_restore_[0-12] instruction is considered as a terminator, @@ -1271,7 +1130,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, } // Recover callee-saved registers. - emitCFIForCSI(MBB, MBBI, getUnmanagedCSI(MF, CSI)); + for (const CalleeSavedInfo &CS : getUnmanagedCSI(MF, CSI)) + CFIHelper.emitRestore(CS.getReg()); if (RVFI->isPushable(MF) && MBBI != MBB.end() && isPop(MBBI->getOpcode())) { // Use available stack adjustment in pop instruction to deallocate stack @@ -1290,17 +1150,14 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, auto NextI = next_nodbg(MBBI, MBB.end()); if (NextI == MBB.end() || NextI->getOpcode() != RISCV::PseudoRET) { ++MBBI; + CFIHelper.setInsertPoint(MBBI); - emitCFIForCSI( - MBB, MBBI, getPushOrLibCallsSavedInfo(MF, CSI)); + for (const CalleeSavedInfo &CS : getPushOrLibCallsSavedInfo(MF, CSI)) + CFIHelper.emitRestore(CS.getReg()); // Update CFA offset. After CM_POP SP should be equal to CFA, so CFA // offset should be a zero. - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); + CFIHelper.emitDefCFAOffset(0); } } @@ -2087,22 +1944,15 @@ void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = MF->getFrameInfo(); - const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - const TargetInstrInfo &TII = *STI.getInstrInfo(); const RISCVRegisterInfo &TRI = *STI.getRegisterInfo(); - DebugLoc DL = MBB.findDebugLoc(MI); + CFIInstEmitterHelper CFIHelper(MBB, MI, MachineInstr::FrameDestroy); const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo()); for (auto &CS : RVVCSI) { MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg()); unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg()); - for (unsigned i = 0; i < NumRegs; ++i) { - unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore( - nullptr, RI->getDwarfRegNum(BaseReg + i, true))); - BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameDestroy); - } + for (unsigned i = 0; i < NumRegs; ++i) + CFIHelper.emitRestore(BaseReg + i); } } From 749516d9f8c15d91e26121878407c20f665189ed Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 16 Apr 2025 02:10:34 +0300 Subject: [PATCH 2/5] Make helper method public, use it in a couple of places --- .../llvm/CodeGen/CFIInstEmitterHelper.h | 26 +++++++++---------- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 14 +++------- 2 files changed, 16 insertions(+), 24 deletions(-) diff --git a/llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h b/llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h index bcc4c2667d081..82139e37b8503 100644 --- a/llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h +++ b/llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h @@ -35,12 +35,6 @@ class CFIInstEmitterHelper { const MCInstrDesc &CFIID; const MIMetadata MIMD; // Default-initialized, no debug location desired. - void emitCFIInstr(const MCCFIInstruction &CFIInst) const { - BuildMI(MBB, InsertPt, MIMD, CFIID) - .addCFIIndex(MF.addFrameInst(CFIInst)) - .setMIFlag(MIFlag); - } - public: CFIInstEmitterHelper(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, @@ -54,32 +48,38 @@ class CFIInstEmitterHelper { void setInsertPoint(MachineBasicBlock::iterator IP) { InsertPt = IP; } + void emitCFIInst(const MCCFIInstruction &CFIInst) const { + BuildMI(MBB, InsertPt, MIMD, CFIID) + .addCFIIndex(MF.addFrameInst(CFIInst)) + .setMIFlag(MIFlag); + } + void emitDefCFA(MCRegister Reg, int64_t Offset) const { - emitCFIInstr(MCCFIInstruction::cfiDefCfa( + emitCFIInst(MCCFIInstruction::cfiDefCfa( nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); } void emitDefCFARegister(MCRegister Reg) const { - emitCFIInstr(MCCFIInstruction::createDefCfaRegister( + emitCFIInst(MCCFIInstruction::createDefCfaRegister( nullptr, TRI.getDwarfRegNum(Reg, IsEH))); } void emitDefCFAOffset(int64_t Offset) const { - emitCFIInstr(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); + emitCFIInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); } void emitOffset(MCRegister Reg, int64_t Offset) const { - emitCFIInstr(MCCFIInstruction::createOffset( + emitCFIInst(MCCFIInstruction::createOffset( nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); } void emitRestore(MCRegister Reg) const { - emitCFIInstr(MCCFIInstruction::createRestore( - nullptr, TRI.getDwarfRegNum(Reg, IsEH))); + emitCFIInst(MCCFIInstruction::createRestore(nullptr, + TRI.getDwarfRegNum(Reg, IsEH))); } void emitEscape(StringRef Bytes) const { - emitCFIInstr(MCCFIInstruction::createEscape(nullptr, Bytes)); + emitCFIInst(MCCFIInstruction::createEscape(nullptr, Bytes)); } }; diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index c8ddcc2e46633..9d26d13b852b5 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -750,7 +750,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo(); const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); Register BPReg = RISCVABI::getBPReg(); @@ -931,11 +930,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, if (!hasFP(MF)) { // Emit .cfi_def_cfa_expression "sp + StackSize + RVVStackSize * vlenb". - unsigned CFIIndex = MF.addFrameInst(createDefCFAExpression( + CFIHelper.emitCFIInst(createDefCFAExpression( *RI, SPReg, getStackSizeWithRVVPadding(MF), RVVStackSize / 8)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); } std::advance(MBBI, getRVVCalleeSavedInfo(MF, CSI).size()); @@ -1909,9 +1905,7 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI( MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = MF->getFrameInfo(); RISCVMachineFunctionInfo *RVFI = MF->getInfo(); - const TargetInstrInfo &TII = *STI.getInstrInfo(); const RISCVRegisterInfo &TRI = *STI.getRegisterInfo(); - DebugLoc DL = MBB.findDebugLoc(MI); const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo()); if (RVVCSI.empty()) @@ -1925,17 +1919,15 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI( FixedSize -= ScalarLocalVarSize; } + CFIInstEmitterHelper CFIHelper(MBB, MI, MachineInstr::FrameSetup); for (auto &CS : RVVCSI) { // Insert the spill to the stack frame. int FI = CS.getFrameIdx(); MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg()); unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg()); for (unsigned i = 0; i < NumRegs; ++i) { - unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset( + CFIHelper.emitCFIInst(createDefCFAOffset( TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i)); - BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); } } } From 166b6aefbdc862944b3d49f4fe62868ac9782f52 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 16 Apr 2025 02:33:38 +0300 Subject: [PATCH 3/5] Rename (Emitter)Helper -> Builder, emit -> build, amend buildEscape --- ...FIInstEmitterHelper.h => CFIInstBuilder.h} | 44 +++++----- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 86 ++++++++++--------- 2 files changed, 66 insertions(+), 64 deletions(-) rename llvm/include/llvm/CodeGen/{CFIInstEmitterHelper.h => CFIInstBuilder.h} (60%) diff --git a/llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h b/llvm/include/llvm/CodeGen/CFIInstBuilder.h similarity index 60% rename from llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h rename to llvm/include/llvm/CodeGen/CFIInstBuilder.h index 82139e37b8503..b8ab512dca014 100644 --- a/llvm/include/llvm/CodeGen/CFIInstEmitterHelper.h +++ b/llvm/include/llvm/CodeGen/CFIInstBuilder.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CODEGEN_CFIINSTREMITTERHELPER_H -#define LLVM_CODEGEN_CFIINSTREMITTERHELPER_H +#ifndef LLVM_CODEGEN_CFIINSTBUILDER_H +#define LLVM_CODEGEN_CFIINSTBUILDER_H #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/TargetInstrInfo.h" @@ -16,8 +16,8 @@ namespace llvm { -/// Helper class for emitting CFI instructions into Machine IR. -class CFIInstEmitterHelper { +/// Helper class for creating CFI instructions and inserting them into MIR. +class CFIInstBuilder { MachineFunction &MF; MachineBasicBlock &MBB; MachineBasicBlock::iterator InsertPt; @@ -36,9 +36,8 @@ class CFIInstEmitterHelper { const MIMetadata MIMD; // Default-initialized, no debug location desired. public: - CFIInstEmitterHelper(MachineBasicBlock &MBB, - MachineBasicBlock::iterator InsertPt, - MachineInstr::MIFlag MIFlag, bool IsEH = true) + CFIInstBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, + MachineInstr::MIFlag MIFlag, bool IsEH = true) : MF(*MBB.getParent()), MBB(MBB), MIFlag(MIFlag), IsEH(IsEH), TRI(*MF.getSubtarget().getRegisterInfo()), CFIID(MF.getSubtarget().getInstrInfo()->get( @@ -48,41 +47,42 @@ class CFIInstEmitterHelper { void setInsertPoint(MachineBasicBlock::iterator IP) { InsertPt = IP; } - void emitCFIInst(const MCCFIInstruction &CFIInst) const { + void insertCFIInst(const MCCFIInstruction &CFIInst) const { BuildMI(MBB, InsertPt, MIMD, CFIID) .addCFIIndex(MF.addFrameInst(CFIInst)) .setMIFlag(MIFlag); } - void emitDefCFA(MCRegister Reg, int64_t Offset) const { - emitCFIInst(MCCFIInstruction::cfiDefCfa( + void buildDefCFA(MCRegister Reg, int64_t Offset) const { + insertCFIInst(MCCFIInstruction::cfiDefCfa( nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); } - void emitDefCFARegister(MCRegister Reg) const { - emitCFIInst(MCCFIInstruction::createDefCfaRegister( + void buildDefCFARegister(MCRegister Reg) const { + insertCFIInst(MCCFIInstruction::createDefCfaRegister( nullptr, TRI.getDwarfRegNum(Reg, IsEH))); } - void emitDefCFAOffset(int64_t Offset) const { - emitCFIInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); + void buildDefCFAOffset(int64_t Offset) const { + insertCFIInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); } - void emitOffset(MCRegister Reg, int64_t Offset) const { - emitCFIInst(MCCFIInstruction::createOffset( + void buildOffset(MCRegister Reg, int64_t Offset) const { + insertCFIInst(MCCFIInstruction::createOffset( nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset)); } - void emitRestore(MCRegister Reg) const { - emitCFIInst(MCCFIInstruction::createRestore(nullptr, - TRI.getDwarfRegNum(Reg, IsEH))); + void buildRestore(MCRegister Reg) const { + insertCFIInst(MCCFIInstruction::createRestore( + nullptr, TRI.getDwarfRegNum(Reg, IsEH))); } - void emitEscape(StringRef Bytes) const { - emitCFIInst(MCCFIInstruction::createEscape(nullptr, Bytes)); + void buildEscape(StringRef Bytes, StringRef Comment = "") const { + insertCFIInst( + MCCFIInstruction::createEscape(nullptr, Bytes, SMLoc(), Comment)); } }; } // namespace llvm -#endif // LLVM_CODEGEN_CFIINSTREMITTERHELPER_H +#endif // LLVM_CODEGEN_CFIINSTBUILDER_H diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 9d26d13b852b5..c45ff6e389cb5 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -14,7 +14,7 @@ #include "RISCVMachineFunctionInfo.h" #include "RISCVSubtarget.h" #include "llvm/BinaryFormat/Dwarf.h" -#include "llvm/CodeGen/CFIInstEmitterHelper.h" +#include "llvm/CodeGen/CFIInstBuilder.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -152,8 +152,8 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, Offset, // addend (sleb128) }; - CFIInstEmitterHelper(MBB, MI, MachineInstr::FrameSetup) - .emitEscape(StringRef(CFIInst, sizeof(CFIInst))); + CFIInstBuilder(MBB, MI, MachineInstr::FrameSetup) + .buildEscape(StringRef(CFIInst, sizeof(CFIInst))); } static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, @@ -197,8 +197,7 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, .addImm(-SlotSize) .setMIFlag(MachineInstr::FrameDestroy); // Restore the SCS pointer - CFIInstEmitterHelper(MBB, MI, MachineInstr::FrameDestroy) - .emitRestore(SCSPReg); + CFIInstBuilder(MBB, MI, MachineInstr::FrameDestroy).buildRestore(SCSPReg); } // Get the ID of the libcall used for spilling and restoring callee saved @@ -468,10 +467,10 @@ void RISCVFrameLowering::allocateAndProbeStackForRVV( .setMIFlag(Flag); TII->mulImm(MF, MBB, MBBI, DL, TargetReg, NumOfVReg, Flag); - CFIInstEmitterHelper CFIHelper(MBB, MBBI, MachineInstr::FrameDestroy); + CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameDestroy); if (EmitCFI) { // Set the CFA register to TargetReg. - CFIHelper.emitDefCFA(TargetReg, -Amount); + CFIBuilder.buildDefCFA(TargetReg, -Amount); } // It will be expanded to a probe loop in `inlineStackProbe`. @@ -481,7 +480,7 @@ void RISCVFrameLowering::allocateAndProbeStackForRVV( if (EmitCFI) { // Set the CFA register back to SP. - CFIHelper.emitDefCFARegister(SPReg); + CFIBuilder.buildDefCFARegister(SPReg); } // SUB SP, SP, T1 @@ -593,7 +592,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, const RISCVRegisterInfo *RI = STI.getRegisterInfo(); const RISCVInstrInfo *TII = STI.getInstrInfo(); bool IsRV64 = STI.is64Bit(); - CFIInstEmitterHelper CFIHelper(MBB, MBBI, MachineInstr::FrameSetup); + CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup); // Simply allocate the stack if it's not big enough to require a probe. if (!NeedProbe || Offset <= ProbeSize) { @@ -601,7 +600,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, MachineInstr::FrameSetup, getStackAlign()); if (EmitCFI) - CFIHelper.emitDefCFAOffset(RealStackSize); + CFIBuilder.buildDefCFAOffset(RealStackSize); if (NeedProbe && DynAllocation) { // s[d|w] zero, 0(sp) @@ -631,7 +630,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, CurrentOffset += ProbeSize; if (EmitCFI) - CFIHelper.emitDefCFAOffset(CurrentOffset); + CFIBuilder.buildDefCFAOffset(CurrentOffset); } uint64_t Residual = Offset - CurrentOffset; @@ -640,7 +639,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, StackOffset::getFixed(-Residual), MachineInstr::FrameSetup, getStackAlign()); if (EmitCFI) - CFIHelper.emitDefCFAOffset(Offset); + CFIBuilder.buildDefCFAOffset(Offset); if (DynAllocation) { // s[d|w] zero, 0(sp) @@ -667,7 +666,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, if (EmitCFI) { // Set the CFA register to TargetReg. - CFIHelper.emitDefCFA(TargetReg, RoundedSize); + CFIBuilder.buildDefCFA(TargetReg, RoundedSize); } // It will be expanded to a probe loop in `inlineStackProbe`. @@ -677,7 +676,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, if (EmitCFI) { // Set the CFA register back to SP. - CFIHelper.emitDefCFARegister(SPReg); + CFIBuilder.buildDefCFARegister(SPReg); } if (Residual) { @@ -694,7 +693,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB, } if (EmitCFI) - CFIHelper.emitDefCFAOffset(Offset); + CFIBuilder.buildDefCFAOffset(Offset); } static bool isPush(unsigned Opcode) { @@ -782,7 +781,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // callee-saved register. MBBI = std::prev(MBBI, getRVVCalleeSavedInfo(MF, CSI).size() + getUnmanagedCSI(MF, CSI).size()); - CFIInstEmitterHelper CFIHelper(MBB, MBBI, MachineInstr::FrameSetup); + CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup); // If libcalls are used to spill and restore callee-saved registers, the frame // has two sections; the opaque section managed by the libcalls, and the @@ -810,9 +809,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign()); RVFI->setLibCallStackSize(LibCallFrameSize); - CFIHelper.emitDefCFAOffset(LibCallFrameSize); + CFIBuilder.buildDefCFAOffset(LibCallFrameSize); for (const CalleeSavedInfo &CS : getPushOrLibCallsSavedInfo(MF, CSI)) - CFIHelper.emitOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); + CFIBuilder.buildOffset(CS.getReg(), + MFI.getObjectOffset(CS.getFrameIdx())); } // FIXME (note copied from Lanai): This appears to be overallocating. Needs @@ -839,9 +839,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, } if (RVFI->useQCIInterrupt(MF)) { - CFIHelper.emitDefCFAOffset(QCIInterruptPushAmount); + CFIBuilder.buildDefCFAOffset(QCIInterruptPushAmount); for (const CalleeSavedInfo &CS : getQCISavedInfo(MF, CSI)) - CFIHelper.emitOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); + CFIBuilder.buildOffset(CS.getReg(), + MFI.getObjectOffset(CS.getFrameIdx())); } else if (RVFI->isPushable(MF) && FirstFrameSetup != MBB.end() && isPush(FirstFrameSetup->getOpcode())) { // Use available stack adjustment in push instruction to allocate additional @@ -853,9 +854,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, FirstFrameSetup->getOperand(1).setImm(StackAdj); StackSize -= StackAdj; - CFIHelper.emitDefCFAOffset(RealStackSize - StackSize); + CFIBuilder.buildDefCFAOffset(RealStackSize - StackSize); for (const CalleeSavedInfo &CS : getPushOrLibCallsSavedInfo(MF, CSI)) - CFIHelper.emitOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); + CFIBuilder.buildOffset(CS.getReg(), + MFI.getObjectOffset(CS.getFrameIdx())); } // Allocate space on the stack if necessary. @@ -876,12 +878,12 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // FIXME: assumes exactly one instruction is used to save each callee-saved // register. std::advance(MBBI, getUnmanagedCSI(MF, CSI).size()); - CFIHelper.setInsertPoint(MBBI); + CFIBuilder.setInsertPoint(MBBI); // Iterate over list of callee-saved registers and emit .cfi_offset // directives. for (const CalleeSavedInfo &CS : getUnmanagedCSI(MF, CSI)) - CFIHelper.emitOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); + CFIBuilder.buildOffset(CS.getReg(), MFI.getObjectOffset(CS.getFrameIdx())); // Generate new FP. if (hasFP(MF)) { @@ -900,7 +902,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MachineInstr::FrameSetup, getStackAlign()); } - CFIHelper.emitDefCFA(FPReg, RVFI->getVarArgsSaveSize()); + CFIBuilder.buildDefCFA(FPReg, RVFI->getVarArgsSaveSize()); } uint64_t SecondSPAdjustAmount = 0; @@ -930,7 +932,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, if (!hasFP(MF)) { // Emit .cfi_def_cfa_expression "sp + StackSize + RVVStackSize * vlenb". - CFIHelper.emitCFIInst(createDefCFAExpression( + CFIBuilder.insertCFIInst(createDefCFAExpression( *RI, SPReg, getStackSizeWithRVVPadding(MF), RVVStackSize / 8)); } @@ -1002,8 +1004,8 @@ void RISCVFrameLowering::deallocateStack(MachineFunction &MF, MachineInstr::FrameDestroy, getStackAlign()); StackSize = 0; - CFIInstEmitterHelper(MBB, MBBI, MachineInstr::FrameDestroy) - .emitDefCFAOffset(CFAOffset); + CFIInstBuilder(MBB, MBBI, MachineInstr::FrameDestroy) + .buildDefCFAOffset(CFAOffset); } void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, @@ -1041,8 +1043,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, // callee-saved register. auto FirstScalarCSRRestoreInsn = std::next(MBBI, getRVVCalleeSavedInfo(MF, CSI).size()); - CFIInstEmitterHelper CFIHelper(MBB, FirstScalarCSRRestoreInsn, - MachineInstr::FrameDestroy); + CFIInstBuilder CFIBuilder(MBB, FirstScalarCSRRestoreInsn, + MachineInstr::FrameDestroy); uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF); uint64_t RealStackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount @@ -1064,7 +1066,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, MachineInstr::FrameDestroy, getStackAlign()); if (!hasFP(MF)) - CFIHelper.emitDefCFA(SPReg, RealStackSize); + CFIBuilder.buildDefCFA(SPReg, RealStackSize); emitCalleeSavedRVVEpilogCFI(MBB, FirstScalarCSRRestoreInsn); } @@ -1083,7 +1085,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, MachineInstr::FrameDestroy, getStackAlign()); if (!hasFP(MF)) - CFIHelper.emitDefCFAOffset(FirstSPAdjustAmount); + CFIBuilder.buildDefCFAOffset(FirstSPAdjustAmount); } // Restore the stack pointer using the value of the frame pointer. Only @@ -1104,13 +1106,13 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, } if (hasFP(MF)) - CFIHelper.emitDefCFA(SPReg, RealStackSize); + CFIBuilder.buildDefCFA(SPReg, RealStackSize); // Skip to after the restores of scalar callee-saved registers // FIXME: assumes exactly one instruction is used to restore each // callee-saved register. MBBI = std::next(FirstScalarCSRRestoreInsn, getUnmanagedCSI(MF, CSI).size()); - CFIHelper.setInsertPoint(MBBI); + CFIBuilder.setInsertPoint(MBBI); if (getLibCallID(MF, CSI) != -1) { // tail __riscv_restore_[0-12] instruction is considered as a terminator, @@ -1127,7 +1129,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, // Recover callee-saved registers. for (const CalleeSavedInfo &CS : getUnmanagedCSI(MF, CSI)) - CFIHelper.emitRestore(CS.getReg()); + CFIBuilder.buildRestore(CS.getReg()); if (RVFI->isPushable(MF) && MBBI != MBB.end() && isPop(MBBI->getOpcode())) { // Use available stack adjustment in pop instruction to deallocate stack @@ -1146,14 +1148,14 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, auto NextI = next_nodbg(MBBI, MBB.end()); if (NextI == MBB.end() || NextI->getOpcode() != RISCV::PseudoRET) { ++MBBI; - CFIHelper.setInsertPoint(MBBI); + CFIBuilder.setInsertPoint(MBBI); for (const CalleeSavedInfo &CS : getPushOrLibCallsSavedInfo(MF, CSI)) - CFIHelper.emitRestore(CS.getReg()); + CFIBuilder.buildRestore(CS.getReg()); // Update CFA offset. After CM_POP SP should be equal to CFA, so CFA // offset should be a zero. - CFIHelper.emitDefCFAOffset(0); + CFIBuilder.buildDefCFAOffset(0); } } @@ -1919,14 +1921,14 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI( FixedSize -= ScalarLocalVarSize; } - CFIInstEmitterHelper CFIHelper(MBB, MI, MachineInstr::FrameSetup); + CFIInstBuilder CFIBuilder(MBB, MI, MachineInstr::FrameSetup); for (auto &CS : RVVCSI) { // Insert the spill to the stack frame. int FI = CS.getFrameIdx(); MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg()); unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg()); for (unsigned i = 0; i < NumRegs; ++i) { - CFIHelper.emitCFIInst(createDefCFAOffset( + CFIBuilder.insertCFIInst(createDefCFAOffset( TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i)); } } @@ -1938,13 +1940,13 @@ void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI( const MachineFrameInfo &MFI = MF->getFrameInfo(); const RISCVRegisterInfo &TRI = *STI.getRegisterInfo(); - CFIInstEmitterHelper CFIHelper(MBB, MI, MachineInstr::FrameDestroy); + CFIInstBuilder CFIHelper(MBB, MI, MachineInstr::FrameDestroy); const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo()); for (auto &CS : RVVCSI) { MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg()); unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg()); for (unsigned i = 0; i < NumRegs; ++i) - CFIHelper.emitRestore(BaseReg + i); + CFIHelper.buildRestore(BaseReg + i); } } From 20c6fc61bee241d9fbbb000fb4bc00d9675c1f4c Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 16 Apr 2025 02:35:29 +0300 Subject: [PATCH 4/5] Fix a typo --- llvm/include/llvm/CodeGen/CFIInstBuilder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/include/llvm/CodeGen/CFIInstBuilder.h b/llvm/include/llvm/CodeGen/CFIInstBuilder.h index b8ab512dca014..e799b47a0c974 100644 --- a/llvm/include/llvm/CodeGen/CFIInstBuilder.h +++ b/llvm/include/llvm/CodeGen/CFIInstBuilder.h @@ -22,7 +22,7 @@ class CFIInstBuilder { MachineBasicBlock &MBB; MachineBasicBlock::iterator InsertPt; - /// MIflag to set on a MachineInstr. Typically, FrameSetup or FrameDestroy. + /// MIFlag to set on a MachineInstr. Typically, FrameSetup or FrameDestroy. MachineInstr::MIFlag MIFlag; /// Selects DWARF register numbering: debug or exception handling. Should be From 4e1f3ac9f3321cabcff26b927dcf6a28368ae9b9 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 16 Apr 2025 18:06:02 +0300 Subject: [PATCH 5/5] Fix a mistake --- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index c45ff6e389cb5..cefe7a732519d 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -467,7 +467,7 @@ void RISCVFrameLowering::allocateAndProbeStackForRVV( .setMIFlag(Flag); TII->mulImm(MF, MBB, MBBI, DL, TargetReg, NumOfVReg, Flag); - CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameDestroy); + CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup); if (EmitCFI) { // Set the CFA register to TargetReg. CFIBuilder.buildDefCFA(TargetReg, -Amount);