From 3c0f7c97372ed677f70d610666f9a9837be75855 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 16 Apr 2025 08:50:17 +0530 Subject: [PATCH 1/2] [RISCV] Add basic ISel patterns for Xqcilo instructions This patch adds instruction selection patterns for generating the 48 bit load/store instructions that are a part of the Qualcomm uC Xqcilo vendor extension. --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 27 ++++ llvm/test/CodeGen/RISCV/qc-xqcilo.ll | 143 ++++++++++++++++++++ 2 files changed, 170 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/qc-xqcilo.ll diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 2458bda80b1d6..6736b0f1d0328 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -159,6 +159,11 @@ def bare_simm32_lsb0 : Operand { let OperandType = "OPERAND_PCREL"; } +def AddLike: PatFrags<(ops node:$A, node:$B), + [(add node:$A, node:$B), (or node:$A, node:$B)], [{ + return CurDAG->isBaseWithConstantOffset(SDValue(N, 0)); +}]>; + //===----------------------------------------------------------------------===// // Instruction Formats //===----------------------------------------------------------------------===// @@ -1239,6 +1244,14 @@ class PatGprNoX0Simm32NoSimm26 : Pat<(i32 (OpNode (i32 GPRNoX0:$rs1), simm32_nosimm26:$imm)), (Inst GPRNoX0:$rs1, simm32_nosimm26:$imm)>; +class QC48LdPat + : Pat<(i32 (LoadOp (AddLike (i32 GPR:$rs1), simm26_nosimm12:$imm26))), + (Inst GPR:$rs1, simm26_nosimm12:$imm26)>; + +class QC48StPat + : Pat<(StoreOp (i32 GPR:$rs2), (AddLike (i32 GPR:$rs1), simm26_nosimm12:$imm26)), + (Inst GPR:$rs2, GPR:$rs1, simm26_nosimm12:$imm26)>; + /// Simple arithmetic operations let Predicates = [HasVendorXqcilia, IsRV32] in { @@ -1253,5 +1266,19 @@ def : PatGprNoX0Simm26NoSimm12; def : PatGprNoX0Simm26NoSimm12; } // Predicates = [HasVendorXqcilia, IsRV32] +let Predicates = [HasVendorXqcilo, IsRV32], AddedComplexity = 2 in { + def : QC48LdPat; + def : QC48LdPat; // Prefer unsigned due to no c.lb in Zcb. + def : QC48LdPat; + def : QC48LdPat; + def : QC48LdPat; + def : QC48LdPat; + def : QC48LdPat; + + def : QC48StPat; + def : QC48StPat; + def : QC48StPat; +} // Predicates = [HasVendorXqcilo, IsRV32], AddedComplexity = 2 + let Predicates = [HasVendorXqciint, IsRV32] in def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>; diff --git a/llvm/test/CodeGen/RISCV/qc-xqcilo.ll b/llvm/test/CodeGen/RISCV/qc-xqcilo.ll new file mode 100644 index 0000000000000..fb06f21b3ab98 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/qc-xqcilo.ll @@ -0,0 +1,143 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32I +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32IXQCILO + +define i32 @lb_ri(i8* %a) { +; RV32I-LABEL: lb_ri: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a1, 2 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: lb a0, 1808(a0) +; RV32I-NEXT: ret +; +; RV32IXQCILO-LABEL: lb_ri: +; RV32IXQCILO: # %bb.0: +; RV32IXQCILO-NEXT: qc.e.lb a0, 10000(a0) +; RV32IXQCILO-NEXT: ret + %1 = getelementptr i8, i8* %a, i32 10000 + %2 = load i8, i8* %1 + %3 = sext i8 %2 to i32 + ret i32 %3 +} + +define i32 @lbu_ri(i8* %a) { +; RV32I-LABEL: lbu_ri: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a1, 1048574 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: lbu a0, 192(a0) +; RV32I-NEXT: ret +; +; RV32IXQCILO-LABEL: lbu_ri: +; RV32IXQCILO: # %bb.0: +; RV32IXQCILO-NEXT: qc.e.lbu a0, -8000(a0) +; RV32IXQCILO-NEXT: ret + %1 = getelementptr i8, i8* %a, i32 -8000 + %2 = load i8, i8* %1 + %3 = zext i8 %2 to i32 + ret i32 %3 +} + +define i32 @lh_ri(i16* %a) { +; RV32I-LABEL: lh_ri: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a1, 11 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: lhu a0, -612(a0) +; RV32I-NEXT: ret +; +; RV32IXQCILO-LABEL: lh_ri: +; RV32IXQCILO: # %bb.0: +; RV32IXQCILO-NEXT: qc.e.lhu a0, 44444(a0) +; RV32IXQCILO-NEXT: ret + %1 = getelementptr i16, i16* %a, i32 22222 + %2 = load i16, i16* %1 + %3 = zext i16 %2 to i32 + ret i32 %3 +} + +define i32 @lhu_ri(i16* %a) { +; RV32I-LABEL: lhu_ri: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a1, 1048570 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: lhu a0, 120(a0) +; RV32I-NEXT: ret +; +; RV32IXQCILO-LABEL: lhu_ri: +; RV32IXQCILO: # %bb.0: +; RV32IXQCILO-NEXT: qc.e.lhu a0, -24456(a0) +; RV32IXQCILO-NEXT: ret + %1 = getelementptr i16, i16* %a, i32 -12228 + %2 = load i16, i16* %1 + %3 = zext i16 %2 to i32 + ret i32 %3 +} + +define i32 @lw_ri(i32* %a) { +; RV32I-LABEL: lw_ri: +; RV32I: # %bb.0: +; RV32I-NEXT: addi a0, a0, 2047 +; RV32I-NEXT: lw a0, 1953(a0) +; RV32I-NEXT: ret +; +; RV32IXQCILO-LABEL: lw_ri: +; RV32IXQCILO: # %bb.0: +; RV32IXQCILO-NEXT: qc.e.lw a0, 4000(a0) +; RV32IXQCILO-NEXT: ret + %1 = getelementptr i32, i32* %a, i32 1000 + %2 = load i32, i32* %1 + ret i32 %2 +} + +define void @sb_ri(i8* %a, i8 %b) { +; RV32I-LABEL: sb_ri: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a2, 2 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: sb a1, 1808(a0) +; RV32I-NEXT: ret +; +; RV32IXQCILO-LABEL: sb_ri: +; RV32IXQCILO: # %bb.0: +; RV32IXQCILO-NEXT: qc.e.sb a1, 10000(a0) +; RV32IXQCILO-NEXT: ret + %1 = getelementptr i8, i8* %a, i32 10000 + store i8 %b, i8* %1 + ret void +} + +define void @sh_ri(i16* %a, i16 %b) { +; RV32I-LABEL: sh_ri: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a2, 11 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: sh a1, -612(a0) +; RV32I-NEXT: ret +; +; RV32IXQCILO-LABEL: sh_ri: +; RV32IXQCILO: # %bb.0: +; RV32IXQCILO-NEXT: qc.e.sh a1, 44444(a0) +; RV32IXQCILO-NEXT: ret + %1 = getelementptr i16, i16* %a, i32 22222 + store i16 %b, i16* %1 + ret void +} + +define void @sw_ri(i32* %a, i32 %b) { +; RV32I-LABEL: sw_ri: +; RV32I: # %bb.0: +; RV32I-NEXT: addi a0, a0, 2047 +; RV32I-NEXT: sw a1, 1953(a0) +; RV32I-NEXT: ret +; +; RV32IXQCILO-LABEL: sw_ri: +; RV32IXQCILO: # %bb.0: +; RV32IXQCILO-NEXT: qc.e.sw a1, 4000(a0) +; RV32IXQCILO-NEXT: ret + %1 = getelementptr i32, i32* %a, i32 1000 + store i32 %b, i32* %1 + ret void +} From 34bba1ee504c5758314fc4fd476a54b03392d459 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 16 Apr 2025 09:31:03 +0530 Subject: [PATCH 2/2] Rename test --- llvm/test/CodeGen/RISCV/{qc-xqcilo.ll => xqcilo.ll} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename llvm/test/CodeGen/RISCV/{qc-xqcilo.ll => xqcilo.ll} (100%) diff --git a/llvm/test/CodeGen/RISCV/qc-xqcilo.ll b/llvm/test/CodeGen/RISCV/xqcilo.ll similarity index 100% rename from llvm/test/CodeGen/RISCV/qc-xqcilo.ll rename to llvm/test/CodeGen/RISCV/xqcilo.ll