[SPIRV]Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point and name change of SPV_INTEL_arbitrary_precision_integers to SPV_ALTERA_arbitrary_precision_integers #136085

aadeshps-mcw · 2025-04-17T06:12:52Z

--Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point
--Added test files for extension SPV_ALTERA_arbitrary_precision_fixed_point

github-actions · 2025-04-17T06:13:17Z

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llvmbot · 2025-04-17T06:13:51Z

@llvm/pr-subscribers-mlir-spirv
@llvm/pr-subscribers-mlir

@llvm/pr-subscribers-backend-spir-v

Author: Aadesh PremKumar (aadeshps-mcw)

Changes

--Added support for extension SPV_INTEL_arbitrary_precision_fixed_point
--Added test files for extension SPV_INTEL_arbitrary_precision_fixed_point

Patch is 40.09 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/136085.diff

7 Files Affected:

(modified) llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp (+75-1)
(modified) llvm/lib/Target/SPIRV/SPIRVBuiltins.td (+14)
(modified) llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp (+4-1)
(modified) llvm/lib/Target/SPIRV/SPIRVInstrInfo.td (+24)
(modified) llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp (+21)
(modified) llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td (+2)
(added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll (+563)

diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 16364ab30f280..77f3535bb9e87 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -697,7 +697,8 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
                                  MachineIRBuilder &MIRBuilder,
                                  SPIRVGlobalRegistry *GR) {
   if (Call->isSpirvOp())
-    return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
+    return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call,
+                              Register(0));
 
   Register ScopeRegister =
       buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -2282,6 +2283,77 @@ static bool generateBindlessImageINTELInst(const SPIRV::IncomingCall *Call,
   return buildBindlessImageINTELInst(Call, Opcode, MIRBuilder, GR);
 }
 
+static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call,
+                                  unsigned Opcode, MachineIRBuilder &MIRBuilder,
+                                  SPIRVGlobalRegistry *GR) {
+  MachineRegisterInfo *MRI = MIRBuilder.getMRI();
+  SmallVector<uint32_t, 1> ImmArgs;
+  Register InputReg = Call->Arguments[0];
+  const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType);
+  bool IsSRet = RetTy->isVoidTy();
+
+  if (IsSRet) {
+    const LLT ValTy = MRI->getType(InputReg);
+    Register ActualRetValReg = MRI->createGenericVirtualRegister(ValTy);
+    SPIRVType *InstructionType =
+        GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
+    InputReg = Call->Arguments[1];
+    auto InputType = GR->getTypeForSPIRVType(GR->getSPIRVTypeForVReg(InputReg));
+    Register PtrInputReg;
+    if (InputType->getTypeID() == llvm::Type::TypeID::TypedPointerTyID) {
+      LLT InputLLT = MRI->getType(InputReg);
+      PtrInputReg = MRI->createGenericVirtualRegister(InputLLT);
+      SPIRVType *PtrType =
+          GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
+      MachineMemOperand *MMO1 = MIRBuilder.getMF().getMachineMemOperand(
+          MachinePointerInfo(), MachineMemOperand::MOLoad,
+          InputLLT.getSizeInBytes(), Align(4));
+      MIRBuilder.buildLoad(PtrInputReg, InputReg, *MMO1);
+      MRI->setRegClass(PtrInputReg, &SPIRV::iIDRegClass);
+      GR->assignSPIRVTypeToVReg(PtrType, PtrInputReg, MIRBuilder.getMF());
+    }
+
+    for (unsigned index = 2; index < 7; index++) {
+      ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
+    }
+
+    // Emit the instruction
+    auto MIB = MIRBuilder.buildInstr(Opcode)
+                   .addDef(ActualRetValReg)
+                   .addUse(GR->getSPIRVTypeID(InstructionType));
+    if (PtrInputReg)
+      MIB.addUse(PtrInputReg);
+    else
+      MIB.addUse(InputReg);
+
+    for (uint32_t Imm : ImmArgs)
+      MIB.addImm(Imm);
+    unsigned Size = ValTy.getSizeInBytes();
+    // Store result to the pointer passed in Arg[0]
+    MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand(
+        MachinePointerInfo(), MachineMemOperand::MOStore, Size, Align(4));
+    MRI->setRegClass(ActualRetValReg, &SPIRV::pIDRegClass);
+    MIRBuilder.buildStore(ActualRetValReg, Call->Arguments[0], *MMO);
+    return true;
+  } else {
+    for (unsigned index = 1; index < 6; index++)
+      ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
+
+    return buildOpFromWrapper(MIRBuilder, Opcode, Call,
+                              GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
+  }
+}
+
+static bool generateAPFixedPointInst(const SPIRV::IncomingCall *Call,
+                                     MachineIRBuilder &MIRBuilder,
+                                     SPIRVGlobalRegistry *GR) {
+  const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
+  unsigned Opcode =
+      SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
+
+  return buildAPFixedPointInst(Call, Opcode, MIRBuilder, GR);
+}
+
 static bool
 generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
                                         MachineIRBuilder &MIRBuilder,
@@ -2875,6 +2947,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
     return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
   case SPIRV::BindlessINTEL:
     return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
+  case SPIRV::ArbitraryPrecisionFixedPoint:
+    return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
   case SPIRV::TernaryBitwiseINTEL:
     return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
   }
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index b504e7b04d336..7650b69b48d51 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -67,6 +67,7 @@ def CoopMatr : BuiltinGroup;
 def ICarryBorrow : BuiltinGroup;
 def ExtendedBitOps : BuiltinGroup;
 def BindlessINTEL : BuiltinGroup;
+def ArbitraryPrecisionFixedPoint : BuiltinGroup;
 def TernaryBitwiseINTEL : BuiltinGroup;
 
 //===----------------------------------------------------------------------===//
@@ -1132,6 +1133,19 @@ defm : DemangledNativeBuiltin<"clock_read_hilo_device", OpenCL_std, KernelClock,
 defm : DemangledNativeBuiltin<"clock_read_hilo_work_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
 defm : DemangledNativeBuiltin<"clock_read_hilo_sub_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
 
+//SPV_INTEL_arbitrary_precision_fixed_point
+defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
+
 //===----------------------------------------------------------------------===//
 // Class defining an atomic instruction on floating-point numbers.
 //
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 86702bbe58f09..6f9c7f7705bfd 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -94,7 +94,10 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
         {"SPV_INTEL_fp_max_error",
          SPIRV::Extension::Extension::SPV_INTEL_fp_max_error},
         {"SPV_INTEL_ternary_bitwise_function",
-         SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
+         SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
+        {"SPV_INTEL_arbitrary_precision_fixed_point",
+         SPIRV::Extension::Extension::
+             SPV_INTEL_arbitrary_precision_fixed_point}};
 
 bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
                                   StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 53064ebb51271..2b40eebbfd7b2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -932,3 +932,27 @@ def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops),
 // SPV_INTEL_ternary_bitwise_function
 def OpBitwiseFunctionINTEL: Op<6242, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c, ID:$lut_index),
                   "$res = OpBitwiseFunctionINTEL $type $a $b $c $lut_index">;
+
+//SPV_INTEL_arbitrary_precision_fixed_point
+def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+      "$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
\ No newline at end of file
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index b1e5e4328cd32..698f554ab02e6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1516,6 +1516,27 @@ void addInstrRequirements(const MachineInstr &MI,
     Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
     Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
     break;
+  case SPIRV::OpFixedCosINTEL:
+  case SPIRV::OpFixedSinINTEL:
+  case SPIRV::OpFixedCosPiINTEL:
+  case SPIRV::OpFixedSinPiINTEL:
+  case SPIRV::OpFixedExpINTEL:
+  case SPIRV::OpFixedLogINTEL:
+  case SPIRV::OpFixedRecipINTEL:
+  case SPIRV::OpFixedSqrtINTEL:
+  case SPIRV::OpFixedSinCosINTEL:
+  case SPIRV::OpFixedSinCosPiINTEL:
+  case SPIRV::OpFixedRsqrtINTEL:
+    if (!ST.canUseExtension(
+            SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
+      report_fatal_error("This instruction requires the "
+                         "following SPIR-V extension: "
+                         "SPV_INTEL_arbitrary_precision_fixed_point",
+                         false);
+    Reqs.addExtension(
+        SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
+    Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
+    break;
   case SPIRV::OpGroupIMulKHR:
   case SPIRV::OpGroupFMulKHR:
   case SPIRV::OpGroupBitwiseAndKHR:
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 0db8a37f8683c..feb41d72b3d66 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -314,6 +314,7 @@ defm SPV_INTEL_long_composites : ExtensionOperand<117>;
 defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
 defm SPV_INTEL_fp_max_error : ExtensionOperand<119>;
 defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
+defm SPV_INTEL_arbitrary_precision_fixed_point : ExtensionOperand<121>;
 
 //===----------------------------------------------------------------------===//
 // Multiclass used to define Capabilities enum values and at the same time
@@ -514,6 +515,7 @@ defm LongCompositesINTEL : CapabilityOperand<6089, 0, 0, [SPV_INTEL_long_composi
 defm BindlessImagesINTEL : CapabilityOperand<6528, 0, 0, [SPV_INTEL_bindless_images], []>;
 defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory_access_aliasing], []>;
 defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
+defm ArbitraryPrecisionFixedPointINTEL : CapabilityOperand<5922, 0, 0, [SPV_INTEL_arbitrary_precision_fixed_point], []>;
 defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
new file mode 100644
index 0000000000000..bbab69378aab4
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
@@ -0,0 +1,563 @@
+; SYCL source (compiled with -S -emit-llvm -fsycl-device-only):
+; template <int W, int rW, bool S, int I, int rI>
+; void sqrt() {
+;   ap_int<W> a;
+;   auto ap_fixed_Sqrt = __spirv_FixedSqrtINTEL<W,rW>(a, S, I, rI);
+;   ap_int<rW> b;
+;   auto ap_fixed_Sqrt_b = __spirv_FixedSqrtINTEL<rW, W>(b, S, I, rI);
+;   ap_int<rW> c;
+;   auto ap_fixed_Sqrt_c = __spirv_FixedSqrtINTEL<rW, W>(c, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void recip() {
+;   ap_int<W> a;
+;   auto ap_fixed_Recip = __spirv_FixedRecipINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void rsqrt() {
+;   ap_int<W> a;
+;   auto ap_fixed_Rsqrt = __spirv_FixedRsqrtINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void sin() {
+;   ap_int<W> a;
+;   auto ap_fixed_Sin = __spirv_FixedSinINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void cos() {
+;   ap_int<W> a;
+;   auto ap_fixed_Cos = __spirv_FixedCosINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void sin_cos() {
+;   ap_int<W> a;
+;   auto ap_fixed_SinCos = __spirv_FixedSinCosINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void sin_pi() {
+;   ap_int<W> a;
+;   auto ap_fixed_SinPi = __spirv_FixedSinPiINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void cos_pi() {
+;   ap_int<W> a;
+;   auto ap_fixed_CosPi = __spirv_FixedCosPiINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void sin_cos_pi() {
+;   ap_int<W> a;
+;   auto ap_fixed_SinCosPi = __spirv_FixedSinCosPiINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void log() {
+;   ap_int<W> a;
+;   auto ap_fixed_Log = __spirv_FixedLogINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void exp() {
+;   ap_int<W> a;
+;   auto ap_fixed_Exp = __spirv_FixedExpINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <typename name, typename Func>
+; __attribute__((sycl_kernel)) void kernel_single_task(Func kernelFunc) {
+;   kernelFunc();
+; }
+
+; int main() {
+;   kernel_single_task<class kernel_function>([]() {
+;     sqrt<13, 5, false, 2, 2>();
+;     recip<3, 8, true, 4, 4>();
+;     rsqrt<11, 10, false, 8, 6>();
+;     sin<17, 11, true, 7, 5>();
+;     cos<35, 28, false, 9, 3>();
+;     sin_cos<31, 20, true, 10, 12>();
+;     sin_pi<60, 5, false, 2, 2>();
+;     cos_pi<28, 16, false, 8, 5>();
+;     sin_cos_pi<13, 5, false, 2, 2>();
+;     log<64, 44, true, 24, 22>();
+;     exp<44, 34, false, 20, 20>();
+;     exp<68, 68, false, 20, 20>();
+;   });
+;   return 0;
+; }
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s 
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - -filetype=obj | spirv-val %}
+
+
+; CHECK-DAG: OpCapability Kernel
+; CHECK-DAG: OpCapability ArbitraryPrecisionIntegersINTEL
+; CHECK-DAG: OpCapability ArbitraryPrecisionFixedPointINTEL
+; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_fixed_point"
+; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_integers"
+
+; CHECK-DAG: %[[Ty_8:[0-9]+]] = OpTypeInt 8 0
+; CHECK-DAG: %[[Ty_13:[0-9]+]] = OpTypeInt 13 0
+; CHECK-DAG: %[[Ty_5:[0-9]+]] = OpTypeInt 5 0
+; CHECK-DAG: %[[Ty_3:[0-9]+]] = OpTypeInt 3 0
+; CHECK-DAG: %[[Ty_11:[0-9]+]] = OpTypeInt 11 0
+; CHECK-DAG: %[[Ty_10:[0-9]+]] = OpTypeInt 10 0
+; CHECK-DAG: %[[Ty_17:[0-9]+]] = OpTypeInt 17 0
+; CHECK-DAG: %[[Ty_35:[0-9]+]] = OpTypeInt 35 0
+; CHECK-DAG: %[[Ty_28:[0-9]+]] = OpTypeInt 28 0
+; CHECK-DAG: %[[Ty_31:[0-9]+]] = OpTypeInt 31 0
+; CHECK-DAG: %[[Ty_40:[0-9]+]] = OpTypeInt 40 0
+; CHECK-DAG: %[[Ty_60:[0-9]+]] = OpTypeInt 60 0
+; CHECK-DAG: %[[Ty_16:[0-9]+]] = OpTypeInt 16 0
+; CHECK-DAG: %[[Ty_64:[0-9]+]] = OpTypeInt 64 0
+; CHECK-DAG: %[[Ty_44:[0-9]+]] = OpTypeInt 44 0
+; CHECK-DAG: %[[Ty_34:[0-9]+]] = OpTypeInt 34 0
+; CHECK-DAG: %[[Ty_51:[0-9]+]] = OpTypeInt 51 0
+
+
+
+; CHECK:        %[[Sqrt_InId:[0-9]+]] = OpLoad %[[Ty_13]]
+; CHECK-NEXT:  %[[#]] = OpFixedSqrtINTEL %[[Ty_5]] %[[Sqrt_InId]] 0 2 2 0 0
+
+; CHECK:        %[[Sqrt_InId_B:[0-9]+]] = OpLoad %[[Ty_5]]
+; CHECK-NEXT:  %[[#]] = OpFixedSqrtINTEL %[[Ty_13]] %[[Sqrt_InId_B]] 0 2 2 0 0
+
+; CHECK:        %[[Sqrt_InId_C:[0-9]+]] = OpLoad %[[Ty_5]]
+; CHECK-NEXT:  %[[#]] = OpFixedSqrtINTEL %[[Ty_13]] %[[Sqrt_InId_C]] 0 2 2 0 0
+
+
+; CHECK:        %[[Recip_InId:[0-9]+]] = OpLoad %[[Ty_3]]
+; CHECK-NEXT:  %[[#]] = OpFixedRecipINTEL %[[Ty_8]] %[[Recip_InId]] 1 4 4 0 0
+
+; CHECK:        %[[Rsqrt_InId:[0-9]+]] = OpLoad %[[Ty_11]]
+; CHECK-NEXT:  %[[#]] = OpFixedRsqrtINTEL %[[Ty_10]] %[[Rsqrt_InId]] 0 8 6 0 0
+
+; CHECK:        %[[Sin_InId:[0-9]+]] = OpLoad %[[Ty_17]]
+; CHECK-NEXT:  %[[#]] = OpFixedSinINTEL %[[Ty_11]] %[[Sin_InId]] 1 7 5 0 0
+
+; CHECK:        %[[Cos_InId:[0-9]+]] = OpLoad %[[Ty_35]]
+; CHECK-NEXT:  %[[#]] = OpFixedCosINTEL %[[Ty_28]] %[[Cos_InId]] 0 9 3 0 0
+
+; CHECK:        %[[SinCos_InId:[0-9]+]] = OpLoad %[[Ty_31]]
+; CHECK-NEXT:  %[[#]] = OpFixedSinCosINTEL %[[Ty_40]] %[[SinCos_InId]] 1 10 12 0 0
+
+; CHECK:        %[[SinPi_InId:[0-9]+]] = OpLoad %[[Ty_60]]
+; CHECK-NEXT:  %[[#]] = OpFixedSinPiINTEL %[[Ty_5]] %[[SinPi_InId]] 0 2 2 0 0
+
+; CHECK:        %[[CosPi_InId:[0-9]+]] = OpLoad %[[Ty_28]]
+; CHECK-NEXT:  %[[#]] = OpFixedCosPiINTEL %[[Ty_16]] %[[CosPi_InId]] 0 8 5 0 0
+
+; CHECK:        %[[SinCosPi_InId:[0-9]+]] = OpLoad %[[Ty_13]]
+; CHECK-NEXT:  %[[#]] = OpFixedSinCosPiINTEL %[[Ty_10]] %[[SinCosPi_InId]] 0 2 2 0 0
+
+; CHECK:        %[[Log_InId:[0-9]+]] = OpLoad %[[Ty_64]]
+; CHECK-NEXT:  %[[#]] = OpFixedLogINTEL %[[Ty_44]] %[[Log_InId]] 1 24 22 0 0
+
+; CHECK:        %[[Exp_InId:[0-9]+]] = OpLoad %[[T...
[truncated]

aadeshps-mcw · 2025-05-06T04:59:31Z

Ping

MrSidims

Thank you for the contribution! There are few nits, other than that the patch is LGTM.

I have one logistical question though, @bashbaug I see this extensions (as well as few others) moved into Altera folder in SPIR-V Registry. Are there plans to rename the extensions themselves?

..._INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll

llvm/docs/SPIRVUsage.rst

llvm/lib/Target/SPIRV/SPIRVInstrInfo.td

..._INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll

aadeshps-mcw · 2025-06-05T05:14:01Z

Ping

michalpaszkowski · 2025-08-03T20:03:54Z

@aadeshps-mcw Could you please rebase the PR (to solve the merge conflicts)?

aadeshps-mcw · 2025-09-29T05:10:41Z

Ping

kuhar

Can you submit MLIR changes as a separate PR?

aadeshps-mcw · 2025-11-06T13:22:14Z

@kuhar Have made a separate PR for the MLIR.
#166771 is the PR consisting of changes in the MLIR.

llvmbot added the backend:SPIR-V label Apr 17, 2025

aadeshps-mcw force-pushed the fixed_point branch from 5dc861e to d691a1e Compare April 17, 2025 06:55

MrSidims requested review from MrSidims and VyacheslavLevytskyy April 17, 2025 11:57

aadeshps-mcw force-pushed the fixed_point branch from d691a1e to 452be45 Compare May 6, 2025 04:08

MrSidims reviewed May 6, 2025

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MrSidims approved these changes May 7, 2025

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MrSidims requested a review from michalpaszkowski May 7, 2025 10:36

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aadeshps-mcw force-pushed the fixed_point branch from e72e7ad to 6fb0d9c Compare May 13, 2025 07:00

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aadeshps-mcw force-pushed the fixed_point branch from 6fb0d9c to bf85d14 Compare May 16, 2025 05:13

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aadeshps-mcw force-pushed the fixed_point branch from 65f2c9d to 09b60b8 Compare November 6, 2025 05:21

aadeshps-mcw requested review from antiagainst and kuhar as code owners November 6, 2025 05:21

llvmbot added mlir:spirv mlir labels Nov 6, 2025

aadeshps-mcw force-pushed the fixed_point branch from 09b60b8 to 821a34d Compare November 6, 2025 05:33

aadeshps-mcw changed the title ~~[SPIRV]Added support for extension SPV_INTEL_arbitrary_precision_fixed_point~~ [SPIRV]Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point Nov 6, 2025

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kuhar reviewed Nov 6, 2025

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aadeshps-mcw force-pushed the fixed_point branch from 4624554 to d7f52dc Compare November 6, 2025 13:10

aadeshps-mcw added 5 commits November 13, 2025 13:10

--Updated the test file

88ecae9

--Updated files after the conflict resolution

449ef3d

--Updated SPIRVInstrInfo.td file

5cb0417

--Rebased the PR to solve merge conflicts.

5b5d0ac

--Changes in Name of extensions from INTEL to ALTERA.

1b02298

aadeshps-mcw force-pushed the fixed_point branch from 8bdc943 to 1b02298 Compare November 13, 2025 07:41

[SPIRV]Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point and name change of SPV_INTEL_arbitrary_precision_integers to SPV_ALTERA_arbitrary_precision_integers #136085

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[SPIRV]Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point and name change of SPV_INTEL_arbitrary_precision_integers to SPV_ALTERA_arbitrary_precision_integers #136085

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