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[Mips] Guard emission of CFI instructions by MF.needsFrameMoves() #136108

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[Mips] Guard emission of CFI instructions by MF.needsFrameMoves() #136108

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958fee1
[Mips] Guard emission of CFI instructions by `MF.needsFrameMoves()`
s-barannikov Apr 17, 2025
8ab109e
Merge remote-tracking branch 'upstream/main' into cfi/mips
s-barannikov Apr 21, 2025
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33 changes: 8 additions & 25 deletions llvm/lib/Target/Mips/Mips16FrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@
#include "MipsRegisterInfo.h"
#include "MipsSubtarget.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
Expand All @@ -24,9 +25,6 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/MathExtras.h"
#include <cstdint>
#include <vector>
Expand All @@ -52,32 +50,17 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
// No need to allocate space on the stack.
if (StackSize == 0 && !MFI.adjustsStack()) return;

const MCRegisterInfo *MRI = MF.getContext().getRegisterInfo();

// Adjust stack.
TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);

// emit ".cfi_def_cfa_offset StackSize"
unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);

const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();

if (!CSI.empty()) {
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();

for (const CalleeSavedInfo &I : CSI) {
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
MCRegister Reg = I.getReg();
unsigned DReg = MRI->getDwarfRegNum(Reg, true);
unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, DReg, Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
if (MF.needsFrameMoves()) {
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::NoFlags);
CFIBuilder.buildDefCFAOffset(StackSize);

for (const CalleeSavedInfo &I : MFI.getCalleeSavedInfo())
CFIBuilder.buildOffset(I.getReg(), MFI.getObjectOffset(I.getFrameIdx()));
}

if (hasFP(MF))
BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
.addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
Expand Down
84 changes: 28 additions & 56 deletions llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
Expand All @@ -33,8 +34,6 @@
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
Expand Down Expand Up @@ -426,76 +425,54 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
// No need to allocate space on the stack.
if (StackSize == 0 && !MFI.adjustsStack()) return;

const MCRegisterInfo *MRI = MF.getContext().getRegisterInfo();
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::NoFlags);
bool NeedsDwarfCFI = MF.needsFrameMoves();

// Adjust stack.
TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);

// emit ".cfi_def_cfa_offset StackSize"
unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
if (NeedsDwarfCFI)
CFIBuilder.buildDefCFAOffset(StackSize);

if (MF.getFunction().hasFnAttribute("interrupt"))
emitInterruptPrologueStub(MF, MBB);

const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();

if (!CSI.empty()) {
// Find the instruction past the last instruction that saves a callee-saved
// register to the stack.
for (unsigned i = 0; i < CSI.size(); ++i)
++MBBI;
// Find the instruction past the last instruction that saves a callee-saved
// register to the stack.
std::advance(MBBI, CSI.size());
CFIBuilder.setInsertPoint(MBBI);

// Iterate over list of callee-saved registers and emit .cfi_offset
// directives.
// Iterate over list of callee-saved registers and emit .cfi_offset
// directives.
if (NeedsDwarfCFI) {
for (const CalleeSavedInfo &I : CSI) {
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
MCRegister Reg = I.getReg();

// If Reg is a double precision register, emit two cfa_offsets,
// one for each of the paired single precision registers.
if (Mips::AFGR64RegClass.contains(Reg)) {
unsigned Reg0 =
MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
unsigned Reg1 =
MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
MCRegister Reg0 = RegInfo.getSubReg(Reg, Mips::sub_lo);
MCRegister Reg1 = RegInfo.getSubReg(Reg, Mips::sub_hi);

if (!STI.isLittle())
std::swap(Reg0, Reg1);

unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);

CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
CFIBuilder.buildOffset(Reg0, Offset);
CFIBuilder.buildOffset(Reg1, Offset + 4);
} else if (Mips::FGR64RegClass.contains(Reg)) {
unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
MCRegister Reg0 = Reg;
MCRegister Reg1 = Reg + 1;

if (!STI.isLittle())
std::swap(Reg0, Reg1);

unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);

CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
CFIBuilder.buildOffset(Reg0, Offset);
CFIBuilder.buildOffset(Reg1, Offset + 4);
} else {
// Reg is either in GPR32 or FGR32.
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
CFIBuilder.buildOffset(Reg, Offset);
}
}
}
Expand All @@ -511,13 +488,11 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
}

// Emit .cfi_offset directives for eh data registers.
for (int I = 0; I < 4; ++I) {
int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I));
unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true);
unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg, Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
if (NeedsDwarfCFI) {
for (int I = 0; I < 4; ++I) {
int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I));
CFIBuilder.buildOffset(ABI.GetEhDataReg(I), Offset);
}
}
}

Expand All @@ -527,11 +502,8 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
.setMIFlag(MachineInstr::FrameSetup);

// emit ".cfi_def_cfa_register $fp"
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
nullptr, MRI->getDwarfRegNum(FP, true)));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
if (NeedsDwarfCFI)
CFIBuilder.buildDefCFARegister(FP);

if (RegInfo.hasStackRealignment(MF)) {
// addiu $Reg, $zero, -MaxAlignment
Expand Down
27 changes: 10 additions & 17 deletions llvm/test/CodeGen/Mips/analyzebranch.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -132,7 +132,7 @@ define double @foo(double %a, double %b) nounwind readnone {
; MIPS64R6-NEXT: mfc1 $1, $f1
; MIPS64R6-NEXT: andi $1, $1, 1
; MIPS64R6-NEXT: bnez $1, .LBB0_2
; MIPS64R6-NEXT: mov.d $f0, $f12
; MIPS64R6-NEXT: mov.d $f0, $f12
; MIPS64R6-NEXT: # %bb.1: # %if.else
; MIPS64R6-NEXT: dmtc1 $zero, $f0
; MIPS64R6-NEXT: cmp.ule.d $f1, $f13, $f0
Expand Down Expand Up @@ -167,11 +167,10 @@ define void @f1(float %f) nounwind {
; MIPS32-LABEL: f1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: mtc1 $zero, $f0
; MIPS32-NEXT: c.eq.s $f12, $f0
; MIPS32-NEXT: bc1f $BB1_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: sw $ra, 20($sp)
; MIPS32-NEXT: # %bb.1: # %if.end
; MIPS32-NEXT: jal f2
; MIPS32-NEXT: nop
Expand All @@ -185,11 +184,10 @@ define void @f1(float %f) nounwind {
; MIPS32R2-LABEL: f1:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: addiu $sp, $sp, -24
; MIPS32R2-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32R2-NEXT: mtc1 $zero, $f0
; MIPS32R2-NEXT: c.eq.s $f12, $f0
; MIPS32R2-NEXT: bc1f $BB1_2
; MIPS32R2-NEXT: nop
; MIPS32R2-NEXT: sw $ra, 20($sp)
; MIPS32R2-NEXT: # %bb.1: # %if.end
; MIPS32R2-NEXT: jal f2
; MIPS32R2-NEXT: nop
Expand All @@ -203,13 +201,12 @@ define void @f1(float %f) nounwind {
; MIPS32r6-LABEL: f1:
; MIPS32r6: # %bb.0: # %entry
; MIPS32r6-NEXT: addiu $sp, $sp, -24
; MIPS32r6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32r6-NEXT: mtc1 $zero, $f0
; MIPS32r6-NEXT: cmp.eq.s $f0, $f12, $f0
; MIPS32r6-NEXT: mfc1 $1, $f0
; MIPS32r6-NEXT: andi $1, $1, 1
; MIPS32r6-NEXT: beqzc $1, $BB1_2
; MIPS32r6-NEXT: nop
; MIPS32r6-NEXT: beqz $1, $BB1_2
; MIPS32r6-NEXT: sw $ra, 20($sp)
; MIPS32r6-NEXT: # %bb.1: # %if.end
; MIPS32r6-NEXT: jal f2
; MIPS32r6-NEXT: nop
Expand All @@ -223,11 +220,10 @@ define void @f1(float %f) nounwind {
; MIPS4-LABEL: f1:
; MIPS4: # %bb.0: # %entry
; MIPS4-NEXT: daddiu $sp, $sp, -16
; MIPS4-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
; MIPS4-NEXT: mtc1 $zero, $f0
; MIPS4-NEXT: c.eq.s $f12, $f0
; MIPS4-NEXT: bc1f .LBB1_2
; MIPS4-NEXT: nop
; MIPS4-NEXT: sd $ra, 8($sp)
; MIPS4-NEXT: # %bb.1: # %if.end
; MIPS4-NEXT: jal f2
; MIPS4-NEXT: nop
Expand All @@ -241,11 +237,10 @@ define void @f1(float %f) nounwind {
; MIPS64-LABEL: f1:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: daddiu $sp, $sp, -16
; MIPS64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
; MIPS64-NEXT: mtc1 $zero, $f0
; MIPS64-NEXT: c.eq.s $f12, $f0
; MIPS64-NEXT: bc1f .LBB1_2
; MIPS64-NEXT: nop
; MIPS64-NEXT: sd $ra, 8($sp)
; MIPS64-NEXT: # %bb.1: # %if.end
; MIPS64-NEXT: jal f2
; MIPS64-NEXT: nop
Expand All @@ -259,11 +254,10 @@ define void @f1(float %f) nounwind {
; MIPS64R2-LABEL: f1:
; MIPS64R2: # %bb.0: # %entry
; MIPS64R2-NEXT: daddiu $sp, $sp, -16
; MIPS64R2-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
; MIPS64R2-NEXT: mtc1 $zero, $f0
; MIPS64R2-NEXT: c.eq.s $f12, $f0
; MIPS64R2-NEXT: bc1f .LBB1_2
; MIPS64R2-NEXT: nop
; MIPS64R2-NEXT: sd $ra, 8($sp)
; MIPS64R2-NEXT: # %bb.1: # %if.end
; MIPS64R2-NEXT: jal f2
; MIPS64R2-NEXT: nop
Expand All @@ -277,13 +271,12 @@ define void @f1(float %f) nounwind {
; MIPS64R6-LABEL: f1:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: daddiu $sp, $sp, -16
; MIPS64R6-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
; MIPS64R6-NEXT: mtc1 $zero, $f0
; MIPS64R6-NEXT: cmp.eq.s $f0, $f12, $f0
; MIPS64R6-NEXT: mfc1 $1, $f0
; MIPS64R6-NEXT: andi $1, $1, 1
; MIPS64R6-NEXT: beqzc $1, .LBB1_2
; MIPS64R6-NEXT: nop
; MIPS64R6-NEXT: beqz $1, .LBB1_2
; MIPS64R6-NEXT: sd $ra, 8($sp)
; MIPS64R6-NEXT: # %bb.1: # %if.end
; MIPS64R6-NEXT: jal f2
; MIPS64R6-NEXT: nop
Expand Down
15 changes: 5 additions & 10 deletions llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -7,12 +7,11 @@

# ASM: # %bb.0:
# ASM-NEXT: daddiu $sp, $sp, -16
# ASM-NEXT: sd $ra, 8($sp)
## BUNDLE should be emitted in order:
# ASM-NEXT: daddiu $sp, $sp, -16
# ASM-NEXT: daddiu $sp, $sp, 16
# ASM-NEXT: beqz $4, .LBB0_2
# ASM-NEXT: nop
# ASM-NEXT: sd $ra, 8($sp)
--- |
target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
target triple = "mips64-unknown-freebsd"
Expand Down Expand Up @@ -87,15 +86,12 @@ body: |
; CHECK: bb.0.entry:
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; CHECK: $sp_64 = DADDiu $sp_64, -16
; CHECK: CFI_INSTRUCTION def_cfa_offset 16
; CHECK: SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
; CHECK: CFI_INSTRUCTION offset $ra_64, -8
; CHECK: BUNDLE {
; CHECK: $sp_64 = DADDiu $sp_64, -16
; CHECK: $sp_64 = DADDiu $sp_64, 16
; CHECK: }
; CHECK: BEQ64 renamable $a0_64, $zero_64, %bb.2, implicit-def $at {
; CHECK: $zero = SLL $zero, 0
; CHECK: SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
; CHECK: }
; CHECK: bb.1.if.then:
; CHECK: successors: %bb.3(0x80000000)
Expand All @@ -120,15 +116,14 @@ body: |
liveins: $a0_64, $ra_64

$sp_64 = DADDiu $sp_64, -16
CFI_INSTRUCTION def_cfa_offset 16
SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
CFI_INSTRUCTION offset $ra_64, -8
; This BUNDLE instruction must not be split by the delay slot filler:
BUNDLE {
$sp_64 = DADDiu $sp_64, -16
$sp_64 = DADDiu $sp_64, 16
}
BEQ64 renamable $a0_64, $zero_64, %bb.2, implicit-def $at
BEQ64 renamable $a0_64, $zero_64, %bb.2, implicit-def $at {
SD killed $ra_64, $sp_64, 8 :: (store (s64) into %stack.0)
}

bb.1.if.then:
successors: %bb.3(0x80000000)
Expand Down
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