From c1c933fded6babbd413779a59952d4e4d8a20be3 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Tue, 22 Apr 2025 09:51:13 +0300 Subject: [PATCH 1/4] Remove TargetTransformInfo::Model --- .../llvm/Analysis/TargetTransformInfo.h | 902 +----------------- .../llvm/Analysis/TargetTransformInfoImpl.h | 2 +- llvm/lib/Analysis/TargetTransformInfo.cpp | 5 +- llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp | 2 +- .../Target/AArch64/AArch64TargetMachine.cpp | 2 +- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +- llvm/lib/Target/AMDGPU/R600TargetMachine.cpp | 2 +- llvm/lib/Target/ARC/ARCTargetMachine.cpp | 2 +- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 2 +- llvm/lib/Target/BPF/BPFTargetMachine.cpp | 2 +- .../Target/DirectX/DirectXTargetMachine.cpp | 2 +- .../Target/Hexagon/HexagonTargetMachine.cpp | 2 +- llvm/lib/Target/Lanai/LanaiTargetMachine.cpp | 2 +- .../LoongArch/LoongArchTargetMachine.cpp | 2 +- llvm/lib/Target/Mips/MipsTargetMachine.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp | 2 +- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 2 +- .../Target/PowerPC/PPCTargetTransformInfo.cpp | 6 +- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +- llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp | 2 +- .../Target/SystemZ/SystemZTargetMachine.cpp | 2 +- llvm/lib/Target/VE/VETargetMachine.cpp | 2 +- .../WebAssembly/WebAssemblyTargetMachine.cpp | 2 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 2 +- llvm/lib/Target/XCore/XCoreTargetMachine.cpp | 2 +- 25 files changed, 36 insertions(+), 921 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index ab5306b7b614e..118ecfb87ec80 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -215,6 +215,10 @@ typedef TargetTransformInfo TTI; /// for IR-level transformations. class TargetTransformInfo { public: + /// The abstract base class used to type erase specific TTI + /// implementations. + class Concept; + enum PartialReductionExtendKind { PR_None, PR_SignExtend, PR_ZeroExtend }; /// Get the kind of extension that an instruction represents. @@ -226,7 +230,7 @@ class TargetTransformInfo { /// /// This is used by targets to construct a TTI wrapping their target-specific /// implementation that encodes appropriate costs for their target. - template TargetTransformInfo(T Impl); + explicit TargetTransformInfo(std::unique_ptr Impl); /// Construct a baseline TTI object using a minimal implementation of /// the \c Concept API below. @@ -1915,14 +1919,6 @@ class TargetTransformInfo { SmallVectorImpl> &LB) const; private: - /// The abstract base class used to type erase specific TTI - /// implementations. - class Concept; - - /// The template model for the base class which wraps a concrete - /// implementation in a type erased interface. - template class Model; - std::unique_ptr TTIImpl; }; @@ -2382,894 +2378,6 @@ class TargetTransformInfo::Concept { SmallVectorImpl> &LB) const = 0; }; -template -class TargetTransformInfo::Model final : public TargetTransformInfo::Concept { - const T Impl; - -public: - Model(T Impl) : Impl(std::move(Impl)) {} - ~Model() override = default; - - const DataLayout &getDataLayout() const override { - return Impl.getDataLayout(); - } - - InstructionCost - getGEPCost(Type *PointeeType, const Value *Ptr, - ArrayRef Operands, Type *AccessType, - TargetTransformInfo::TargetCostKind CostKind) const override { - return Impl.getGEPCost(PointeeType, Ptr, Operands, AccessType, CostKind); - } - InstructionCost getPointersChainCost(ArrayRef Ptrs, - const Value *Base, - const PointersChainInfo &Info, - Type *AccessTy, - TargetCostKind CostKind) const override { - return Impl.getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind); - } - unsigned getInliningThresholdMultiplier() const override { - return Impl.getInliningThresholdMultiplier(); - } - unsigned adjustInliningThreshold(const CallBase *CB) const override { - return Impl.adjustInliningThreshold(CB); - } - unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const override { - return Impl.getInliningCostBenefitAnalysisSavingsMultiplier(); - } - unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const override { - return Impl.getInliningCostBenefitAnalysisProfitableMultiplier(); - } - int getInliningLastCallToStaticBonus() const override { - return Impl.getInliningLastCallToStaticBonus(); - } - int getInlinerVectorBonusPercent() const override { - return Impl.getInlinerVectorBonusPercent(); - } - unsigned getCallerAllocaCost(const CallBase *CB, - const AllocaInst *AI) const override { - return Impl.getCallerAllocaCost(CB, AI); - } - InstructionCost getMemcpyCost(const Instruction *I) const override { - return Impl.getMemcpyCost(I); - } - - uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override { - return Impl.getMaxMemIntrinsicInlineSizeThreshold(); - } - - InstructionCost getInstructionCost(const User *U, - ArrayRef Operands, - TargetCostKind CostKind) const override { - return Impl.getInstructionCost(U, Operands, CostKind); - } - BranchProbability getPredictableBranchThreshold() const override { - return Impl.getPredictableBranchThreshold(); - } - InstructionCost getBranchMispredictPenalty() const override { - return Impl.getBranchMispredictPenalty(); - } - bool hasBranchDivergence(const Function *F = nullptr) const override { - return Impl.hasBranchDivergence(F); - } - bool isSourceOfDivergence(const Value *V) const override { - return Impl.isSourceOfDivergence(V); - } - - bool isAlwaysUniform(const Value *V) const override { - return Impl.isAlwaysUniform(V); - } - - bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override { - return Impl.isValidAddrSpaceCast(FromAS, ToAS); - } - - bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override { - return Impl.addrspacesMayAlias(AS0, AS1); - } - - unsigned getFlatAddressSpace() const override { - return Impl.getFlatAddressSpace(); - } - - bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes, - Intrinsic::ID IID) const override { - return Impl.collectFlatAddressOperands(OpIndexes, IID); - } - - bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override { - return Impl.isNoopAddrSpaceCast(FromAS, ToAS); - } - - bool - canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override { - return Impl.canHaveNonUndefGlobalInitializerInAddressSpace(AS); - } - - unsigned getAssumedAddrSpace(const Value *V) const override { - return Impl.getAssumedAddrSpace(V); - } - - bool isSingleThreaded() const override { return Impl.isSingleThreaded(); } - - std::pair - getPredicatedAddrSpace(const Value *V) const override { - return Impl.getPredicatedAddrSpace(V); - } - - Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, - Value *NewV) const override { - return Impl.rewriteIntrinsicWithAddressSpace(II, OldV, NewV); - } - - bool isLoweredToCall(const Function *F) const override { - return Impl.isLoweredToCall(F); - } - void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, - UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const override { - return Impl.getUnrollingPreferences(L, SE, UP, ORE); - } - void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - PeelingPreferences &PP) const override { - return Impl.getPeelingPreferences(L, SE, PP); - } - bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, - AssumptionCache &AC, TargetLibraryInfo *LibInfo, - HardwareLoopInfo &HWLoopInfo) const override { - return Impl.isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo); - } - unsigned getEpilogueVectorizationMinVF() const override { - return Impl.getEpilogueVectorizationMinVF(); - } - bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const override { - return Impl.preferPredicateOverEpilogue(TFI); - } - TailFoldingStyle - getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const override { - return Impl.getPreferredTailFoldingStyle(IVUpdateMayOverflow); - } - std::optional - instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override { - return Impl.instCombineIntrinsic(IC, II); - } - std::optional - simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, - APInt DemandedMask, KnownBits &Known, - bool &KnownBitsComputed) const override { - return Impl.simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known, - KnownBitsComputed); - } - std::optional simplifyDemandedVectorEltsIntrinsic( - InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, - APInt &UndefElts2, APInt &UndefElts3, - std::function - SimplifyAndSetOp) const override { - return Impl.simplifyDemandedVectorEltsIntrinsic( - IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, - SimplifyAndSetOp); - } - bool isLegalAddImmediate(int64_t Imm) const override { - return Impl.isLegalAddImmediate(Imm); - } - bool isLegalAddScalableImmediate(int64_t Imm) const override { - return Impl.isLegalAddScalableImmediate(Imm); - } - bool isLegalICmpImmediate(int64_t Imm) const override { - return Impl.isLegalICmpImmediate(Imm); - } - bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, - bool HasBaseReg, int64_t Scale, unsigned AddrSpace, - Instruction *I, - int64_t ScalableOffset) const override { - return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, - AddrSpace, I, ScalableOffset); - } - bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, - const TargetTransformInfo::LSRCost &C2) const override { - return Impl.isLSRCostLess(C1, C2); - } - bool isNumRegsMajorCostOfLSR() const override { - return Impl.isNumRegsMajorCostOfLSR(); - } - bool shouldDropLSRSolutionIfLessProfitable() const override { - return Impl.shouldDropLSRSolutionIfLessProfitable(); - } - bool isProfitableLSRChainElement(Instruction *I) const override { - return Impl.isProfitableLSRChainElement(I); - } - bool canMacroFuseCmp() const override { return Impl.canMacroFuseCmp(); } - bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, - DominatorTree *DT, AssumptionCache *AC, - TargetLibraryInfo *LibInfo) const override { - return Impl.canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo); - } - AddressingModeKind - getPreferredAddressingMode(const Loop *L, - ScalarEvolution *SE) const override { - return Impl.getPreferredAddressingMode(L, SE); - } - bool isLegalMaskedStore(Type *DataType, Align Alignment, - unsigned AddressSpace) const override { - return Impl.isLegalMaskedStore(DataType, Alignment, AddressSpace); - } - bool isLegalMaskedLoad(Type *DataType, Align Alignment, - unsigned AddressSpace) const override { - return Impl.isLegalMaskedLoad(DataType, Alignment, AddressSpace); - } - bool isLegalNTStore(Type *DataType, Align Alignment) const override { - return Impl.isLegalNTStore(DataType, Alignment); - } - bool isLegalNTLoad(Type *DataType, Align Alignment) const override { - return Impl.isLegalNTLoad(DataType, Alignment); - } - bool isLegalBroadcastLoad(Type *ElementTy, - ElementCount NumElements) const override { - return Impl.isLegalBroadcastLoad(ElementTy, NumElements); - } - bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override { - return Impl.isLegalMaskedScatter(DataType, Alignment); - } - bool isLegalMaskedGather(Type *DataType, Align Alignment) const override { - return Impl.isLegalMaskedGather(DataType, Alignment); - } - bool forceScalarizeMaskedGather(VectorType *DataType, - Align Alignment) const override { - return Impl.forceScalarizeMaskedGather(DataType, Alignment); - } - bool forceScalarizeMaskedScatter(VectorType *DataType, - Align Alignment) const override { - return Impl.forceScalarizeMaskedScatter(DataType, Alignment); - } - bool isLegalMaskedCompressStore(Type *DataType, - Align Alignment) const override { - return Impl.isLegalMaskedCompressStore(DataType, Alignment); - } - bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const override { - return Impl.isLegalMaskedExpandLoad(DataType, Alignment); - } - bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const override { - return Impl.isLegalStridedLoadStore(DataType, Alignment); - } - bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, - Align Alignment, - unsigned AddrSpace) const override { - return Impl.isLegalInterleavedAccessType(VTy, Factor, Alignment, AddrSpace); - } - bool isLegalMaskedVectorHistogram(Type *AddrType, - Type *DataType) const override { - return Impl.isLegalMaskedVectorHistogram(AddrType, DataType); - } - bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, - const SmallBitVector &OpcodeMask) const override { - return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); - } - bool enableOrderedReductions() const override { - return Impl.enableOrderedReductions(); - } - bool hasDivRemOp(Type *DataType, bool IsSigned) const override { - return Impl.hasDivRemOp(DataType, IsSigned); - } - bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const override { - return Impl.hasVolatileVariant(I, AddrSpace); - } - bool prefersVectorizedAddressing() const override { - return Impl.prefersVectorizedAddressing(); - } - InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - StackOffset BaseOffset, bool HasBaseReg, - int64_t Scale, - unsigned AddrSpace) const override { - return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, - AddrSpace); - } - bool LSRWithInstrQueries() const override { - return Impl.LSRWithInstrQueries(); - } - bool isTruncateFree(Type *Ty1, Type *Ty2) const override { - return Impl.isTruncateFree(Ty1, Ty2); - } - bool isProfitableToHoist(Instruction *I) const override { - return Impl.isProfitableToHoist(I); - } - bool useAA() const override { return Impl.useAA(); } - bool isTypeLegal(Type *Ty) const override { return Impl.isTypeLegal(Ty); } - unsigned getRegUsageForType(Type *Ty) const override { - return Impl.getRegUsageForType(Ty); - } - bool shouldBuildLookupTables() const override { - return Impl.shouldBuildLookupTables(); - } - bool shouldBuildLookupTablesForConstant(Constant *C) const override { - return Impl.shouldBuildLookupTablesForConstant(C); - } - bool shouldBuildRelLookupTables() const override { - return Impl.shouldBuildRelLookupTables(); - } - bool useColdCCForColdCall(Function &F) const override { - return Impl.useColdCCForColdCall(F); - } - bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const override { - return Impl.isTargetIntrinsicTriviallyScalarizable(ID); - } - - bool - isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, - unsigned ScalarOpdIdx) const override { - return Impl.isTargetIntrinsicWithScalarOpAtArg(ID, ScalarOpdIdx); - } - - bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, - int OpdIdx) const override { - return Impl.isTargetIntrinsicWithOverloadTypeAtArg(ID, OpdIdx); - } - - bool - isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, - int RetIdx) const override { - return Impl.isTargetIntrinsicWithStructReturnOverloadAtField(ID, RetIdx); - } - - InstructionCost - getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, - bool Insert, bool Extract, TargetCostKind CostKind, - ArrayRef VL = {}) const override { - return Impl.getScalarizationOverhead(Ty, DemandedElts, Insert, Extract, - CostKind, VL); - } - InstructionCost - getOperandsScalarizationOverhead(ArrayRef Args, - ArrayRef Tys, - TargetCostKind CostKind) const override { - return Impl.getOperandsScalarizationOverhead(Args, Tys, CostKind); - } - - bool supportsEfficientVectorElementLoadStore() const override { - return Impl.supportsEfficientVectorElementLoadStore(); - } - - bool supportsTailCalls() const override { return Impl.supportsTailCalls(); } - bool supportsTailCallFor(const CallBase *CB) const override { - return Impl.supportsTailCallFor(CB); - } - - bool enableAggressiveInterleaving(bool LoopHasReductions) const override { - return Impl.enableAggressiveInterleaving(LoopHasReductions); - } - MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, - bool IsZeroCmp) const override { - return Impl.enableMemCmpExpansion(OptSize, IsZeroCmp); - } - bool enableSelectOptimize() const override { - return Impl.enableSelectOptimize(); - } - bool shouldTreatInstructionLikeSelect(const Instruction *I) const override { - return Impl.shouldTreatInstructionLikeSelect(I); - } - bool enableInterleavedAccessVectorization() const override { - return Impl.enableInterleavedAccessVectorization(); - } - bool enableMaskedInterleavedAccessVectorization() const override { - return Impl.enableMaskedInterleavedAccessVectorization(); - } - bool isFPVectorizationPotentiallyUnsafe() const override { - return Impl.isFPVectorizationPotentiallyUnsafe(); - } - bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, - unsigned AddressSpace, Align Alignment, - unsigned *Fast) const override { - return Impl.allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace, - Alignment, Fast); - } - PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const override { - return Impl.getPopcntSupport(IntTyWidthInBit); - } - bool haveFastSqrt(Type *Ty) const override { return Impl.haveFastSqrt(Ty); } - - bool isExpensiveToSpeculativelyExecute(const Instruction *I) const override { - return Impl.isExpensiveToSpeculativelyExecute(I); - } - - bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const override { - return Impl.isFCmpOrdCheaperThanFCmpZero(Ty); - } - - InstructionCost getFPOpCost(Type *Ty) const override { - return Impl.getFPOpCost(Ty); - } - - InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, - const APInt &Imm, - Type *Ty) const override { - return Impl.getIntImmCodeSizeCost(Opc, Idx, Imm, Ty); - } - InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TargetCostKind CostKind) const override { - return Impl.getIntImmCost(Imm, Ty, CostKind); - } - InstructionCost - getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, - TargetCostKind CostKind, - Instruction *Inst = nullptr) const override { - return Impl.getIntImmCostInst(Opc, Idx, Imm, Ty, CostKind, Inst); - } - InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, - const APInt &Imm, Type *Ty, - TargetCostKind CostKind) const override { - return Impl.getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind); - } - bool preferToKeepConstantsAttached(const Instruction &Inst, - const Function &Fn) const override { - return Impl.preferToKeepConstantsAttached(Inst, Fn); - } - unsigned getNumberOfRegisters(unsigned ClassID) const override { - return Impl.getNumberOfRegisters(ClassID); - } - bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const override { - return Impl.hasConditionalLoadStoreForType(Ty, IsStore); - } - unsigned getRegisterClassForType(bool Vector, - Type *Ty = nullptr) const override { - return Impl.getRegisterClassForType(Vector, Ty); - } - const char *getRegisterClassName(unsigned ClassID) const override { - return Impl.getRegisterClassName(ClassID); - } - TypeSize getRegisterBitWidth(RegisterKind K) const override { - return Impl.getRegisterBitWidth(K); - } - unsigned getMinVectorRegisterBitWidth() const override { - return Impl.getMinVectorRegisterBitWidth(); - } - std::optional getMaxVScale() const override { - return Impl.getMaxVScale(); - } - std::optional getVScaleForTuning() const override { - return Impl.getVScaleForTuning(); - } - bool isVScaleKnownToBeAPowerOfTwo() const override { - return Impl.isVScaleKnownToBeAPowerOfTwo(); - } - bool shouldMaximizeVectorBandwidth( - TargetTransformInfo::RegisterKind K) const override { - return Impl.shouldMaximizeVectorBandwidth(K); - } - ElementCount getMinimumVF(unsigned ElemWidth, - bool IsScalable) const override { - return Impl.getMinimumVF(ElemWidth, IsScalable); - } - unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override { - return Impl.getMaximumVF(ElemWidth, Opcode); - } - unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, - Type *ScalarValTy) const override { - return Impl.getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy); - } - bool shouldConsiderAddressTypePromotion( - const Instruction &I, - bool &AllowPromotionWithoutCommonHeader) const override { - return Impl.shouldConsiderAddressTypePromotion( - I, AllowPromotionWithoutCommonHeader); - } - unsigned getCacheLineSize() const override { return Impl.getCacheLineSize(); } - std::optional getCacheSize(CacheLevel Level) const override { - return Impl.getCacheSize(Level); - } - std::optional - getCacheAssociativity(CacheLevel Level) const override { - return Impl.getCacheAssociativity(Level); - } - - std::optional getMinPageSize() const override { - return Impl.getMinPageSize(); - } - - /// Return the preferred prefetch distance in terms of instructions. - /// - unsigned getPrefetchDistance() const override { - return Impl.getPrefetchDistance(); - } - - /// Return the minimum stride necessary to trigger software - /// prefetching. - /// - unsigned getMinPrefetchStride(unsigned NumMemAccesses, - unsigned NumStridedMemAccesses, - unsigned NumPrefetches, - bool HasCall) const override { - return Impl.getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses, - NumPrefetches, HasCall); - } - - /// Return the maximum prefetch distance in terms of loop - /// iterations. - /// - unsigned getMaxPrefetchIterationsAhead() const override { - return Impl.getMaxPrefetchIterationsAhead(); - } - - /// \return True if prefetching should also be done for writes. - bool enableWritePrefetching() const override { - return Impl.enableWritePrefetching(); - } - - /// \return if target want to issue a prefetch in address space \p AS. - bool shouldPrefetchAddressSpace(unsigned AS) const override { - return Impl.shouldPrefetchAddressSpace(AS); - } - - InstructionCost getPartialReductionCost( - unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, - ElementCount VF, PartialReductionExtendKind OpAExtend, - PartialReductionExtendKind OpBExtend, - std::optional BinOp = std::nullopt) const override { - return Impl.getPartialReductionCost(Opcode, InputTypeA, InputTypeB, - AccumType, VF, OpAExtend, OpBExtend, - BinOp); - } - - unsigned getMaxInterleaveFactor(ElementCount VF) const override { - return Impl.getMaxInterleaveFactor(VF); - } - unsigned - getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, - ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI) const override { - return Impl.getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI); - } - InstructionCost - getArithmeticInstrCost(unsigned Opcode, Type *Ty, - TTI::TargetCostKind CostKind, - OperandValueInfo Opd1Info, OperandValueInfo Opd2Info, - ArrayRef Args, - const Instruction *CxtI = nullptr) const override { - return Impl.getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info, - Args, CxtI); - } - InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, - unsigned Opcode1, - const SmallBitVector &OpcodeMask, - TTI::TargetCostKind CostKind) const override { - return Impl.getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind); - } - - InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args, - const Instruction *CxtI) const override { - return Impl.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args, - CxtI); - } - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I) const override { - return Impl.getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); - } - InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, - VectorType *VecTy, - unsigned Index) const override { - return Impl.getExtractWithExtendCost(Opcode, Dst, VecTy, Index); - } - InstructionCost - getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const override { - return Impl.getCFInstrCost(Opcode, CostKind, I); - } - InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, - CmpInst::Predicate VecPred, - TTI::TargetCostKind CostKind, - OperandValueInfo Op1Info, - OperandValueInfo Op2Info, - const Instruction *I) const override { - return Impl.getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, - Op1Info, Op2Info, I); - } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - TTI::TargetCostKind CostKind, - unsigned Index, Value *Op0, - Value *Op1) const override { - return Impl.getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1); - } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - TTI::TargetCostKind CostKind, - unsigned Index, Value *Scalar, - ArrayRef> - ScalarUserAndIdx) const override { - return Impl.getVectorInstrCost(Opcode, Val, CostKind, Index, Scalar, - ScalarUserAndIdx); - } - InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, - TTI::TargetCostKind CostKind, - unsigned Index) const override { - return Impl.getVectorInstrCost(I, Val, CostKind, Index); - } - InstructionCost - getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, - const APInt &DemandedDstElts, - TTI::TargetCostKind CostKind) const override { - return Impl.getReplicationShuffleCost(EltTy, ReplicationFactor, VF, - DemandedDstElts, CostKind); - } - InstructionCost - getInsertExtractValueCost(unsigned Opcode, - TTI::TargetCostKind CostKind) const override { - return Impl.getInsertExtractValueCost(Opcode, CostKind); - } - InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, - unsigned AddressSpace, - TTI::TargetCostKind CostKind, - OperandValueInfo OpInfo, - const Instruction *I) const override { - return Impl.getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind, - OpInfo, I); - } - InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, - unsigned AddressSpace, - TTI::TargetCostKind CostKind, - const Instruction *I) const override { - return Impl.getVPMemoryOpCost(Opcode, Src, Alignment, AddressSpace, - CostKind, I); - } - InstructionCost - getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, - unsigned AddressSpace, - TTI::TargetCostKind CostKind) const override { - return Impl.getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, - CostKind); - } - InstructionCost - getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, - bool VariableMask, Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const override { - return Impl.getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, - Alignment, CostKind, I); - } - InstructionCost - getExpandCompressMemoryOpCost(unsigned Opcode, Type *DataTy, - bool VariableMask, Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const override { - return Impl.getExpandCompressMemoryOpCost(Opcode, DataTy, VariableMask, - Alignment, CostKind, I); - } - InstructionCost - getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, - bool VariableMask, Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const override { - return Impl.getStridedMemoryOpCost(Opcode, DataTy, Ptr, VariableMask, - Alignment, CostKind, I); - } - InstructionCost getInterleavedMemoryOpCost( - unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, - Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond, bool UseMaskForGaps) const override { - return Impl.getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, - Alignment, AddressSpace, CostKind, - UseMaskForCond, UseMaskForGaps); - } - InstructionCost - getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, - std::optional FMF, - TTI::TargetCostKind CostKind) const override { - return Impl.getArithmeticReductionCost(Opcode, Ty, FMF, CostKind); - } - InstructionCost - getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, - TTI::TargetCostKind CostKind) const override { - return Impl.getMinMaxReductionCost(IID, Ty, FMF, CostKind); - } - InstructionCost - getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, - VectorType *Ty, std::optional FMF, - TTI::TargetCostKind CostKind) const override { - return Impl.getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF, - CostKind); - } - InstructionCost - getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, - TTI::TargetCostKind CostKind) const override { - return Impl.getMulAccReductionCost(IsUnsigned, ResTy, Ty, CostKind); - } - InstructionCost - getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const override { - return Impl.getIntrinsicInstrCost(ICA, CostKind); - } - InstructionCost - getCallInstrCost(Function *F, Type *RetTy, ArrayRef Tys, - TTI::TargetCostKind CostKind) const override { - return Impl.getCallInstrCost(F, RetTy, Tys, CostKind); - } - unsigned getNumberOfParts(Type *Tp) const override { - return Impl.getNumberOfParts(Tp); - } - InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE, - const SCEV *Ptr) const override { - return Impl.getAddressComputationCost(Ty, SE, Ptr); - } - InstructionCost - getCostOfKeepingLiveOverCall(ArrayRef Tys) const override { - return Impl.getCostOfKeepingLiveOverCall(Tys); - } - bool getTgtMemIntrinsic(IntrinsicInst *Inst, - MemIntrinsicInfo &Info) const override { - return Impl.getTgtMemIntrinsic(Inst, Info); - } - unsigned getAtomicMemIntrinsicMaxElementSize() const override { - return Impl.getAtomicMemIntrinsicMaxElementSize(); - } - Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, - Type *ExpectedType) const override { - return Impl.getOrCreateResultFromMemIntrinsic(Inst, ExpectedType); - } - Type *getMemcpyLoopLoweringType( - LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, - unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, - std::optional AtomicElementSize) const override { - return Impl.getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace, - DestAddrSpace, SrcAlign, DestAlign, - AtomicElementSize); - } - void getMemcpyLoopResidualLoweringType( - SmallVectorImpl &OpsOut, LLVMContext &Context, - unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, - Align SrcAlign, Align DestAlign, - std::optional AtomicCpySize) const override { - Impl.getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes, - SrcAddrSpace, DestAddrSpace, - SrcAlign, DestAlign, AtomicCpySize); - } - bool areInlineCompatible(const Function *Caller, - const Function *Callee) const override { - return Impl.areInlineCompatible(Caller, Callee); - } - unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, - unsigned DefaultCallPenalty) const override { - return Impl.getInlineCallPenalty(F, Call, DefaultCallPenalty); - } - bool areTypesABICompatible(const Function *Caller, const Function *Callee, - const ArrayRef &Types) const override { - return Impl.areTypesABICompatible(Caller, Callee, Types); - } - bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const override { - return Impl.isIndexedLoadLegal(Mode, Ty); - } - bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const override { - return Impl.isIndexedStoreLegal(Mode, Ty); - } - unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override { - return Impl.getLoadStoreVecRegBitWidth(AddrSpace); - } - bool isLegalToVectorizeLoad(LoadInst *LI) const override { - return Impl.isLegalToVectorizeLoad(LI); - } - bool isLegalToVectorizeStore(StoreInst *SI) const override { - return Impl.isLegalToVectorizeStore(SI); - } - bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const override { - return Impl.isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, - AddrSpace); - } - bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const override { - return Impl.isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment, - AddrSpace); - } - bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, - ElementCount VF) const override { - return Impl.isLegalToVectorizeReduction(RdxDesc, VF); - } - bool isElementTypeLegalForScalableVector(Type *Ty) const override { - return Impl.isElementTypeLegalForScalableVector(Ty); - } - unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, - unsigned ChainSizeInBytes, - VectorType *VecTy) const override { - return Impl.getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy); - } - unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, - unsigned ChainSizeInBytes, - VectorType *VecTy) const override { - return Impl.getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy); - } - bool preferFixedOverScalableIfEqualCost() const override { - return Impl.preferFixedOverScalableIfEqualCost(); - } - bool preferInLoopReduction(RecurKind Kind, Type *Ty) const override { - return Impl.preferInLoopReduction(Kind, Ty); - } - bool preferAlternateOpcodeVectorization() const override { - return Impl.preferAlternateOpcodeVectorization(); - } - bool preferPredicatedReductionSelect(unsigned Opcode, - Type *Ty) const override { - return Impl.preferPredicatedReductionSelect(Opcode, Ty); - } - bool preferEpilogueVectorization() const override { - return Impl.preferEpilogueVectorization(); - } - - bool shouldExpandReduction(const IntrinsicInst *II) const override { - return Impl.shouldExpandReduction(II); - } - - ReductionShuffle - getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const override { - return Impl.getPreferredExpandedReductionShuffle(II); - } - - unsigned getGISelRematGlobalCost() const override { - return Impl.getGISelRematGlobalCost(); - } - - unsigned getMinTripCountTailFoldingThreshold() const override { - return Impl.getMinTripCountTailFoldingThreshold(); - } - - bool supportsScalableVectors() const override { - return Impl.supportsScalableVectors(); - } - - bool enableScalableVectorization() const override { - return Impl.enableScalableVectorization(); - } - - bool hasActiveVectorLength(unsigned Opcode, Type *DataType, - Align Alignment) const override { - return Impl.hasActiveVectorLength(Opcode, DataType, Alignment); - } - - bool isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &Ops) const override { - return Impl.isProfitableToSinkOperands(I, Ops); - }; - - bool isVectorShiftByScalarCheap(Type *Ty) const override { - return Impl.isVectorShiftByScalarCheap(Ty); - } - - VPLegalization - getVPLegalizationStrategy(const VPIntrinsic &PI) const override { - return Impl.getVPLegalizationStrategy(PI); - } - - bool hasArmWideBranch(bool Thumb) const override { - return Impl.hasArmWideBranch(Thumb); - } - - uint64_t getFeatureMask(const Function &F) const override { - return Impl.getFeatureMask(F); - } - - bool isMultiversionedFunction(const Function &F) const override { - return Impl.isMultiversionedFunction(F); - } - - unsigned getMaxNumArgs() const override { - return Impl.getMaxNumArgs(); - } - - unsigned getNumBytesToPadGlobalArray(unsigned Size, - Type *ArrayType) const override { - return Impl.getNumBytesToPadGlobalArray(Size, ArrayType); - } - - void collectKernelLaunchBounds( - const Function &F, - SmallVectorImpl> &LB) const override { - Impl.collectKernelLaunchBounds(F, LB); - } -}; - -template -TargetTransformInfo::TargetTransformInfo(T Impl) - : TTIImpl(new Model(Impl)) {} - /// Analysis pass providing the \c TargetTransformInfo. /// /// The core idea of the TargetIRAnalysis is to expose an interface through diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index b46eb349c2249..e2fb01e65694a 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -31,7 +31,7 @@ class Function; /// Base class for use as a mix-in that aids implementing /// a TargetTransformInfo-compatible class. -class TargetTransformInfoImplBase { +class TargetTransformInfoImplBase : public TTI::Concept { protected: typedef TargetTransformInfo TTI; diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 3f97484fb2fa3..f5426cae42228 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -57,6 +57,9 @@ struct NoTTIImpl : TargetTransformInfoImplCRTPBase { }; } // namespace +TargetTransformInfo::TargetTransformInfo(std::unique_ptr Impl) + : TTIImpl(std::move(Impl)) {} + bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) { // If the loop has irreducible control flow, it can not be converted to // Hardware loop. @@ -199,7 +202,7 @@ bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE, } TargetTransformInfo::TargetTransformInfo(const DataLayout &DL) - : TTIImpl(new Model(NoTTIImpl(DL))) {} + : TTIImpl(std::make_unique(DL)) {} TargetTransformInfo::~TargetTransformInfo() = default; diff --git a/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp b/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp index dcadee6812bdb..4a3503a2da7db 100644 --- a/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp +++ b/llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp @@ -103,7 +103,7 @@ CodeGenTargetMachineImpl::CodeGenTargetMachineImpl( TargetTransformInfo CodeGenTargetMachineImpl::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(BasicTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } /// addPassesToX helper drives creation and initialization of TargetPassConfig. diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 6d8d9a703df62..431076f188d98 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -582,7 +582,7 @@ void AArch64TargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { TargetTransformInfo AArch64TargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(AArch64TTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index b6cc5137d711a..eb50617b281a1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -1070,7 +1070,7 @@ GCNTargetMachine::getSubtargetImpl(const Function &F) const { TargetTransformInfo GCNTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(GCNTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } Error GCNTargetMachine::buildCodeGenPipeline( diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp index 10552a1f0b1bc..2a3b42e9453bd 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp @@ -87,7 +87,7 @@ R600TargetMachine::getSubtargetImpl(const Function &F) const { TargetTransformInfo R600TargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(R600TTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } ScheduleDAGInstrs * diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp index 57e0177cd3748..f781fa9d7b57e 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -103,5 +103,5 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() { TargetTransformInfo ARCTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(ARCTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index a0d56704305a3..2f9720ee23568 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -322,7 +322,7 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { TargetTransformInfo ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(ARMTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } ScheduleDAGInstrs * diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 4c4e6e27b9a5e..873719e6983ae 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -154,7 +154,7 @@ void BPFPassConfig::addIRPasses() { TargetTransformInfo BPFTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(BPFTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } // Install an instruction selector pass using diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp index 41f6f37a41f9d..9372678f84692 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp +++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp @@ -187,7 +187,7 @@ DirectXTargetMachine::getSubtargetImpl(const Function &) const { TargetTransformInfo DirectXTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(DirectXTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } DirectXTargetLowering::DirectXTargetLowering(const DirectXTargetMachine &TM, diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index eb67d2c94b5f0..aa3491b1138f0 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -286,7 +286,7 @@ void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { TargetTransformInfo HexagonTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(HexagonTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo( diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp index f5e83286b7052..e7286527a1c35 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -67,7 +67,7 @@ LanaiTargetMachine::LanaiTargetMachine( TargetTransformInfo LanaiTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(LanaiTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } MachineFunctionInfo *LanaiTargetMachine::createMachineFunctionInfo( diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp index dc490e8185504..0c8cb14f1ad30 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp @@ -196,7 +196,7 @@ bool LoongArchPassConfig::addInstSelector() { TargetTransformInfo LoongArchTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(LoongArchTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } void LoongArchPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); } diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 4d1bcb17e2fb5..9c6cccb987230 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -298,7 +298,7 @@ MipsTargetMachine::getTargetTransformInfo(const Function &F) const { } LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n"); - return TargetTransformInfo(MipsTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } MachineFunctionInfo *MipsTargetMachine::createMachineFunctionInfo( diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index a4c3b43aec9f2..4186e7fbfb4a7 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -266,7 +266,7 @@ void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { TargetTransformInfo NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(NVPTXTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } std::pair diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 2107153962f5c..71b874ac81527 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -604,7 +604,7 @@ void PPCPassConfig::addPreEmitPass2() { TargetTransformInfo PPCTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(PPCTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } bool PPCTargetMachine::isLittleEndian() const { diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index eb487bdaa88b9..c496f4326d0f1 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -344,6 +344,10 @@ bool PPCTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, TargetSchedModel SchedModel; SchedModel.init(ST); + // FIXME: Sure there is no other way to get TTI? This should be cheap though. + TargetTransformInfo TTI = + TM.getTargetTransformInfo(*L->getHeader()->getParent()); + // Do not convert small short loops to CTR loop. unsigned ConstTripCount = SE.getSmallConstantTripCount(L); if (ConstTripCount && ConstTripCount < SmallCTRLoopThreshold) { @@ -351,7 +355,7 @@ bool PPCTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, CodeMetrics::collectEphemeralValues(L, &AC, EphValues); CodeMetrics Metrics; for (BasicBlock *BB : L->blocks()) - Metrics.analyzeBasicBlock(BB, *this, EphValues); + Metrics.analyzeBasicBlock(BB, TTI, EphValues); // 6 is an approximate latency for the mtctr instruction. if (Metrics.NumInsts <= (6 * SchedModel.getIssueWidth())) return false; diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 7fb64be3975d5..315b504399a45 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -281,7 +281,7 @@ MachineFunctionInfo *RISCVTargetMachine::createMachineFunctionInfo( TargetTransformInfo RISCVTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(RISCVTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index 68286737b972f..2127148a0ef18 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -179,7 +179,7 @@ void SPIRVPassConfig::addPostRegAlloc() { TargetTransformInfo SPIRVTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(SPIRVTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } TargetPassConfig *SPIRVTargetMachine::createPassConfig(PassManagerBase &PM) { diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index 6300fb72990d0..f8b0fdcf8fd18 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -332,7 +332,7 @@ TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) { TargetTransformInfo SystemZTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(SystemZTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } MachineFunctionInfo *SystemZTargetMachine::createMachineFunctionInfo( diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp index 3a6f73cc697e6..a7ee4ffe0d5c3 100644 --- a/llvm/lib/Target/VE/VETargetMachine.cpp +++ b/llvm/lib/Target/VE/VETargetMachine.cpp @@ -101,7 +101,7 @@ VETargetMachine::~VETargetMachine() = default; TargetTransformInfo VETargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(VETTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } MachineFunctionInfo *VETargetMachine::createMachineFunctionInfo( diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index ba8c479a658fc..873d2c59dc18c 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -385,7 +385,7 @@ MachineFunctionInfo *WebAssemblyTargetMachine::createMachineFunctionInfo( TargetTransformInfo WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } TargetPassConfig * diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 4cecbbf27aa30..5301b397e2d39 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -394,7 +394,7 @@ X86TargetMachine::createPostMachineScheduler(MachineSchedContext *C) const { TargetTransformInfo X86TargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(X86TTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index fc93ab5c500e0..4672174f5aa95 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -111,7 +111,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() { TargetTransformInfo XCoreTargetMachine::getTargetTransformInfo(const Function &F) const { - return TargetTransformInfo(XCoreTTIImpl(this, F)); + return TargetTransformInfo(std::make_unique(this, F)); } MachineFunctionInfo *XCoreTargetMachine::createMachineFunctionInfo( From 8e138efb4bb3bbb6bc9152ce9b381e7552957d5c Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Tue, 22 Apr 2025 12:34:18 +0300 Subject: [PATCH 2/4] override everything --- .../llvm/Analysis/TargetTransformInfoImpl.h | 596 ++++++++++-------- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 288 +++++---- .../AArch64/AArch64TargetTransformInfo.h | 229 +++---- .../Target/AMDGPU/AMDGPUTargetTransformInfo.h | 123 ++-- .../Target/AMDGPU/R600TargetTransformInfo.h | 23 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 162 ++--- llvm/lib/Target/BPF/BPFTargetTransformInfo.h | 15 +- .../DirectX/DirectXTargetTransformInfo.h | 8 +- .../Hexagon/HexagonTargetTransformInfo.h | 102 +-- .../Target/Lanai/LanaiTargetTransformInfo.h | 22 +- .../LoongArch/LoongArchTargetTransformInfo.h | 14 +- .../lib/Target/Mips/MipsTargetTransformInfo.h | 4 +- .../Target/NVPTX/NVPTXTargetTransformInfo.h | 60 +- .../Target/PowerPC/PPCTargetTransformInfo.h | 113 ++-- .../Target/RISCV/RISCVTargetTransformInfo.h | 195 +++--- .../Target/SPIRV/SPIRVTargetTransformInfo.h | 2 +- .../SystemZ/SystemZTargetTransformInfo.h | 89 ++- llvm/lib/Target/VE/VETargetTransformInfo.h | 21 +- .../WebAssemblyTargetTransformInfo.h | 42 +- llvm/lib/Target/X86/X86TargetTransformInfo.h | 184 +++--- .../Target/XCore/XCoreTargetTransformInfo.h | 2 +- 21 files changed, 1204 insertions(+), 1090 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index e2fb01e65694a..7cf5fc377bfd5 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -45,13 +45,13 @@ class TargetTransformInfoImplBase : public TTI::Concept { TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg) = default; TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg) : DL(Arg.DL) {} - const DataLayout &getDataLayout() const { return DL; } + const DataLayout &getDataLayout() const override { return DL; } // FIXME: It looks like this implementation is dead. All clients appear to // use the (non-const) version from `TargetTransformInfoImplCRTPBase`. InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef Operands, Type *AccessType, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { // In the basic model, we just assume that all-constant GEPs will be folded // into their uses via addressing modes. for (const Value *Operand : Operands) @@ -61,40 +61,43 @@ class TargetTransformInfoImplBase : public TTI::Concept { return TTI::TCC_Free; } - unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, - unsigned &JTSize, - ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI) const { + unsigned + getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, + ProfileSummaryInfo *PSI, + BlockFrequencyInfo *BFI) const override { (void)PSI; (void)BFI; JTSize = 0; return SI.getNumCases(); } - unsigned getInliningThresholdMultiplier() const { return 1; } - unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const { return 8; } - unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const { + unsigned getInliningThresholdMultiplier() const override { return 1; } + unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const override { return 8; } - int getInliningLastCallToStaticBonus() const { + unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const override { + return 8; + } + int getInliningLastCallToStaticBonus() const override { // This is the value of InlineConstants::LastCallToStaticBonus before it was // removed along with the introduction of this function. return 15000; } - unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; } - unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const { + unsigned adjustInliningThreshold(const CallBase *CB) const override { + return 0; + } + unsigned getCallerAllocaCost(const CallBase *CB, + const AllocaInst *AI) const override { return 0; }; - int getInlinerVectorBonusPercent() const { return 150; } + int getInlinerVectorBonusPercent() const override { return 150; } - InstructionCost getMemcpyCost(const Instruction *I) const { + InstructionCost getMemcpyCost(const Instruction *I) const override { return TTI::TCC_Expensive; } - uint64_t getMaxMemIntrinsicInlineSizeThreshold() const { - return 64; - } + uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override { return 64; } // Although this default value is arbitrary, it is not random. It is assumed // that a condition that evaluates the same way by a higher percentage than @@ -102,53 +105,56 @@ class TargetTransformInfoImplBase : public TTI::Concept { // should be set such that the win from N% correct executions is greater than // the loss from (100 - N)% mispredicted executions for the majority of // intended targets. - BranchProbability getPredictableBranchThreshold() const { + BranchProbability getPredictableBranchThreshold() const override { return BranchProbability(99, 100); } - InstructionCost getBranchMispredictPenalty() const { return 0; } + InstructionCost getBranchMispredictPenalty() const override { return 0; } - bool hasBranchDivergence(const Function *F = nullptr) const { return false; } + bool hasBranchDivergence(const Function *F = nullptr) const override { + return false; + } - bool isSourceOfDivergence(const Value *V) const { return false; } + bool isSourceOfDivergence(const Value *V) const override { return false; } - bool isAlwaysUniform(const Value *V) const { return false; } + bool isAlwaysUniform(const Value *V) const override { return false; } - bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const { + bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override { return false; } - bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const { + bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override { return true; } - unsigned getFlatAddressSpace() const { return -1; } + unsigned getFlatAddressSpace() const override { return -1; } bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes, - Intrinsic::ID IID) const { + Intrinsic::ID IID) const override { return false; } - bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; } - bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const { + bool isNoopAddrSpaceCast(unsigned, unsigned) const override { return false; } + bool + canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override { return AS == 0; }; - unsigned getAssumedAddrSpace(const Value *V) const { return -1; } + unsigned getAssumedAddrSpace(const Value *V) const override { return -1; } - bool isSingleThreaded() const { return false; } + bool isSingleThreaded() const override { return false; } std::pair - getPredicatedAddrSpace(const Value *V) const { + getPredicatedAddrSpace(const Value *V) const override { return std::make_pair(nullptr, -1); } Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, - Value *NewV) const { + Value *NewV) const override { return nullptr; } - bool isLoweredToCall(const Function *F) const { + bool isLoweredToCall(const Function *F) const override { assert(F && "A concrete function must be provided to this routine."); // FIXME: These should almost certainly not be handled here, and instead @@ -197,28 +203,30 @@ class TargetTransformInfoImplBase : public TTI::Concept { bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, - HardwareLoopInfo &HWLoopInfo) const { + HardwareLoopInfo &HWLoopInfo) const override { return false; } - unsigned getEpilogueVectorizationMinVF() const { return 16; } + unsigned getEpilogueVectorizationMinVF() const override { return 16; } - bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const { return false; } + bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const override { + return false; + } TailFoldingStyle - getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const { + getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const override { return TailFoldingStyle::DataWithoutLaneMask; } - std::optional instCombineIntrinsic(InstCombiner &IC, - IntrinsicInst &II) const { + std::optional + instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override { return std::nullopt; } std::optional simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, - bool &KnownBitsComputed) const { + bool &KnownBitsComputed) const override { return std::nullopt; } @@ -226,143 +234,154 @@ class TargetTransformInfoImplBase : public TTI::Concept { InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function - SimplifyAndSetOp) const { + SimplifyAndSetOp) const override { return std::nullopt; } void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, - OptimizationRemarkEmitter *) const {} + OptimizationRemarkEmitter *) const override {} void getPeelingPreferences(Loop *, ScalarEvolution &, - TTI::PeelingPreferences &) const {} + TTI::PeelingPreferences &) const override {} - bool isLegalAddImmediate(int64_t Imm) const { return false; } + bool isLegalAddImmediate(int64_t Imm) const override { return false; } - bool isLegalAddScalableImmediate(int64_t Imm) const { return false; } + bool isLegalAddScalableImmediate(int64_t Imm) const override { return false; } - bool isLegalICmpImmediate(int64_t Imm) const { return false; } + bool isLegalICmpImmediate(int64_t Imm) const override { return false; } bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I = nullptr, - int64_t ScalableOffset = 0) const { + int64_t ScalableOffset = 0) const override { // Guess that only reg and reg+reg addressing is allowed. This heuristic is // taken from the implementation of LSR. return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1); } - bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const { + bool isLSRCostLess(const TTI::LSRCost &C1, + const TTI::LSRCost &C2) const override { return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) < std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost); } - bool isNumRegsMajorCostOfLSR() const { return true; } + bool isNumRegsMajorCostOfLSR() const override { return true; } - bool shouldDropLSRSolutionIfLessProfitable() const { return false; } + bool shouldDropLSRSolutionIfLessProfitable() const override { return false; } - bool isProfitableLSRChainElement(Instruction *I) const { return false; } + bool isProfitableLSRChainElement(Instruction *I) const override { + return false; + } - bool canMacroFuseCmp() const { return false; } + bool canMacroFuseCmp() const override { return false; } bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, - TargetLibraryInfo *LibInfo) const { + TargetLibraryInfo *LibInfo) const override { return false; } TTI::AddressingModeKind - getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const { + getPreferredAddressingMode(const Loop *L, + ScalarEvolution *SE) const override { return TTI::AMK_None; } bool isLegalMaskedStore(Type *DataType, Align Alignment, - unsigned AddressSpace) const { + unsigned AddressSpace) const override { return false; } bool isLegalMaskedLoad(Type *DataType, Align Alignment, - unsigned AddressSpace) const { + unsigned AddressSpace) const override { return false; } - bool isLegalNTStore(Type *DataType, Align Alignment) const { + bool isLegalNTStore(Type *DataType, Align Alignment) const override { // By default, assume nontemporal memory stores are available for stores // that are aligned and have a size that is a power of 2. unsigned DataSize = DL.getTypeStoreSize(DataType); return Alignment >= DataSize && isPowerOf2_32(DataSize); } - bool isLegalNTLoad(Type *DataType, Align Alignment) const { + bool isLegalNTLoad(Type *DataType, Align Alignment) const override { // By default, assume nontemporal memory loads are available for loads that // are aligned and have a size that is a power of 2. unsigned DataSize = DL.getTypeStoreSize(DataType); return Alignment >= DataSize && isPowerOf2_32(DataSize); } - bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const { + bool isLegalBroadcastLoad(Type *ElementTy, + ElementCount NumElements) const override { return false; } - bool isLegalMaskedScatter(Type *DataType, Align Alignment) const { + bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override { return false; } - bool isLegalMaskedGather(Type *DataType, Align Alignment) const { + bool isLegalMaskedGather(Type *DataType, Align Alignment) const override { return false; } - bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const { + bool forceScalarizeMaskedGather(VectorType *DataType, + Align Alignment) const override { return false; } bool forceScalarizeMaskedScatter(VectorType *DataType, - Align Alignment) const { + Align Alignment) const override { return false; } - bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const { + bool isLegalMaskedCompressStore(Type *DataType, + Align Alignment) const override { return false; } bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, - const SmallBitVector &OpcodeMask) const { + const SmallBitVector &OpcodeMask) const override { return false; } - bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const { + bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const override { return false; } - bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const { + bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const override { return false; } bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, - Align Alignment, unsigned AddrSpace) const { + Align Alignment, + unsigned AddrSpace) const override { return false; } - bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const { + bool isLegalMaskedVectorHistogram(Type *AddrType, + Type *DataType) const override { return false; } - bool enableOrderedReductions() const { return false; } + bool enableOrderedReductions() const override { return false; } - bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; } + bool hasDivRemOp(Type *DataType, bool IsSigned) const override { + return false; + } - bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const { + bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const override { return false; } - bool prefersVectorizedAddressing() const { return true; } + bool prefersVectorizedAddressing() const override { return true; } InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, - unsigned AddrSpace) const { + unsigned AddrSpace) const override { // Guess that all legal addressing mode are free. if (isLegalAddressingMode(Ty, BaseGV, BaseOffset.getFixed(), HasBaseReg, Scale, AddrSpace, /*I=*/nullptr, @@ -371,76 +390,79 @@ class TargetTransformInfoImplBase : public TTI::Concept { return InstructionCost::getInvalid(); } - bool LSRWithInstrQueries() const { return false; } + bool LSRWithInstrQueries() const override { return false; } - bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; } + bool isTruncateFree(Type *Ty1, Type *Ty2) const override { return false; } - bool isProfitableToHoist(Instruction *I) const { return true; } + bool isProfitableToHoist(Instruction *I) const override { return true; } - bool useAA() const { return false; } + bool useAA() const override { return false; } - bool isTypeLegal(Type *Ty) const { return false; } + bool isTypeLegal(Type *Ty) const override { return false; } - unsigned getRegUsageForType(Type *Ty) const { return 1; } + unsigned getRegUsageForType(Type *Ty) const override { return 1; } - bool shouldBuildLookupTables() const { return true; } + bool shouldBuildLookupTables() const override { return true; } - bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; } + bool shouldBuildLookupTablesForConstant(Constant *C) const override { + return true; + } - bool shouldBuildRelLookupTables() const { return false; } + bool shouldBuildRelLookupTables() const override { return false; } - bool useColdCCForColdCall(Function &F) const { return false; } + bool useColdCCForColdCall(Function &F) const override { return false; } - bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const { + bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const override { return false; } - bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, - unsigned ScalarOpdIdx) const { + bool + isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, + unsigned ScalarOpdIdx) const override { return false; } bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, - int OpdIdx) const { + int OpdIdx) const override { return OpdIdx == -1; } - bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, - int RetIdx) const { + bool + isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, + int RetIdx) const override { return RetIdx == 0; } - InstructionCost getScalarizationOverhead(VectorType *Ty, - const APInt &DemandedElts, - bool Insert, bool Extract, - TTI::TargetCostKind CostKind, - ArrayRef VL = {}) const { + InstructionCost getScalarizationOverhead( + VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, + TTI::TargetCostKind CostKind, ArrayRef VL = {}) const override { return 0; } - InstructionCost - getOperandsScalarizationOverhead(ArrayRef Args, - ArrayRef Tys, - TTI::TargetCostKind CostKind) const { + InstructionCost getOperandsScalarizationOverhead( + ArrayRef Args, ArrayRef Tys, + TTI::TargetCostKind CostKind) const override { return 0; } - bool supportsEfficientVectorElementLoadStore() const { return false; } + bool supportsEfficientVectorElementLoadStore() const override { + return false; + } - bool supportsTailCalls() const { return true; } + bool supportsTailCalls() const override { return true; } - bool enableAggressiveInterleaving(bool LoopHasReductions) const { + bool enableAggressiveInterleaving(bool LoopHasReductions) const override { return false; } - TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, - bool IsZeroCmp) const { + TTI::MemCmpExpansionOptions + enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override { return {}; } - bool enableSelectOptimize() const { return true; } + bool enableSelectOptimize() const override { return true; } - bool shouldTreatInstructionLikeSelect(const Instruction *I) const { + bool shouldTreatInstructionLikeSelect(const Instruction *I) const override { // A select with two constant operands will usually be better left as a // select. using namespace llvm::PatternMatch; @@ -453,72 +475,77 @@ class TargetTransformInfoImplBase : public TTI::Concept { m_LogicalOr(m_Value(), m_Value()))); } - bool enableInterleavedAccessVectorization() const { return false; } + bool enableInterleavedAccessVectorization() const override { return false; } - bool enableMaskedInterleavedAccessVectorization() const { return false; } + bool enableMaskedInterleavedAccessVectorization() const override { + return false; + } - bool isFPVectorizationPotentiallyUnsafe() const { return false; } + bool isFPVectorizationPotentiallyUnsafe() const override { return false; } bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, - unsigned *Fast) const { + unsigned *Fast) const override { return false; } - TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const { + TTI::PopcntSupportKind + getPopcntSupport(unsigned IntTyWidthInBit) const override { return TTI::PSK_Software; } - bool haveFastSqrt(Type *Ty) const { return false; } + bool haveFastSqrt(Type *Ty) const override { return false; } - bool isExpensiveToSpeculativelyExecute(const Instruction *I) const { + bool isExpensiveToSpeculativelyExecute(const Instruction *I) const override { return true; } - bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; } + bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const override { return true; } - InstructionCost getFPOpCost(Type *Ty) const { + InstructionCost getFPOpCost(Type *Ty) const override { return TargetTransformInfo::TCC_Basic; } InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, - const APInt &Imm, Type *Ty) const { + const APInt &Imm, + Type *Ty) const override { return 0; } InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { return TTI::TCC_Basic; } - InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, - const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind, - Instruction *Inst = nullptr) const { + InstructionCost + getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, + TTI::TargetCostKind CostKind, + Instruction *Inst = nullptr) const override { return TTI::TCC_Free; } - InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, - const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const { + InstructionCost + getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty, TTI::TargetCostKind CostKind) const override { return TTI::TCC_Free; } bool preferToKeepConstantsAttached(const Instruction &Inst, - const Function &Fn) const { + const Function &Fn) const override { return false; } - unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; } - bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const { + unsigned getNumberOfRegisters(unsigned ClassID) const override { return 8; } + bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const override { return false; } - unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const { + unsigned getRegisterClassForType(bool Vector, + Type *Ty = nullptr) const override { return Vector ? 1 : 0; } - const char *getRegisterClassName(unsigned ClassID) const { + const char *getRegisterClassName(unsigned ClassID) const override { switch (ClassID) { default: return "Generic::Unknown Register Class"; @@ -529,37 +556,46 @@ class TargetTransformInfoImplBase : public TTI::Concept { } } - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override { return TypeSize::getFixed(32); } - unsigned getMinVectorRegisterBitWidth() const { return 128; } + unsigned getMinVectorRegisterBitWidth() const override { return 128; } - std::optional getMaxVScale() const { return std::nullopt; } - std::optional getVScaleForTuning() const { return std::nullopt; } - bool isVScaleKnownToBeAPowerOfTwo() const { return false; } + std::optional getMaxVScale() const override { return std::nullopt; } + std::optional getVScaleForTuning() const override { + return std::nullopt; + } + bool isVScaleKnownToBeAPowerOfTwo() const override { return false; } - bool - shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const { + bool shouldMaximizeVectorBandwidth( + TargetTransformInfo::RegisterKind K) const override { return false; } - ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const { + ElementCount getMinimumVF(unsigned ElemWidth, + bool IsScalable) const override { return ElementCount::get(0, IsScalable); } - unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; } - unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const { return VF; } + unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override { + return 0; + } + unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const override { + return VF; + } bool shouldConsiderAddressTypePromotion( - const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const { + const Instruction &I, + bool &AllowPromotionWithoutCommonHeader) const override { AllowPromotionWithoutCommonHeader = false; return false; } - unsigned getCacheLineSize() const { return 0; } + unsigned getCacheLineSize() const override { return 0; } std::optional - getCacheSize(TargetTransformInfo::CacheLevel Level) const { + getCacheSize(TargetTransformInfo::CacheLevel Level) const override { switch (Level) { case TargetTransformInfo::CacheLevel::L1D: [[fallthrough]]; @@ -570,7 +606,7 @@ class TargetTransformInfoImplBase : public TTI::Concept { } std::optional - getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const { + getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const override { switch (Level) { case TargetTransformInfo::CacheLevel::L1D: [[fallthrough]]; @@ -581,34 +617,34 @@ class TargetTransformInfoImplBase : public TTI::Concept { llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); } - std::optional getMinPageSize() const { return {}; } + std::optional getMinPageSize() const override { return {}; } - unsigned getPrefetchDistance() const { return 0; } + unsigned getPrefetchDistance() const override { return 0; } unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, - unsigned NumPrefetches, bool HasCall) const { + unsigned NumPrefetches, + bool HasCall) const override { return 1; } - unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; } - bool enableWritePrefetching() const { return false; } - bool shouldPrefetchAddressSpace(unsigned AS) const { return !AS; } + unsigned getMaxPrefetchIterationsAhead() const override { return UINT_MAX; } + bool enableWritePrefetching() const override { return false; } + bool shouldPrefetchAddressSpace(unsigned AS) const override { return !AS; } - InstructionCost - getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, - Type *AccumType, ElementCount VF, - TTI::PartialReductionExtendKind OpAExtend, - TTI::PartialReductionExtendKind OpBExtend, - std::optional BinOp = std::nullopt) const { + InstructionCost getPartialReductionCost( + unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, + ElementCount VF, TTI::PartialReductionExtendKind OpAExtend, + TTI::PartialReductionExtendKind OpBExtend, + std::optional BinOp = std::nullopt) const override { return InstructionCost::getInvalid(); } - unsigned getMaxInterleaveFactor(ElementCount VF) const { return 1; } + unsigned getMaxInterleaveFactor(ElementCount VF) const override { return 1; } InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info, ArrayRef Args, - const Instruction *CxtI = nullptr) const { + const Instruction *CxtI = nullptr) const override { // Widenable conditions will eventually lower into constants, so some // operations with them will be trivially optimized away. auto IsWidenableCondition = [](const Value *V) { @@ -648,23 +684,22 @@ class TargetTransformInfoImplBase : public TTI::Concept { InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { return InstructionCost::getInvalid(); } - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const { + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override { return 1; } InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, - const Instruction *I) const { + const Instruction *I) const override { switch (Opcode) { default: break; @@ -701,12 +736,13 @@ class TargetTransformInfoImplBase : public TTI::Concept { InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, - unsigned Index) const { + unsigned Index) const override { return 1; } - InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const { + InstructionCost + getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override { // A phi would be free, unless we're costing the throughput because it // will require a register. if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput) @@ -719,14 +755,14 @@ class TargetTransformInfoImplBase : public TTI::Concept { TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info, - const Instruction *I) const { + const Instruction *I) const override { return 1; } InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const { + Value *Op1) const override { return 1; } @@ -734,29 +770,30 @@ class TargetTransformInfoImplBase : public TTI::Concept { /// vector with 'Scalar' being the value being extracted,'User' being the user /// of the extract(nullptr if user is not known before vectorization) and /// 'Idx' being the extract lane. - InstructionCost getVectorInstrCost( - unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, - Value *Scalar, - ArrayRef> ScalarUserAndIdx) const { + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, + TTI::TargetCostKind CostKind, + unsigned Index, Value *Scalar, + ArrayRef> + ScalarUserAndIdx) const override { return 1; } InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, - unsigned Index) const { + unsigned Index) const override { return 1; } InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { return 1; } InstructionCost getInsertExtractValueCost(unsigned Opcode, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { // Note: The `insertvalue` cost here is chosen to match the default case of // getInstructionCost() -- as pior to adding this helper `insertvalue` was // not handled. @@ -769,54 +806,58 @@ class TargetTransformInfoImplBase : public TTI::Concept { unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo, - const Instruction *I) const { + const Instruction *I) const override { return 1; } InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - const Instruction *I) const { + const Instruction *I) const override { return 1; } - InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, - Align Alignment, unsigned AddressSpace, - TTI::TargetCostKind CostKind) const { + InstructionCost + getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind) const override { return 1; } - InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, - const Value *Ptr, bool VariableMask, - Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const { + InstructionCost + getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, + bool VariableMask, Align Alignment, + TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override { return 1; } - InstructionCost getExpandCompressMemoryOpCost( - unsigned Opcode, Type *DataTy, bool VariableMask, Align Alignment, - TTI::TargetCostKind CostKind, const Instruction *I = nullptr) const { + InstructionCost + getExpandCompressMemoryOpCost(unsigned Opcode, Type *DataTy, + bool VariableMask, Align Alignment, + TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override { return 1; } - InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, - const Value *Ptr, bool VariableMask, - Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const { + InstructionCost + getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, + bool VariableMask, Align Alignment, + TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override { return InstructionCost::getInvalid(); } InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond, bool UseMaskForGaps) const { + bool UseMaskForCond, bool UseMaskForGaps) const override { return 1; } - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const { + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override { switch (ICA.getID()) { default: break; @@ -866,54 +907,57 @@ class TargetTransformInfoImplBase : public TTI::Concept { return 1; } - InstructionCost getCallInstrCost(Function *F, Type *RetTy, - ArrayRef Tys, - TTI::TargetCostKind CostKind) const { + InstructionCost + getCallInstrCost(Function *F, Type *RetTy, ArrayRef Tys, + TTI::TargetCostKind CostKind) const override { return 1; } // Assume that we have a register of the right size for the type. - unsigned getNumberOfParts(Type *Tp) const { return 1; } + unsigned getNumberOfParts(Type *Tp) const override { return 1; } InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, - const SCEV *) const { + const SCEV *) const override { return 0; } - InstructionCost getArithmeticReductionCost(unsigned, VectorType *, - std::optional FMF, - TTI::TargetCostKind) const { + InstructionCost + getArithmeticReductionCost(unsigned, VectorType *, + std::optional FMF, + TTI::TargetCostKind) const override { return 1; } InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *, FastMathFlags, - TTI::TargetCostKind) const { + TTI::TargetCostKind) const override { return 1; } - InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, - Type *ResTy, VectorType *Ty, - std::optional FMF, - TTI::TargetCostKind CostKind) const { + InstructionCost + getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, + VectorType *Ty, std::optional FMF, + TTI::TargetCostKind CostKind) const override { return 1; } - InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, - VectorType *Ty, - TTI::TargetCostKind CostKind) const { + InstructionCost + getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, + TTI::TargetCostKind CostKind) const override { return 1; } - InstructionCost getCostOfKeepingLiveOverCall(ArrayRef Tys) const { + InstructionCost + getCostOfKeepingLiveOverCall(ArrayRef Tys) const override { return 0; } - bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const { + bool getTgtMemIntrinsic(IntrinsicInst *Inst, + MemIntrinsicInfo &Info) const override { return false; } - unsigned getAtomicMemIntrinsicMaxElementSize() const { + unsigned getAtomicMemIntrinsicMaxElementSize() const override { // Note for overrides: You must ensure for all element unordered-atomic // memory intrinsics that all power-of-2 element sizes up to, and // including, the return value of this method have a corresponding @@ -923,15 +967,14 @@ class TargetTransformInfoImplBase : public TTI::Concept { } Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, - Type *ExpectedType) const { + Type *ExpectedType) const override { return nullptr; } - Type * - getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, - unsigned SrcAddrSpace, unsigned DestAddrSpace, - Align SrcAlign, Align DestAlign, - std::optional AtomicElementSize) const { + Type *getMemcpyLoopLoweringType( + LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, + unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, + std::optional AtomicElementSize) const override { return AtomicElementSize ? Type::getIntNTy(Context, *AtomicElementSize * 8) : Type::getInt8Ty(Context); } @@ -940,7 +983,7 @@ class TargetTransformInfoImplBase : public TTI::Concept { SmallVectorImpl &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, - std::optional AtomicCpySize) const { + std::optional AtomicCpySize) const override { unsigned OpSizeInBytes = AtomicCpySize.value_or(1); Type *OpType = Type::getIntNTy(Context, OpSizeInBytes * 8); for (unsigned i = 0; i != RemainingBytes; i += OpSizeInBytes) @@ -948,7 +991,7 @@ class TargetTransformInfoImplBase : public TTI::Concept { } bool areInlineCompatible(const Function *Caller, - const Function *Callee) const { + const Function *Callee) const override { return (Caller->getFnAttribute("target-cpu") == Callee->getFnAttribute("target-cpu")) && (Caller->getFnAttribute("target-features") == @@ -956,123 +999,133 @@ class TargetTransformInfoImplBase : public TTI::Concept { } unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, - unsigned DefaultCallPenalty) const { + unsigned DefaultCallPenalty) const override { return DefaultCallPenalty; } bool areTypesABICompatible(const Function *Caller, const Function *Callee, - const ArrayRef &Types) const { + const ArrayRef &Types) const override { return (Caller->getFnAttribute("target-cpu") == Callee->getFnAttribute("target-cpu")) && (Caller->getFnAttribute("target-features") == Callee->getFnAttribute("target-features")); } - bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty) const { + bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty) const override { return false; } - bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty) const { + bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty) const override { return false; } - unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; } + unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override { + return 128; + } - bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; } + bool isLegalToVectorizeLoad(LoadInst *LI) const override { return true; } - bool isLegalToVectorizeStore(StoreInst *SI) const { return true; } + bool isLegalToVectorizeStore(StoreInst *SI) const override { return true; } bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const { + unsigned AddrSpace) const override { return true; } bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const { + unsigned AddrSpace) const override { return true; } bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, - ElementCount VF) const { + ElementCount VF) const override { return true; } - bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; } + bool isElementTypeLegalForScalableVector(Type *Ty) const override { + return true; + } unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, - VectorType *VecTy) const { + VectorType *VecTy) const override { return VF; } unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, - VectorType *VecTy) const { + VectorType *VecTy) const override { return VF; } - bool preferFixedOverScalableIfEqualCost() const { return false; } + bool preferFixedOverScalableIfEqualCost() const override { return false; } - bool preferInLoopReduction(RecurKind Kind, Type *Ty) const { return false; } - bool preferAlternateOpcodeVectorization() const { return true; } + bool preferInLoopReduction(RecurKind Kind, Type *Ty) const override { + return false; + } + bool preferAlternateOpcodeVectorization() const override { return true; } - bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty) const { + bool preferPredicatedReductionSelect(unsigned Opcode, + Type *Ty) const override { return false; } - bool preferEpilogueVectorization() const { + bool preferEpilogueVectorization() const override { return true; } + + bool shouldExpandReduction(const IntrinsicInst *II) const override { return true; } - bool shouldExpandReduction(const IntrinsicInst *II) const { return true; } - TTI::ReductionShuffle - getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const { + getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const override { return TTI::ReductionShuffle::SplitHalf; } - unsigned getGISelRematGlobalCost() const { return 1; } + unsigned getGISelRematGlobalCost() const override { return 1; } - unsigned getMinTripCountTailFoldingThreshold() const { return 0; } + unsigned getMinTripCountTailFoldingThreshold() const override { return 0; } - bool supportsScalableVectors() const { return false; } + bool supportsScalableVectors() const override { return false; } - bool enableScalableVectorization() const { return false; } + bool enableScalableVectorization() const override { return false; } bool hasActiveVectorLength(unsigned Opcode, Type *DataType, - Align Alignment) const { + Align Alignment) const override { return false; } bool isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &Ops) const { + SmallVectorImpl &Ops) const override { return false; } - bool isVectorShiftByScalarCheap(Type *Ty) const { return false; } + bool isVectorShiftByScalarCheap(Type *Ty) const override { return false; } TargetTransformInfo::VPLegalization - getVPLegalizationStrategy(const VPIntrinsic &PI) const { + getVPLegalizationStrategy(const VPIntrinsic &PI) const override { return TargetTransformInfo::VPLegalization( /* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard, /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert); } - bool hasArmWideBranch(bool) const { return false; } + bool hasArmWideBranch(bool) const override { return false; } - uint64_t getFeatureMask(const Function &F) const { return 0; } + uint64_t getFeatureMask(const Function &F) const override { return 0; } - bool isMultiversionedFunction(const Function &F) const { return false; } + bool isMultiversionedFunction(const Function &F) const override { + return false; + } - unsigned getMaxNumArgs() const { return UINT_MAX; } + unsigned getMaxNumArgs() const override { return UINT_MAX; } - unsigned getNumBytesToPadGlobalArray(unsigned Size, Type *ArrayType) const { + unsigned getNumBytesToPadGlobalArray(unsigned Size, + Type *ArrayType) const override { return 0; } void collectKernelLaunchBounds( const Function &F, - SmallVectorImpl> &LB) const {} + SmallVectorImpl> &LB) const override {} protected: // Obtain the minimum required size to hold the value (without the sign) @@ -1167,11 +1220,9 @@ class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase { explicit TargetTransformInfoImplCRTPBase(const DataLayout &DL) : BaseT(DL) {} public: - using BaseT::getGEPCost; - InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef Operands, Type *AccessType, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { assert(PointeeType && Ptr && "can't get GEPCost of nullptr"); auto *BaseGV = dyn_cast(Ptr->stripPointerCasts()); bool HasBaseReg = (BaseGV == nullptr); @@ -1247,11 +1298,10 @@ class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase { return TTI::TCC_Basic; } - InstructionCost getPointersChainCost(ArrayRef Ptrs, - const Value *Base, - const TTI::PointersChainInfo &Info, - Type *AccessTy, - TTI::TargetCostKind CostKind) const { + InstructionCost + getPointersChainCost(ArrayRef Ptrs, const Value *Base, + const TTI::PointersChainInfo &Info, Type *AccessTy, + TTI::TargetCostKind CostKind) const override { InstructionCost Cost = TTI::TCC_Free; // In the basic model we take into account GEP instructions only // (although here can come alloca instruction, a value, constants and/or @@ -1284,9 +1334,9 @@ class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase { return Cost; } - InstructionCost getInstructionCost(const User *U, - ArrayRef Operands, - TTI::TargetCostKind CostKind) const { + InstructionCost + getInstructionCost(const User *U, ArrayRef Operands, + TTI::TargetCostKind CostKind) const override { using namespace llvm::PatternMatch; auto *TargetTTI = static_cast(this); @@ -1586,7 +1636,7 @@ class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase { return CostKind == TTI::TCK_RecipThroughput ? -1 : TTI::TCC_Basic; } - bool isExpensiveToSpeculativelyExecute(const Instruction *I) const { + bool isExpensiveToSpeculativelyExecute(const Instruction *I) const override { auto *TargetTTI = static_cast(this); SmallVector Ops(I->operand_values()); InstructionCost Cost = TargetTTI->getInstructionCost( @@ -1594,7 +1644,7 @@ class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase { return Cost >= TargetTransformInfo::TCC_Expensive; } - bool supportsTailCallFor(const CallBase *CB) const { + bool supportsTailCallFor(const CallBase *CB) const override { return static_cast(this)->supportsTailCalls(); } }; diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index db5fb2f7f1a54..4720377164f06 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -359,14 +359,14 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { /// @{ bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, - unsigned *Fast) const { + unsigned *Fast) const override { EVT E = EVT::getIntegerVT(Context, BitWidth); return getTLI()->allowsMisalignedMemoryAccesses( E, AddressSpace, Alignment, MachineMemOperand::MONone, Fast); } bool areInlineCompatible(const Function *Caller, - const Function *Callee) const { + const Function *Callee) const override { const TargetMachine &TM = getTLI()->getTargetMachine(); const FeatureBitset &CallerBits = @@ -379,69 +379,71 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return (CallerBits & CalleeBits) == CalleeBits; } - bool hasBranchDivergence(const Function *F = nullptr) const { return false; } + bool hasBranchDivergence(const Function *F = nullptr) const override { + return false; + } - bool isSourceOfDivergence(const Value *V) const { return false; } + bool isSourceOfDivergence(const Value *V) const override { return false; } - bool isAlwaysUniform(const Value *V) const { return false; } + bool isAlwaysUniform(const Value *V) const override { return false; } - bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const { + bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override { return false; } - bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const { + bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override { return true; } - unsigned getFlatAddressSpace() const { + unsigned getFlatAddressSpace() const override { // Return an invalid address space. return -1; } bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes, - Intrinsic::ID IID) const { + Intrinsic::ID IID) const override { return false; } - bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const { + bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override { return getTLI()->getTargetMachine().isNoopAddrSpaceCast(FromAS, ToAS); } - unsigned getAssumedAddrSpace(const Value *V) const { + unsigned getAssumedAddrSpace(const Value *V) const override { return getTLI()->getTargetMachine().getAssumedAddrSpace(V); } - bool isSingleThreaded() const { + bool isSingleThreaded() const override { return getTLI()->getTargetMachine().Options.ThreadModel == ThreadModel::Single; } std::pair - getPredicatedAddrSpace(const Value *V) const { + getPredicatedAddrSpace(const Value *V) const override { return getTLI()->getTargetMachine().getPredicatedAddrSpace(V); } Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, - Value *NewV) const { + Value *NewV) const override { return nullptr; } - bool isLegalAddImmediate(int64_t imm) const { + bool isLegalAddImmediate(int64_t imm) const override { return getTLI()->isLegalAddImmediate(imm); } - bool isLegalAddScalableImmediate(int64_t Imm) const { + bool isLegalAddScalableImmediate(int64_t Imm) const override { return getTLI()->isLegalAddScalableImmediate(Imm); } - bool isLegalICmpImmediate(int64_t imm) const { + bool isLegalICmpImmediate(int64_t imm) const override { return getTLI()->isLegalICmpImmediate(imm); } bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I = nullptr, - int64_t ScalableOffset = 0) const { + int64_t ScalableOffset = 0) const override { TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; AM.BaseOffs = BaseOffset; @@ -456,7 +458,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { } unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, - Type *ScalarValTy) const { + Type *ScalarValTy) const override { auto &&IsSupportedByTarget = [this, ScalarMemTy, ScalarValTy](unsigned VF) { auto *SrcTy = FixedVectorType::get(ScalarMemTy, VF / 2); EVT VT = getTLI()->getValueType(DL, SrcTy); @@ -475,36 +477,37 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return VF; } - bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty) const { + bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty) const override { EVT VT = getTLI()->getValueType(DL, Ty); return getTLI()->isIndexedLoadLegal(getISDIndexedMode(M), VT); } - bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty) const { + bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty) const override { EVT VT = getTLI()->getValueType(DL, Ty); return getTLI()->isIndexedStoreLegal(getISDIndexedMode(M), VT); } - bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const { + bool isLSRCostLess(const TTI::LSRCost &C1, + const TTI::LSRCost &C2) const override { return TargetTransformInfoImplBase::isLSRCostLess(C1, C2); } - bool isNumRegsMajorCostOfLSR() const { + bool isNumRegsMajorCostOfLSR() const override { return TargetTransformInfoImplBase::isNumRegsMajorCostOfLSR(); } - bool shouldDropLSRSolutionIfLessProfitable() const { + bool shouldDropLSRSolutionIfLessProfitable() const override { return TargetTransformInfoImplBase::shouldDropLSRSolutionIfLessProfitable(); } - bool isProfitableLSRChainElement(Instruction *I) const { + bool isProfitableLSRChainElement(Instruction *I) const override { return TargetTransformInfoImplBase::isProfitableLSRChainElement(I); } InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, - unsigned AddrSpace) const { + unsigned AddrSpace) const override { TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; AM.BaseOffs = BaseOffset.getFixed(); @@ -516,36 +519,35 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return InstructionCost::getInvalid(); } - bool isTruncateFree(Type *Ty1, Type *Ty2) const { + bool isTruncateFree(Type *Ty1, Type *Ty2) const override { return getTLI()->isTruncateFree(Ty1, Ty2); } - bool isProfitableToHoist(Instruction *I) const { + bool isProfitableToHoist(Instruction *I) const override { return getTLI()->isProfitableToHoist(I); } - bool useAA() const { return getST()->useAA(); } + bool useAA() const override { return getST()->useAA(); } - bool isTypeLegal(Type *Ty) const { + bool isTypeLegal(Type *Ty) const override { EVT VT = getTLI()->getValueType(DL, Ty, /*AllowUnknown=*/true); return getTLI()->isTypeLegal(VT); } - unsigned getRegUsageForType(Type *Ty) const { + unsigned getRegUsageForType(Type *Ty) const override { EVT ETy = getTLI()->getValueType(DL, Ty); return getTLI()->getNumRegisters(Ty->getContext(), ETy); } InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef Operands, Type *AccessType, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { return BaseT::getGEPCost(PointeeType, Ptr, Operands, AccessType, CostKind); } - unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, - unsigned &JumpTableSize, - ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI) const { + unsigned getEstimatedNumberOfCaseClusters( + const SwitchInst &SI, unsigned &JumpTableSize, ProfileSummaryInfo *PSI, + BlockFrequencyInfo *BFI) const override { /// Try to find the estimated number of clusters. Note that the number of /// clusters identified in this function could be different from the actual /// numbers found in lowering. This function ignore switches that are @@ -601,13 +603,13 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return N; } - bool shouldBuildLookupTables() const { + bool shouldBuildLookupTables() const override { const TargetLoweringBase *TLI = getTLI(); return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other); } - bool shouldBuildRelLookupTables() const { + bool shouldBuildRelLookupTables() const override { const TargetMachine &TM = getTLI()->getTargetMachine(); // If non-PIC mode, do not generate a relative lookup table. if (!TM.isPositionIndependent()) @@ -632,16 +634,16 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return true; } - bool haveFastSqrt(Type *Ty) const { + bool haveFastSqrt(Type *Ty) const override { const TargetLoweringBase *TLI = getTLI(); EVT VT = TLI->getValueType(DL, Ty); return TLI->isTypeLegal(VT) && TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); } - bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; } + bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const override { return true; } - InstructionCost getFPOpCost(Type *Ty) const { + InstructionCost getFPOpCost(Type *Ty) const override { // Check whether FADD is available, as a proxy for floating-point in // general. const TargetLoweringBase *TLI = getTLI(); @@ -652,7 +654,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { } bool preferToKeepConstantsAttached(const Instruction &Inst, - const Function &Fn) const { + const Function &Fn) const override { switch (Inst.getOpcode()) { default: break; @@ -670,17 +672,20 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return false; } - unsigned getInliningThresholdMultiplier() const { return 1; } - unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; } - unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const { + unsigned getInliningThresholdMultiplier() const override { return 1; } + unsigned adjustInliningThreshold(const CallBase *CB) const override { + return 0; + } + unsigned getCallerAllocaCost(const CallBase *CB, + const AllocaInst *AI) const override { return 0; } - int getInlinerVectorBonusPercent() const { return 150; } + int getInlinerVectorBonusPercent() const override { return 150; } void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const { + OptimizationRemarkEmitter *ORE) const override { // This unrolling functionality is target independent, but to provide some // motivation for its intended use, for x86: @@ -751,7 +756,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { } void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const { + TTI::PeelingPreferences &PP) const override { PP.PeelCount = 0; PP.AllowPeeling = true; PP.AllowLoopNestsPeeling = false; @@ -760,32 +765,32 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, - HardwareLoopInfo &HWLoopInfo) const { + HardwareLoopInfo &HWLoopInfo) const override { return BaseT::isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo); } - unsigned getEpilogueVectorizationMinVF() const { + unsigned getEpilogueVectorizationMinVF() const override { return BaseT::getEpilogueVectorizationMinVF(); } - bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const { + bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const override { return BaseT::preferPredicateOverEpilogue(TFI); } TailFoldingStyle - getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const { + getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const override { return BaseT::getPreferredTailFoldingStyle(IVUpdateMayOverflow); } - std::optional instCombineIntrinsic(InstCombiner &IC, - IntrinsicInst &II) const { + std::optional + instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override { return BaseT::instCombineIntrinsic(IC, II); } std::optional simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, - bool &KnownBitsComputed) const { + bool &KnownBitsComputed) const override { return BaseT::simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known, KnownBitsComputed); } @@ -794,20 +799,20 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function - SimplifyAndSetOp) const { + SimplifyAndSetOp) const override { return BaseT::simplifyDemandedVectorEltsIntrinsic( IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, SimplifyAndSetOp); } virtual std::optional - getCacheSize(TargetTransformInfo::CacheLevel Level) const { + getCacheSize(TargetTransformInfo::CacheLevel Level) const override { return std::optional( getST()->getCacheSize(static_cast(Level))); } virtual std::optional - getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const { + getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const override { std::optional TargetResult = getST()->getCacheAssociativity(static_cast(Level)); @@ -817,31 +822,31 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return BaseT::getCacheAssociativity(Level); } - virtual unsigned getCacheLineSize() const { + virtual unsigned getCacheLineSize() const override { return getST()->getCacheLineSize(); } - virtual unsigned getPrefetchDistance() const { + virtual unsigned getPrefetchDistance() const override { return getST()->getPrefetchDistance(); } virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, - bool HasCall) const { + bool HasCall) const override { return getST()->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses, NumPrefetches, HasCall); } - virtual unsigned getMaxPrefetchIterationsAhead() const { + virtual unsigned getMaxPrefetchIterationsAhead() const override { return getST()->getMaxPrefetchIterationsAhead(); } - virtual bool enableWritePrefetching() const { + virtual bool enableWritePrefetching() const override { return getST()->enableWritePrefetching(); } - virtual bool shouldPrefetchAddressSpace(unsigned AS) const { + virtual bool shouldPrefetchAddressSpace(unsigned AS) const override { return getST()->shouldPrefetchAddressSpace(AS); } @@ -850,22 +855,23 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { /// \name Vector TTI Implementations /// @{ - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override { return TypeSize::getFixed(32); } - std::optional getMaxVScale() const { return std::nullopt; } - std::optional getVScaleForTuning() const { return std::nullopt; } - bool isVScaleKnownToBeAPowerOfTwo() const { return false; } + std::optional getMaxVScale() const override { return std::nullopt; } + std::optional getVScaleForTuning() const override { + return std::nullopt; + } + bool isVScaleKnownToBeAPowerOfTwo() const override { return false; } /// Estimate the overhead of scalarizing an instruction. Insert and Extract /// are set if the demanded result elements need to be inserted and/or /// extracted from vectors. - InstructionCost getScalarizationOverhead(VectorType *InTy, - const APInt &DemandedElts, - bool Insert, bool Extract, - TTI::TargetCostKind CostKind, - ArrayRef VL = {}) const { + InstructionCost getScalarizationOverhead( + VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract, + TTI::TargetCostKind CostKind, ArrayRef VL = {}) const override { /// FIXME: a bitfield is not a reasonable abstraction for talking about /// which elements are needed from a scalable vector if (isa(InTy)) @@ -894,22 +900,24 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return Cost; } - bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const { + bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const override { return false; } - bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, - unsigned ScalarOpdIdx) const { + bool + isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, + unsigned ScalarOpdIdx) const override { return false; } bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, - int OpdIdx) const { + int OpdIdx) const override { return OpdIdx == -1; } - bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, - int RetIdx) const { + bool + isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, + int RetIdx) const override { return RetIdx == 0; } @@ -929,10 +937,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { /// Estimate the overhead of scalarizing an instructions unique /// non-constant operands. The (potentially vector) types to use for each of /// argument are passes via Tys. - InstructionCost - getOperandsScalarizationOverhead(ArrayRef Args, - ArrayRef Tys, - TTI::TargetCostKind CostKind) const { + InstructionCost getOperandsScalarizationOverhead( + ArrayRef Args, ArrayRef Tys, + TTI::TargetCostKind CostKind) const override { assert(Args.size() == Tys.size() && "Expected matching Args and Tys"); InstructionCost Cost = 0; @@ -1011,14 +1018,14 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { } } - unsigned getMaxInterleaveFactor(ElementCount VF) const { return 1; } + unsigned getMaxInterleaveFactor(ElementCount VF) const override { return 1; } InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const { + const Instruction *CxtI = nullptr) const override { // Check if any of the operands are vector operands. const TargetLoweringBase *TLI = getTLI(); int ISD = TLI->InstructionOpcodeToISD(Opcode); @@ -1142,12 +1149,11 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return Kind; } - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const { + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override { switch (improveShuffleKindFromMask(Kind, Mask, Tp, Index, SubTp)) { case TTI::SK_Broadcast: if (auto *FVT = dyn_cast(Tp)) @@ -1172,10 +1178,10 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { llvm_unreachable("Unknown TTI::ShuffleKind"); } - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const { + InstructionCost + getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override { if (BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I) == 0) return 0; @@ -1334,7 +1340,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, - unsigned Index) const { + unsigned Index) const override { TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; return thisT()->getVectorInstrCost(Instruction::ExtractElement, VecTy, CostKind, Index, nullptr, nullptr) + @@ -1342,8 +1348,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { TTI::CastContextHint::None, CostKind); } - InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const { + InstructionCost + getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override { return BaseT::getCFInstrCost(Opcode, CostKind, I); } @@ -1352,7 +1359,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const { + const Instruction *I = nullptr) const override { const TargetLoweringBase *TLI = getTLI(); int ISD = TLI->InstructionOpcodeToISD(Opcode); assert(ISD && "Invalid opcode"); @@ -1403,7 +1410,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const { + Value *Op1) const override { return getRegUsageForType(Val->getScalarType()); } @@ -1411,17 +1418,18 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { /// vector with 'Scalar' being the value being extracted,'User' being the user /// of the extract(nullptr if user is not known before vectorization) and /// 'Idx' being the extract lane. - InstructionCost getVectorInstrCost( - unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, - Value *Scalar, - ArrayRef> ScalarUserAndIdx) const { + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, + TTI::TargetCostKind CostKind, + unsigned Index, Value *Scalar, + ArrayRef> + ScalarUserAndIdx) const override { return thisT()->getVectorInstrCost(Opcode, Val, CostKind, Index, nullptr, nullptr); } InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, - unsigned Index) const { + unsigned Index) const override { Value *Op0 = nullptr; Value *Op1 = nullptr; if (auto *IE = dyn_cast(&I)) { @@ -1435,7 +1443,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { assert(DemandedDstElts.getBitWidth() == (unsigned)VF * ReplicationFactor && "Unexpected size of DemandedDstElts."); @@ -1469,7 +1477,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const { + const Instruction *I = nullptr) const override { assert(!Src->isVoidTy() && "Invalid type"); // Assume types, such as structs, are expensive. if (getTLI()->getValueType(DL, Src, true) == MVT::Other) @@ -1510,26 +1518,29 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return Cost; } - InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, - Align Alignment, unsigned AddressSpace, - TTI::TargetCostKind CostKind) const { + InstructionCost + getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind) const override { // TODO: Pass on AddressSpace when we have test coverage. return getCommonMaskedMemoryOpCost(Opcode, DataTy, Alignment, true, false, CostKind); } - InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, - const Value *Ptr, bool VariableMask, - Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const { + InstructionCost + getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, + bool VariableMask, Align Alignment, + TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override { return getCommonMaskedMemoryOpCost(Opcode, DataTy, Alignment, VariableMask, true, CostKind); } - InstructionCost getExpandCompressMemoryOpCost( - unsigned Opcode, Type *DataTy, bool VariableMask, Align Alignment, - TTI::TargetCostKind CostKind, const Instruction *I = nullptr) const { + InstructionCost + getExpandCompressMemoryOpCost(unsigned Opcode, Type *DataTy, + bool VariableMask, Align Alignment, + TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override { // Treat expand load/compress store as gather/scatter operation. // TODO: implement more precise cost estimation for these intrinsics. return getCommonMaskedMemoryOpCost(Opcode, DataTy, Alignment, VariableMask, @@ -1540,7 +1551,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, - const Instruction *I) const { + const Instruction *I) const override { // For a target without strided memory operations (or for an illegal // operation type on one which does), assume we lower to a gather/scatter // operation. (Which may in turn be scalarized.) @@ -1551,7 +1562,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond = false, bool UseMaskForGaps = false) const { + bool UseMaskForCond = false, bool UseMaskForGaps = false) const override { // We cannot scalarize scalable vectors, so return Invalid. if (isa(VecTy)) @@ -1692,8 +1703,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { } /// Get intrinsic cost based on arguments. - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const { + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override { // Check for generically free intrinsics. if (BaseT::getIntrinsicInstrCost(ICA, CostKind) == 0) return 0; @@ -2859,13 +2871,13 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { /// \param RetTy Return value types. /// \param Tys Argument types. /// \returns The cost of Call instruction. - InstructionCost getCallInstrCost(Function *F, Type *RetTy, - ArrayRef Tys, - TTI::TargetCostKind CostKind) const { + InstructionCost + getCallInstrCost(Function *F, Type *RetTy, ArrayRef Tys, + TTI::TargetCostKind CostKind) const override { return 10; } - unsigned getNumberOfParts(Type *Tp) const { + unsigned getNumberOfParts(Type *Tp) const override { std::pair LT = getTypeLegalizationCost(Tp); if (!LT.first.isValid()) return 0; @@ -2883,7 +2895,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { } InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *, - const SCEV *) const { + const SCEV *) const override { return 0; } @@ -3004,7 +3016,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional FMF, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { assert(Ty && "Unknown reduction vector type"); if (TTI::requiresOrderedReduction(FMF)) return getOrderedReductionCost(Opcode, Ty, CostKind); @@ -3013,9 +3025,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { /// Try to calculate op costs for min/max reduction operations. /// \param CondTy Conditional type for the Select instruction. - InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, - FastMathFlags FMF, - TTI::TargetCostKind CostKind) const { + InstructionCost + getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, + TTI::TargetCostKind CostKind) const override { // Targets must implement a default value for the scalable case, since // we don't know how many lanes the vector has. if (isa(Ty)) @@ -3061,10 +3073,10 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { CostKind, 0, nullptr, nullptr); } - InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, - Type *ResTy, VectorType *Ty, - std::optional FMF, - TTI::TargetCostKind CostKind) const { + InstructionCost + getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, + VectorType *Ty, std::optional FMF, + TTI::TargetCostKind CostKind) const override { if (auto *FTy = dyn_cast(Ty); FTy && IsUnsigned && Opcode == Instruction::Add && FTy->getElementType() == IntegerType::getInt1Ty(Ty->getContext())) { @@ -3090,9 +3102,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return RedCost + ExtCost; } - InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, - VectorType *Ty, - TTI::TargetCostKind CostKind) const { + InstructionCost + getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, + TTI::TargetCostKind CostKind) const override { // Without any native support, this is equivalent to the cost of // vecreduce.add(mul(ext(Ty A), ext(Ty B))) or // vecreduce.add(mul(A, B)). diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index 7da2820bee323..18d1836611858 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -83,17 +83,17 @@ class AArch64TTIImpl : public BasicTTIImplBase { TLI(ST->getTargetLowering()) {} bool areInlineCompatible(const Function *Caller, - const Function *Callee) const; + const Function *Callee) const override; bool areTypesABICompatible(const Function *Caller, const Function *Callee, - const ArrayRef &Types) const; + const ArrayRef &Types) const override; unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, - unsigned DefaultCallPenalty) const; + unsigned DefaultCallPenalty) const override; - uint64_t getFeatureMask(const Function &F) const; + uint64_t getFeatureMask(const Function &F) const override; - bool isMultiversionedFunction(const Function &F) const; + bool isMultiversionedFunction(const Function &F) const override; /// \name Scalar TTI Implementations /// @{ @@ -101,28 +101,28 @@ class AArch64TTIImpl : public BasicTTIImplBase { using BaseT::getIntImmCost; InstructionCost getIntImmCost(int64_t Val) const; InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, - Instruction *Inst = nullptr) const; - InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, - const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const; + Instruction *Inst = nullptr) const override; + InstructionCost + getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty, TTI::TargetCostKind CostKind) const override; + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override; /// @} /// \name Vector TTI Implementations /// @{ - bool enableInterleavedAccessVectorization() const { return true; } + bool enableInterleavedAccessVectorization() const override { return true; } - bool enableMaskedInterleavedAccessVectorization() const { + bool enableMaskedInterleavedAccessVectorization() const override { return ST->hasSVE(); } - unsigned getNumberOfRegisters(unsigned ClassID) const { + unsigned getNumberOfRegisters(unsigned ClassID) const override { bool Vector = (ClassID == 1); if (Vector) { if (ST->hasNEON()) @@ -132,31 +132,34 @@ class AArch64TTIImpl : public BasicTTIImplBase { return 31; } - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const; + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override; - std::optional instCombineIntrinsic(InstCombiner &IC, - IntrinsicInst &II) const; + std::optional + instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override; std::optional simplifyDemandedVectorEltsIntrinsic( InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function - SimplifyAndSetOp) const; + SimplifyAndSetOp) const override; - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override; - unsigned getMinVectorRegisterBitWidth() const { + unsigned getMinVectorRegisterBitWidth() const override { return ST->getMinVectorRegisterBitWidth(); } - std::optional getVScaleForTuning() const { + std::optional getVScaleForTuning() const override { return ST->getVScaleForTuning(); } - bool isVScaleKnownToBeAPowerOfTwo() const { return true; } + bool isVScaleKnownToBeAPowerOfTwo() const override { return true; } - bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const; + bool shouldMaximizeVectorBandwidth( + TargetTransformInfo::RegisterKind K) const override; /// Try to return an estimate cost factor that can be used as a multiplier /// when scalarizing an operation for a vector with ElementCount \p VF. @@ -169,56 +172,58 @@ class AArch64TTIImpl : public BasicTTIImplBase { return VF.getKnownMinValue() * ST->getVScaleForTuning(); } - unsigned getMaxInterleaveFactor(ElementCount VF) const; + unsigned getMaxInterleaveFactor(ElementCount VF) const override; - bool prefersVectorizedAddressing() const; + bool prefersVectorizedAddressing() const override; - InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, - Align Alignment, unsigned AddressSpace, - TTI::TargetCostKind CostKind) const; + InstructionCost + getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind) const override; - InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, - const Value *Ptr, bool VariableMask, - Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + InstructionCost + getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, + bool VariableMask, Align Alignment, + TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; bool isExtPartOfAvgExpr(const Instruction *ExtUser, Type *Dst, Type *Src) const; - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + InstructionCost + getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, - unsigned Index) const; + unsigned Index) const override; InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; + Value *Op1) const override; /// \param ScalarUserAndIdx encodes the information about extracts from a /// vector with 'Scalar' being the value being extracted,'User' being the user /// of the extract(nullptr if user is not known before vectorization) and /// 'Idx' being the extract lane. - InstructionCost getVectorInstrCost( - unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, - Value *Scalar, - ArrayRef> ScalarUserAndIdx) const; + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, + TTI::TargetCostKind CostKind, + unsigned Index, Value *Scalar, + ArrayRef> + ScalarUserAndIdx) const override; InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, - unsigned Index) const; + unsigned Index) const override; - InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, - FastMathFlags FMF, - TTI::TargetCostKind CostKind) const; + InstructionCost + getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, + TTI::TargetCostKind CostKind) const override; InstructionCost getArithmeticReductionCostSVE(unsigned Opcode, VectorType *ValTy, @@ -232,43 +237,45 @@ class AArch64TTIImpl : public BasicTTIImplBase { TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + const Instruction *CxtI = nullptr) const override; InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE, - const SCEV *Ptr) const; + const SCEV *Ptr) const override; InstructionCost getCmpSelInstrCost( unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; - TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, - bool IsZeroCmp) const; + TTI::MemCmpExpansionOptions + enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override; bool useNeonVector(const Type *Ty) const; InstructionCost getMemoryOpCost( unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; - InstructionCost getCostOfKeepingLiveOverCall(ArrayRef Tys) const; + InstructionCost + getCostOfKeepingLiveOverCall(ArrayRef Tys) const override; void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; + TTI::PeelingPreferences &PP) const override; Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, - Type *ExpectedType) const; + Type *ExpectedType) const override; - bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const; + bool getTgtMemIntrinsic(IntrinsicInst *Inst, + MemIntrinsicInfo &Info) const override; - bool isElementTypeLegalForScalableVector(Type *Ty) const { + bool isElementTypeLegalForScalableVector(Type *Ty) const override { if (Ty->isPointerTy()) return true; @@ -298,12 +305,12 @@ class AArch64TTIImpl : public BasicTTIImplBase { } bool isLegalMaskedLoad(Type *DataType, Align Alignment, - unsigned /*AddressSpace*/) const { + unsigned /*AddressSpace*/) const override { return isLegalMaskedLoadStore(DataType, Alignment); } bool isLegalMaskedStore(Type *DataType, Align Alignment, - unsigned /*AddressSpace*/) const { + unsigned /*AddressSpace*/) const override { return isLegalMaskedLoadStore(DataType, Alignment); } @@ -320,15 +327,16 @@ class AArch64TTIImpl : public BasicTTIImplBase { return isElementTypeLegalForScalableVector(DataType->getScalarType()); } - bool isLegalMaskedGather(Type *DataType, Align Alignment) const { + bool isLegalMaskedGather(Type *DataType, Align Alignment) const override { return isLegalMaskedGatherScatter(DataType); } - bool isLegalMaskedScatter(Type *DataType, Align Alignment) const { + bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override { return isLegalMaskedGatherScatter(DataType); } - bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const { + bool isLegalBroadcastLoad(Type *ElementTy, + ElementCount NumElements) const override { // Return true if we can generate a `ld1r` splat load instruction. if (!ST->hasNEON() || NumElements.isScalable()) return false; @@ -362,11 +370,11 @@ class AArch64TTIImpl : public BasicTTIImplBase { return BaseT::isLegalNTStore(DataType, Alignment); } - bool isLegalNTStore(Type *DataType, Align Alignment) const { + bool isLegalNTStore(Type *DataType, Align Alignment) const override { return isLegalNTStoreLoad(DataType, Alignment); } - bool isLegalNTLoad(Type *DataType, Align Alignment) const { + bool isLegalNTLoad(Type *DataType, Align Alignment) const override { // Only supports little-endian targets. if (ST->isLittleEndian()) return isLegalNTStoreLoad(DataType, Alignment); @@ -378,29 +386,31 @@ class AArch64TTIImpl : public BasicTTIImplBase { Type *AccumType, ElementCount VF, TTI::PartialReductionExtendKind OpAExtend, TTI::PartialReductionExtendKind OpBExtend, - std::optional BinOp) const; + std::optional BinOp) const override; - bool enableOrderedReductions() const { return true; } + bool enableOrderedReductions() const override { return true; } InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond = false, bool UseMaskForGaps = false) const; + bool UseMaskForCond = false, bool UseMaskForGaps = false) const override; bool shouldConsiderAddressTypePromotion( - const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const; + const Instruction &I, + bool &AllowPromotionWithoutCommonHeader) const override; - bool shouldExpandReduction(const IntrinsicInst *II) const { return false; } - - unsigned getGISelRematGlobalCost() const { - return 2; + bool shouldExpandReduction(const IntrinsicInst *II) const override { + return false; } - unsigned getMinTripCountTailFoldingThreshold() const { + unsigned getGISelRematGlobalCost() const override { return 2; } + + unsigned getMinTripCountTailFoldingThreshold() const override { return ST->hasSVE() ? 5 : 0; } - TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow) const { + TailFoldingStyle + getPreferredTailFoldingStyle(bool IVUpdateMayOverflow) const override { if (ST->hasSVE()) return IVUpdateMayOverflow ? TailFoldingStyle::DataAndControlFlowWithoutRuntimeCheck @@ -409,51 +419,49 @@ class AArch64TTIImpl : public BasicTTIImplBase { return TailFoldingStyle::DataWithoutLaneMask; } - bool preferFixedOverScalableIfEqualCost() const; + bool preferFixedOverScalableIfEqualCost() const override; - unsigned getEpilogueVectorizationMinVF() const; + unsigned getEpilogueVectorizationMinVF() const override; - bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const; + bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const override; - bool supportsScalableVectors() const { + bool supportsScalableVectors() const override { return ST->isSVEorStreamingSVEAvailable(); } - bool enableScalableVectorization() const; + bool enableScalableVectorization() const override; bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, - ElementCount VF) const; + ElementCount VF) const override; - bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty) const { + bool preferPredicatedReductionSelect(unsigned Opcode, + Type *Ty) const override { return ST->hasSVE(); } InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional FMF, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; - InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, - Type *ResTy, VectorType *ValTy, - std::optional FMF, - TTI::TargetCostKind CostKind) const; + InstructionCost + getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, + VectorType *ValTy, std::optional FMF, + TTI::TargetCostKind CostKind) const override; InstructionCost getMulAccReductionCost( bool IsUnsigned, Type *ResTy, VectorType *Ty, - TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const; + TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const override; - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override; - InstructionCost getScalarizationOverhead(VectorType *Ty, - const APInt &DemandedElts, - bool Insert, bool Extract, - TTI::TargetCostKind CostKind, - ArrayRef VL = {}) const; + InstructionCost getScalarizationOverhead( + VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, + TTI::TargetCostKind CostKind, ArrayRef VL = {}) const override; /// Return the cost of the scaling factor used in the addressing /// mode represented by AM for this target, for a load/store @@ -462,14 +470,17 @@ class AArch64TTIImpl : public BasicTTIImplBase { /// If the AM is not supported, it returns an invalid cost. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, - int64_t Scale, unsigned AddrSpace) const; + int64_t Scale, + unsigned AddrSpace) const override; - bool enableSelectOptimize() const { return ST->enableSelectOptimize(); } + bool enableSelectOptimize() const override { + return ST->enableSelectOptimize(); + } - bool shouldTreatInstructionLikeSelect(const Instruction *I) const; + bool shouldTreatInstructionLikeSelect(const Instruction *I) const override; unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, - Type *ScalarValTy) const { + Type *ScalarValTy) const override { // We can vectorize store v4i8. if (ScalarMemTy->isIntegerTy(8) && isPowerOf2_32(VF) && VF >= 4) return 4; @@ -477,13 +488,13 @@ class AArch64TTIImpl : public BasicTTIImplBase { return BaseT::getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy); } - std::optional getMinPageSize() const { return 4096; } + std::optional getMinPageSize() const override { return 4096; } bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, - const TargetTransformInfo::LSRCost &C2) const; + const TargetTransformInfo::LSRCost &C2) const override; bool isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &Ops) const; + SmallVectorImpl &Ops) const override; /// @} }; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h index 57682ff8ed76f..1a27cb6f814d2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -52,12 +52,12 @@ class AMDGPUTTIImpl final : public BasicTTIImplBase { void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; + TTI::PeelingPreferences &PP) const override; - uint64_t getMaxMemIntrinsicInlineSizeThreshold() const; + uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override; }; class GCNTTIImpl final : public BasicTTIImplBase { @@ -104,64 +104,65 @@ class GCNTTIImpl final : public BasicTTIImplBase { public: explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F); - bool hasBranchDivergence(const Function *F = nullptr) const; + bool hasBranchDivergence(const Function *F = nullptr) const override; void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; + TTI::PeelingPreferences &PP) const override; - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const { + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override { assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); return TTI::PSK_FastHardware; } - unsigned getNumberOfRegisters(unsigned RCID) const; - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const; - unsigned getMinVectorRegisterBitWidth() const; - unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const; + unsigned getNumberOfRegisters(unsigned RCID) const override; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override; + unsigned getMinVectorRegisterBitWidth() const override; + unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override; unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, - VectorType *VecTy) const; + VectorType *VecTy) const override; unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, - VectorType *VecTy) const; - unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const; + VectorType *VecTy) const override; + unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override; bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const; bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const; + unsigned AddrSpace) const override; bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const; + unsigned AddrSpace) const override; - uint64_t getMaxMemIntrinsicInlineSizeThreshold() const; - Type * - getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, - unsigned SrcAddrSpace, unsigned DestAddrSpace, - Align SrcAlign, Align DestAlign, - std::optional AtomicElementSize) const; + uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override; + Type *getMemcpyLoopLoweringType( + LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, + unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, + std::optional AtomicElementSize) const override; void getMemcpyLoopResidualLoweringType( SmallVectorImpl &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, - std::optional AtomicCpySize) const; - unsigned getMaxInterleaveFactor(ElementCount VF) const; + std::optional AtomicCpySize) const override; + unsigned getMaxInterleaveFactor(ElementCount VF) const override; - bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const; + bool getTgtMemIntrinsic(IntrinsicInst *Inst, + MemIntrinsicInfo &Info) const override; InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + const Instruction *CxtI = nullptr) const override; InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; bool isInlineAsmSourceOfDivergence(const CallInst *CI, ArrayRef Indices = {}) const; @@ -170,13 +171,13 @@ class GCNTTIImpl final : public BasicTTIImplBase { InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; + Value *Op1) const override; bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const; - bool isSourceOfDivergence(const Value *V) const; - bool isAlwaysUniform(const Value *V) const; + bool isSourceOfDivergence(const Value *V) const override; + bool isAlwaysUniform(const Value *V) const override; - bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const { + bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override { // Address space casts must cast between different address spaces. if (FromAS == ToAS) return false; @@ -197,11 +198,11 @@ class GCNTTIImpl final : public BasicTTIImplBase { return false; } - bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const { + bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override { return AMDGPU::addrspacesMayAlias(AS0, AS1); } - unsigned getFlatAddressSpace() const { + unsigned getFlatAddressSpace() const override { // Don't bother running InferAddressSpaces pass on graphics shaders which // don't use flat addressing. if (IsGraphics) @@ -210,15 +211,16 @@ class GCNTTIImpl final : public BasicTTIImplBase { } bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes, - Intrinsic::ID IID) const; + Intrinsic::ID IID) const override; - bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const { + bool + canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override { return AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS && AS != AMDGPUAS::PRIVATE_ADDRESS; } Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, - Value *NewV) const; + Value *NewV) const override; bool canSimplifyLegacyMulToMul(const Instruction &I, const Value *Op0, const Value *Op1, InstCombiner &IC) const; @@ -226,8 +228,8 @@ class GCNTTIImpl final : public BasicTTIImplBase { bool simplifyDemandedLaneMaskArg(InstCombiner &IC, IntrinsicInst &II, unsigned LaneAgIdx) const; - std::optional instCombineIntrinsic(InstCombiner &IC, - IntrinsicInst &II) const; + std::optional + instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override; Value *simplifyAMDGCNLaneIntrinsicDemanded(InstCombiner &IC, IntrinsicInst &II, @@ -238,40 +240,43 @@ class GCNTTIImpl final : public BasicTTIImplBase { InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function - SimplifyAndSetOp) const; + SimplifyAndSetOp) const override; InstructionCost getVectorSplitCost() const { return 0; } - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override; bool isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &Ops) const; + SmallVectorImpl &Ops) const override; bool areInlineCompatible(const Function *Caller, - const Function *Callee) const; + const Function *Callee) const override; - int getInliningLastCallToStaticBonus() const; - unsigned getInliningThresholdMultiplier() const { return 11; } - unsigned adjustInliningThreshold(const CallBase *CB) const; - unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const; + int getInliningLastCallToStaticBonus() const override; + unsigned getInliningThresholdMultiplier() const override { return 11; } + unsigned adjustInliningThreshold(const CallBase *CB) const override; + unsigned getCallerAllocaCost(const CallBase *CB, + const AllocaInst *AI) const override; - int getInlinerVectorBonusPercent() const { return InlinerVectorBonusPercent; } + int getInlinerVectorBonusPercent() const override { + return InlinerVectorBonusPercent; + } InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional FMF, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const; - InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, - FastMathFlags FMF, - TTI::TargetCostKind CostKind) const; + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override; + InstructionCost + getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, + TTI::TargetCostKind CostKind) const override; /// Data cache line size for LoopDataPrefetch pass. Has no use before GFX12. unsigned getCacheLineSize() const override { return 128; } @@ -284,7 +289,7 @@ class GCNTTIImpl final : public BasicTTIImplBase { bool shouldPrefetchAddressSpace(unsigned AS) const override; void collectKernelLaunchBounds( const Function &F, - SmallVectorImpl> &LB) const; + SmallVectorImpl> &LB) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h index 163d01516efa7..5be87c6d10299 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h @@ -43,28 +43,29 @@ class R600TTIImpl final : public BasicTTIImplBase { void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; + TTI::PeelingPreferences &PP) const override; unsigned getHardwareNumberOfRegisters(bool Vec) const; - unsigned getNumberOfRegisters(unsigned ClassID) const; - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const; - unsigned getMinVectorRegisterBitWidth() const; - unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const; + unsigned getNumberOfRegisters(unsigned ClassID) const override; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override; + unsigned getMinVectorRegisterBitWidth() const override; + unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override; bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const; bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const; + unsigned AddrSpace) const override; bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const; - unsigned getMaxInterleaveFactor(ElementCount VF) const; + unsigned AddrSpace) const override; + unsigned getMaxInterleaveFactor(ElementCount VF) const override; InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; + Value *Op1) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index 2a3ad431cc169..c94c56c195685 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -105,49 +105,50 @@ class ARMTTIImpl : public BasicTTIImplBase { TLI(ST->getTargetLowering()) {} bool areInlineCompatible(const Function *Caller, - const Function *Callee) const; + const Function *Callee) const override; - bool enableInterleavedAccessVectorization() const { return true; } + bool enableInterleavedAccessVectorization() const override { return true; } TTI::AddressingModeKind - getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const; + getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const override; /// Floating-point computation using ARMv8 AArch32 Advanced /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD /// and Arm MVE are IEEE-754 compliant. - bool isFPVectorizationPotentiallyUnsafe() const { + bool isFPVectorizationPotentiallyUnsafe() const override { return !ST->isTargetDarwin() && !ST->hasMVEFloatOps(); } - std::optional instCombineIntrinsic(InstCombiner &IC, - IntrinsicInst &II) const; + std::optional + instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override; std::optional simplifyDemandedVectorEltsIntrinsic( InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function - SimplifyAndSetOp) const; + SimplifyAndSetOp) const override; /// \name Scalar TTI Implementations /// @{ InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, - const APInt &Imm, Type *Ty) const; + const APInt &Imm, + Type *Ty) const override; using BaseT::getIntImmCost; InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, - Instruction *Inst = nullptr) const; + Instruction *Inst = nullptr) const override; /// @} /// \name Vector TTI Implementations /// @{ - unsigned getNumberOfRegisters(unsigned ClassID) const { + unsigned getNumberOfRegisters(unsigned ClassID) const override { bool Vector = (ClassID == 1); if (Vector) { if (ST->hasNEON()) @@ -162,7 +163,8 @@ class ARMTTIImpl : public BasicTTIImplBase { return 13; } - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override { switch (K) { case TargetTransformInfo::RGK_Scalar: return TypeSize::getFixed(32); @@ -178,21 +180,22 @@ class ARMTTIImpl : public BasicTTIImplBase { llvm_unreachable("Unsupported register kind"); } - unsigned getMaxInterleaveFactor(ElementCount VF) const { + unsigned getMaxInterleaveFactor(ElementCount VF) const override { return ST->getMaxInterleaveFactor(); } - bool isProfitableLSRChainElement(Instruction *I) const; + bool isProfitableLSRChainElement(Instruction *I) const override; bool isLegalMaskedLoad(Type *DataTy, Align Alignment, - unsigned AddressSpace) const; + unsigned AddressSpace) const override; bool isLegalMaskedStore(Type *DataTy, Align Alignment, - unsigned AddressSpace) const { + unsigned AddressSpace) const override { return isLegalMaskedLoad(DataTy, Alignment, AddressSpace); } - bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) const { + bool forceScalarizeMaskedGather(VectorType *VTy, + Align Alignment) const override { // For MVE, we have a custom lowering pass that will already have custom // legalised any gathers that we can lower to MVE intrinsics, and want to // expand all the rest. The pass runs before the masked intrinsic lowering @@ -200,107 +203,112 @@ class ARMTTIImpl : public BasicTTIImplBase { return true; } - bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment) const { + bool forceScalarizeMaskedScatter(VectorType *VTy, + Align Alignment) const override { return forceScalarizeMaskedGather(VTy, Alignment); } - bool isLegalMaskedGather(Type *Ty, Align Alignment) const; + bool isLegalMaskedGather(Type *Ty, Align Alignment) const override; - bool isLegalMaskedScatter(Type *Ty, Align Alignment) const { + bool isLegalMaskedScatter(Type *Ty, Align Alignment) const override { return isLegalMaskedGather(Ty, Alignment); } - InstructionCost getMemcpyCost(const Instruction *I) const; + InstructionCost getMemcpyCost(const Instruction *I) const override; - uint64_t getMaxMemIntrinsicInlineSizeThreshold() const { + uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override { return ST->getMaxInlineSizeThreshold(); } int getNumMemOps(const IntrinsicInst *I) const; - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override; - bool preferInLoopReduction(RecurKind Kind, Type *Ty) const; + bool preferInLoopReduction(RecurKind Kind, Type *Ty) const override; - bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty) const; + bool preferPredicatedReductionSelect(unsigned Opcode, + Type *Ty) const override; - bool shouldExpandReduction(const IntrinsicInst *II) const { return false; } + bool shouldExpandReduction(const IntrinsicInst *II) const override { + return false; + } InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + InstructionCost + getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; InstructionCost getCmpSelInstrCost( unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; + Value *Op1) const override; InstructionCost getAddressComputationCost(Type *Val, ScalarEvolution *SE, - const SCEV *Ptr) const; + const SCEV *Ptr) const override; InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + const Instruction *CxtI = nullptr) const override; InstructionCost getMemoryOpCost( unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; - InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, - Align Alignment, unsigned AddressSpace, - TTI::TargetCostKind CostKind) const; + InstructionCost + getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind) const override; InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond = false, bool UseMaskForGaps = false) const; + bool UseMaskForCond = false, bool UseMaskForGaps = false) const override; - InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, - const Value *Ptr, bool VariableMask, - Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + InstructionCost + getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, + bool VariableMask, Align Alignment, + TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, std::optional FMF, - TTI::TargetCostKind CostKind) const; - InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, - Type *ResTy, VectorType *ValTy, - std::optional FMF, - TTI::TargetCostKind CostKind) const; - InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, - VectorType *ValTy, - TTI::TargetCostKind CostKind) const; - - InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, - FastMathFlags FMF, - TTI::TargetCostKind CostKind) const; - - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; + InstructionCost + getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, + VectorType *ValTy, std::optional FMF, + TTI::TargetCostKind CostKind) const override; + InstructionCost + getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *ValTy, + TTI::TargetCostKind CostKind) const override; + + InstructionCost + getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, + TTI::TargetCostKind CostKind) const override; + + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override; /// getScalingFactorCost - Return the cost of the scaling used in /// addressing mode represented by AM. @@ -308,24 +316,25 @@ class ARMTTIImpl : public BasicTTIImplBase { /// If the AM is not supported, the return value is an invalid cost. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, - int64_t Scale, unsigned AddrSpace) const; + int64_t Scale, + unsigned AddrSpace) const override; bool maybeLoweredToCall(Instruction &I) const; - bool isLoweredToCall(const Function *F) const; + bool isLoweredToCall(const Function *F) const override; bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, - HardwareLoopInfo &HWLoopInfo) const; - bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const; + HardwareLoopInfo &HWLoopInfo) const override; + bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const override; void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; TailFoldingStyle - getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const; + getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; - bool shouldBuildLookupTablesForConstant(Constant *C) const { + TTI::PeelingPreferences &PP) const override; + bool shouldBuildLookupTablesForConstant(Constant *C) const override { // In the ROPI and RWPI relocation models we can't have pointers to global // variables or functions in constant data, so don't convert switches to // lookup tables if any of the values would need relocation. @@ -335,12 +344,13 @@ class ARMTTIImpl : public BasicTTIImplBase { return true; } - bool hasArmWideBranch(bool Thumb) const; + bool hasArmWideBranch(bool Thumb) const override; bool isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &Ops) const; + SmallVectorImpl &Ops) const override; - unsigned getNumBytesToPadGlobalArray(unsigned Size, Type *ArrayType) const; + unsigned getNumBytesToPadGlobalArray(unsigned Size, + Type *ArrayType) const override; /// @} }; diff --git a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h index 9667f7e8f9e64..e94497896f681 100644 --- a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h +++ b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h @@ -38,7 +38,7 @@ class BPFTTIImpl : public BasicTTIImplBase { TLI(ST->getTargetLowering()) {} InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { if (Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) return TTI::TCC_Free; @@ -50,7 +50,7 @@ class BPFTTIImpl : public BasicTTIImplBase { TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - const llvm::Instruction *I = nullptr) const { + const llvm::Instruction *I = nullptr) const override { if (Opcode == Instruction::Select) return SCEVCheapExpansionBudget.getValue(); @@ -63,7 +63,7 @@ class BPFTTIImpl : public BasicTTIImplBase { TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const { + const Instruction *CxtI = nullptr) const override { int ISD = TLI->InstructionOpcodeToISD(Opcode); if (ISD == ISD::ADD && CostKind == TTI::TCK_RecipThroughput) return SCEVCheapExpansionBudget.getValue() + 1; @@ -72,18 +72,15 @@ class BPFTTIImpl : public BasicTTIImplBase { Op2Info); } - TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, - bool IsZeroCmp) const { + TTI::MemCmpExpansionOptions + enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override { TTI::MemCmpExpansionOptions Options; Options.LoadSizes = {8, 4, 2, 1}; Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); return Options; } - unsigned getMaxNumArgs() const { - return 5; - } - + unsigned getMaxNumArgs() const override { return 5; } }; } // end namespace llvm diff --git a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h index 170274c7aa32d..9f344d7d52ba0 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h +++ b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h @@ -33,12 +33,12 @@ class DirectXTTIImpl : public BasicTTIImplBase { explicit DirectXTTIImpl(const DirectXTargetMachine *TM, const Function &F) : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} - unsigned getMinVectorRegisterBitWidth() const { return 32; } - bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const; + unsigned getMinVectorRegisterBitWidth() const override { return 32; } + bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const override; bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, - unsigned ScalarOpdIdx) const; + unsigned ScalarOpdIdx) const override; bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, - int OpdIdx) const; + int OpdIdx) const override; }; } // namespace llvm diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index b9dc41b6f4fe1..6bcdd58ed5d4f 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -58,19 +58,20 @@ class HexagonTTIImpl : public BasicTTIImplBase { /// \name Scalar TTI Implementations /// @{ - TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const; + TTI::PopcntSupportKind + getPopcntSupport(unsigned IntTyWidthInBit) const override; // The Hexagon target can unroll loops with run-time trip counts. void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; + TTI::PeelingPreferences &PP) const override; /// Bias LSR towards creating post-increment opportunities. TTI::AddressingModeKind - getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const; + getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const override; // L1 cache prefetch. unsigned getPrefetchDistance() const override; @@ -81,94 +82,101 @@ class HexagonTTIImpl : public BasicTTIImplBase { /// \name Vector TTI Implementations /// @{ - unsigned getNumberOfRegisters(unsigned ClassID) const; - unsigned getMaxInterleaveFactor(ElementCount VF) const; - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; - unsigned getMinVectorRegisterBitWidth() const; - ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const; + unsigned getNumberOfRegisters(unsigned ClassID) const override; + unsigned getMaxInterleaveFactor(ElementCount VF) const override; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override; + unsigned getMinVectorRegisterBitWidth() const override; + ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const override; - bool - shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const { + bool shouldMaximizeVectorBandwidth( + TargetTransformInfo::RegisterKind K) const override { return true; } - bool supportsEfficientVectorElementLoadStore() const { return false; } - bool hasBranchDivergence(const Function *F = nullptr) const { return false; } - bool enableAggressiveInterleaving(bool LoopHasReductions) const { + bool supportsEfficientVectorElementLoadStore() const override { return false; } - bool prefersVectorizedAddressing() const { return false; } - bool enableInterleavedAccessVectorization() const { return true; } + bool hasBranchDivergence(const Function *F = nullptr) const override { + return false; + } + bool enableAggressiveInterleaving(bool LoopHasReductions) const override { + return false; + } + bool prefersVectorizedAddressing() const override { return false; } + bool enableInterleavedAccessVectorization() const override { return true; } InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef Tys, - TTI::TargetCostKind CostKind) const; - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override; InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *SE, - const SCEV *S) const; + const SCEV *S) const override; InstructionCost getMemoryOpCost( unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; - InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, - Align Alignment, unsigned AddressSpace, - TTI::TargetCostKind CostKind) const; - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + const Instruction *I = nullptr) const override; + InstructionCost + getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind) const override; + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override; InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, - const Instruction *I) const; + const Instruction *I) const override; InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond = false, bool UseMaskForGaps = false) const; + bool UseMaskForCond = false, bool UseMaskForGaps = false) const override; InstructionCost getCmpSelInstrCost( unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *CxtI = nullptr) const override; + InstructionCost + getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; + Value *Op1) const override; - InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const { + InstructionCost + getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override { return 1; } bool isLegalMaskedStore(Type *DataType, Align Alignment, - unsigned AddressSpace) const; + unsigned AddressSpace) const override; bool isLegalMaskedLoad(Type *DataType, Align Alignment, - unsigned AddressSpace) const; + unsigned AddressSpace) const override; /// @} - InstructionCost getInstructionCost(const User *U, - ArrayRef Operands, - TTI::TargetCostKind CostKind) const; + InstructionCost + getInstructionCost(const User *U, ArrayRef Operands, + TTI::TargetCostKind CostKind) const override; // Hexagon specific decision to generate a lookup table. - bool shouldBuildLookupTables() const; + bool shouldBuildLookupTables() const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h index ad7e561426395..3c005cd5bdb36 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h +++ b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h @@ -41,17 +41,17 @@ class LanaiTTIImpl : public BasicTTIImplBase { : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} - bool shouldBuildLookupTables() const { return false; } + bool shouldBuildLookupTables() const override { return false; } TargetTransformInfo::PopcntSupportKind - getPopcntSupport(unsigned TyWidth) const { + getPopcntSupport(unsigned TyWidth) const override { if (TyWidth == 32) return TTI::PSK_FastHardware; return TTI::PSK_Software; } InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const { + TTI::TargetCostKind CostKind) const override { assert(Ty->isIntegerTy()); unsigned BitSize = Ty->getPrimitiveSizeInBits(); // There is no cost model for constants with a bit size of 0. Return @@ -78,16 +78,16 @@ class LanaiTTIImpl : public BasicTTIImplBase { return 4 * TTI::TCC_Basic; } - InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, - const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind, - Instruction *Inst = nullptr) const { + InstructionCost + getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, + TTI::TargetCostKind CostKind, + Instruction *Inst = nullptr) const override { return getIntImmCost(Imm, Ty, CostKind); } - InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, - const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const { + InstructionCost + getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty, TTI::TargetCostKind CostKind) const override { return getIntImmCost(Imm, Ty, CostKind); } @@ -96,7 +96,7 @@ class LanaiTTIImpl : public BasicTTIImplBase { TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const { + const Instruction *CxtI = nullptr) const override { int ISD = TLI->InstructionOpcodeToISD(Opcode); switch (ISD) { diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h index 26d59c3e53a3e..fdf57933cfdda 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h +++ b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h @@ -40,12 +40,14 @@ class LoongArchTTIImpl : public BasicTTIImplBase { : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; - unsigned getNumberOfRegisters(unsigned ClassID) const; - unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const; - unsigned getMaxInterleaveFactor(ElementCount VF) const; - const char *getRegisterClassName(unsigned ClassID) const; - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override; + unsigned getNumberOfRegisters(unsigned ClassID) const override; + unsigned getRegisterClassForType(bool Vector, + Type *Ty = nullptr) const override; + unsigned getMaxInterleaveFactor(ElementCount VF) const override; + const char *getRegisterClassName(unsigned ClassID) const override; + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override; unsigned getCacheLineSize() const override; unsigned getPrefetchDistance() const override; diff --git a/llvm/lib/Target/Mips/MipsTargetTransformInfo.h b/llvm/lib/Target/Mips/MipsTargetTransformInfo.h index cf3f873fd0cb0..5e3884cd80161 100644 --- a/llvm/lib/Target/Mips/MipsTargetTransformInfo.h +++ b/llvm/lib/Target/Mips/MipsTargetTransformInfo.h @@ -32,10 +32,10 @@ class MipsTTIImpl : public BasicTTIImplBase { : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} - bool hasDivRemOp(Type *DataType, bool IsSigned) const; + bool hasDivRemOp(Type *DataType, bool IsSigned) const override; bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, - const TargetTransformInfo::LSRCost &C2) const; + const TargetTransformInfo::LSRCost &C2) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h index b57efe8360d4e..324e4127e1013 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h @@ -42,30 +42,33 @@ class NVPTXTTIImpl : public BasicTTIImplBase { : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl()), TLI(ST->getTargetLowering()) {} - bool hasBranchDivergence(const Function *F = nullptr) const { return true; } + bool hasBranchDivergence(const Function *F = nullptr) const override { + return true; + } - bool isSourceOfDivergence(const Value *V) const; + bool isSourceOfDivergence(const Value *V) const override; - unsigned getFlatAddressSpace() const { + unsigned getFlatAddressSpace() const override { return AddressSpace::ADDRESS_SPACE_GENERIC; } - bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const { + bool + canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override { return AS != AddressSpace::ADDRESS_SPACE_SHARED && AS != AddressSpace::ADDRESS_SPACE_LOCAL && AS != ADDRESS_SPACE_PARAM; } - std::optional instCombineIntrinsic(InstCombiner &IC, - IntrinsicInst &II) const; + std::optional + instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override; // Loads and stores can be vectorized if the alignment is at least as big as // the load/store we want to vectorize. bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const { + unsigned AddrSpace) const override { return Alignment >= ChainSizeInBytes; } bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const { + unsigned AddrSpace) const override { return isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, AddrSpace); } @@ -74,43 +77,42 @@ class NVPTXTTIImpl : public BasicTTIImplBase { // vectorizers but disables heuristics based on the number of registers. // FIXME: Return a more reasonable number, while keeping an eye on // LoopVectorizer's unrolling heuristics. - unsigned getNumberOfRegisters(unsigned ClassID) const { return 1; } + unsigned getNumberOfRegisters(unsigned ClassID) const override { return 1; } // Only <2 x half> should be vectorized, so always return 32 for the vector // register size. - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override { return TypeSize::getFixed(32); } - unsigned getMinVectorRegisterBitWidth() const { return 32; } + unsigned getMinVectorRegisterBitWidth() const override { return 32; } // We don't want to prevent inlining because of target-cpu and -features // attributes that were added to newer versions of LLVM/Clang: There are // no incompatible functions in PTX, ptxas will throw errors in such cases. bool areInlineCompatible(const Function *Caller, - const Function *Callee) const { + const Function *Callee) const override { return true; } // Increase the inlining cost threshold by a factor of 11, reflecting that // calls are particularly expensive in NVPTX. - unsigned getInliningThresholdMultiplier() const { return 11; } + unsigned getInliningThresholdMultiplier() const override { return 11; } - InstructionCost getInstructionCost(const User *U, - ArrayRef Operands, - TTI::TargetCostKind CostKind) const; + InstructionCost + getInstructionCost(const User *U, ArrayRef Operands, + TTI::TargetCostKind CostKind) const override; InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + const Instruction *CxtI = nullptr) const override; - InstructionCost getScalarizationOverhead(VectorType *InTy, - const APInt &DemandedElts, - bool Insert, bool Extract, - TTI::TargetCostKind CostKind, - ArrayRef VL = {}) const { + InstructionCost getScalarizationOverhead( + VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract, + TTI::TargetCostKind CostKind, ArrayRef VL = {}) const override { if (!InTy->getElementCount().isFixed()) return InstructionCost::getInvalid(); @@ -144,12 +146,12 @@ class NVPTXTTIImpl : public BasicTTIImplBase { void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; + TTI::PeelingPreferences &PP) const override; - bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const { + bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const override { // Volatile loads/stores are only supported for shared and global address // spaces, or for generic AS that maps to them. if (!(AddrSpace == llvm::ADDRESS_SPACE_GENERIC || @@ -167,15 +169,15 @@ class NVPTXTTIImpl : public BasicTTIImplBase { } bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes, - Intrinsic::ID IID) const; + Intrinsic::ID IID) const override; Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, - Value *NewV) const; - unsigned getAssumedAddrSpace(const Value *V) const; + Value *NewV) const override; + unsigned getAssumedAddrSpace(const Value *V) const override; void collectKernelLaunchBounds( const Function &F, - SmallVectorImpl> &LB) const; + SmallVectorImpl> &LB) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h index d5428c7e4e24c..c8eda22f847ad 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -40,65 +40,68 @@ class PPCTTIImpl : public BasicTTIImplBase { : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} - std::optional instCombineIntrinsic(InstCombiner & IC, - IntrinsicInst & II) const; + std::optional + instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override; /// \name Scalar TTI Implementations /// @{ using BaseT::getIntImmCost; InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, - Instruction *Inst = nullptr) const; - InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, - const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + Instruction *Inst = nullptr) const override; + InstructionCost + getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty, TTI::TargetCostKind CostKind) const override; - InstructionCost getInstructionCost(const User *U, - ArrayRef Operands, - TTI::TargetCostKind CostKind) const; + InstructionCost + getInstructionCost(const User *U, ArrayRef Operands, + TTI::TargetCostKind CostKind) const override; - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const; + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override; bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, - HardwareLoopInfo &HWLoopInfo) const; + HardwareLoopInfo &HWLoopInfo) const override; bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, - TargetLibraryInfo *LibInfo) const; - bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const; + TargetLibraryInfo *LibInfo) const override; + bool getTgtMemIntrinsic(IntrinsicInst *Inst, + MemIntrinsicInfo &Info) const override; void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; + TTI::PeelingPreferences &PP) const override; bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, - const TargetTransformInfo::LSRCost &C2) const; - bool isNumRegsMajorCostOfLSR() const; - bool shouldBuildRelLookupTables() const; + const TargetTransformInfo::LSRCost &C2) const override; + bool isNumRegsMajorCostOfLSR() const override; + bool shouldBuildRelLookupTables() const override; /// @} /// \name Vector TTI Implementations /// @{ - bool useColdCCForColdCall(Function &F) const; - bool enableAggressiveInterleaving(bool LoopHasReductions) const; - TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, - bool IsZeroCmp) const; - bool enableInterleavedAccessVectorization() const; + bool useColdCCForColdCall(Function &F) const override; + bool enableAggressiveInterleaving(bool LoopHasReductions) const override; + TTI::MemCmpExpansionOptions + enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override; + bool enableInterleavedAccessVectorization() const override; enum PPCRegisterClass { GPRRC, FPRRC, VRRC, VSXRC }; - unsigned getNumberOfRegisters(unsigned ClassID) const; - unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const; - const char* getRegisterClassName(unsigned ClassID) const; - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; + unsigned getNumberOfRegisters(unsigned ClassID) const override; + unsigned getRegisterClassForType(bool Vector, + Type *Ty = nullptr) const override; + const char *getRegisterClassName(unsigned ClassID) const override; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override; unsigned getCacheLineSize() const override; unsigned getPrefetchDistance() const override; - unsigned getMaxInterleaveFactor(ElementCount VF) const; + unsigned getMaxInterleaveFactor(ElementCount VF) const override; InstructionCost vectorCostAdjustmentFactor(unsigned Opcode, Type *Ty1, Type *Ty2) const; InstructionCost getArithmeticInstrCost( @@ -106,52 +109,52 @@ class PPCTTIImpl : public BasicTTIImplBase { TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *CxtI = nullptr) const override; + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override; + InstructionCost + getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; InstructionCost getCmpSelInstrCost( unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; + Value *Op1) const override; InstructionCost getMemoryOpCost( unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond = false, bool UseMaskForGaps = false) const; - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const; + bool UseMaskForCond = false, bool UseMaskForGaps = false) const override; + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override; bool areInlineCompatible(const Function *Caller, - const Function *Callee) const; + const Function *Callee) const override; bool areTypesABICompatible(const Function *Caller, const Function *Callee, - const ArrayRef &Types) const; + const ArrayRef &Types) const override; bool hasActiveVectorLength(unsigned Opcode, Type *DataType, - Align Alignment) const; - InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, - unsigned AddressSpace, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; - bool supportsTailCallFor(const CallBase *CB) const; + Align Alignment) const override; + InstructionCost + getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, + unsigned AddressSpace, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; + bool supportsTailCallFor(const CallBase *CB) const override; private: // The following constant is used for estimating costs on power9. diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 43a367b3d3e5a..9a75431cee831 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -79,14 +79,14 @@ class RISCVTTIImpl : public BasicTTIImplBase { TTI::TargetCostKind CostKind) const; InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, - Instruction *Inst = nullptr) const; - InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, - const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + Instruction *Inst = nullptr) const override; + InstructionCost + getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty, TTI::TargetCostKind CostKind) const override; /// \name EVL Support for predicated vectorization. /// Whether the target supports the %evl parameter of VP intrinsic efficiently @@ -102,148 +102,152 @@ class RISCVTTIImpl : public BasicTTIImplBase { /// \param Alignment the alignment for memory access operation checked for /// predicated version support. bool hasActiveVectorLength(unsigned Opcode, Type *DataType, - Align Alignment) const; + Align Alignment) const override; TargetTransformInfo::PopcntSupportKind - getPopcntSupport(unsigned TyWidth) const; + getPopcntSupport(unsigned TyWidth) const override; - bool shouldExpandReduction(const IntrinsicInst *II) const; - bool supportsScalableVectors() const { return ST->hasVInstructions(); } - bool enableOrderedReductions() const { return true; } - bool enableScalableVectorization() const { return ST->hasVInstructions(); } + bool shouldExpandReduction(const IntrinsicInst *II) const override; + bool supportsScalableVectors() const override { + return ST->hasVInstructions(); + } + bool enableOrderedReductions() const override { return true; } + bool enableScalableVectorization() const override { + return ST->hasVInstructions(); + } TailFoldingStyle - getPreferredTailFoldingStyle(bool IVUpdateMayOverflow) const { + getPreferredTailFoldingStyle(bool IVUpdateMayOverflow) const override { return ST->hasVInstructions() ? TailFoldingStyle::Data : TailFoldingStyle::DataWithoutLaneMask; } - std::optional getMaxVScale() const; - std::optional getVScaleForTuning() const; + std::optional getMaxVScale() const override; + std::optional getVScaleForTuning() const override; - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override; - unsigned getRegUsageForType(Type *Ty) const; + unsigned getRegUsageForType(Type *Ty) const override; - unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const; + unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override; - bool preferAlternateOpcodeVectorization() const { return false; } + bool preferAlternateOpcodeVectorization() const override { return false; } - bool preferEpilogueVectorization() const { + bool preferEpilogueVectorization() const override { // Epilogue vectorization is usually unprofitable - tail folding or // a smaller VF would have been better. This a blunt hammer - we // should re-examine this once vectorization is better tuned. return false; } - InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, - Align Alignment, unsigned AddressSpace, - TTI::TargetCostKind CostKind) const; + InstructionCost + getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind) const override; - InstructionCost getPointersChainCost(ArrayRef Ptrs, - const Value *Base, - const TTI::PointersChainInfo &Info, - Type *AccessTy, - TTI::TargetCostKind CostKind) const; + InstructionCost + getPointersChainCost(ArrayRef Ptrs, const Value *Base, + const TTI::PointersChainInfo &Info, Type *AccessTy, + TTI::TargetCostKind CostKind) const override; void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; + TTI::PeelingPreferences &PP) const override; - unsigned getMinVectorRegisterBitWidth() const { + unsigned getMinVectorRegisterBitWidth() const override { return ST->useRVVForFixedLengthVectors() ? 16 : 0; } - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override; - InstructionCost getScalarizationOverhead(VectorType *Ty, - const APInt &DemandedElts, - bool Insert, bool Extract, - TTI::TargetCostKind CostKind, - ArrayRef VL = {}) const; + InstructionCost getScalarizationOverhead( + VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, + TTI::TargetCostKind CostKind, ArrayRef VL = {}) const override; - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const; + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override; InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond = false, bool UseMaskForGaps = false) const; + bool UseMaskForCond = false, bool UseMaskForGaps = false) const override; InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, - const Instruction *I) const; + const Instruction *I) const override; InstructionCost getExpandCompressMemoryOpCost(unsigned Opcode, Type *Src, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, - const Instruction *I) const; + const Instruction *I) const override; - InstructionCost getCostOfKeepingLiveOverCall(ArrayRef Tys) const; + InstructionCost + getCostOfKeepingLiveOverCall(ArrayRef Tys) const override; - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + InstructionCost + getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; - InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, - FastMathFlags FMF, - TTI::TargetCostKind CostKind) const; + InstructionCost + getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, + TTI::TargetCostKind CostKind) const override; InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional FMF, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; - InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, - Type *ResTy, VectorType *ValTy, - std::optional FMF, - TTI::TargetCostKind CostKind) const; + InstructionCost + getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, + VectorType *ValTy, std::optional FMF, + TTI::TargetCostKind CostKind) const override; InstructionCost getMemoryOpCost( unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpdInfo = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; InstructionCost getCmpSelInstrCost( unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; + Value *Op1) const override; InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + const Instruction *CxtI = nullptr) const override; - bool isElementTypeLegalForScalableVector(Type *Ty) const { + bool isElementTypeLegalForScalableVector(Type *Ty) const override { return TLI->isLegalElementTypeForRVV(TLI->getValueType(DL, Ty)); } @@ -265,11 +269,11 @@ class RISCVTTIImpl : public BasicTTIImplBase { } bool isLegalMaskedLoad(Type *DataType, Align Alignment, - unsigned /*AddressSpace*/) const { + unsigned /*AddressSpace*/) const override { return isLegalMaskedLoadStore(DataType, Alignment); } bool isLegalMaskedStore(Type *DataType, Align Alignment, - unsigned /*AddressSpace*/) const { + unsigned /*AddressSpace*/) const override { return isLegalMaskedLoadStore(DataType, Alignment); } @@ -296,46 +300,49 @@ class RISCVTTIImpl : public BasicTTIImplBase { return TLI->isLegalElementTypeForRVV(ElemType); } - bool isLegalMaskedGather(Type *DataType, Align Alignment) const { + bool isLegalMaskedGather(Type *DataType, Align Alignment) const override { return isLegalMaskedGatherScatter(DataType, Alignment); } - bool isLegalMaskedScatter(Type *DataType, Align Alignment) const { + bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override { return isLegalMaskedGatherScatter(DataType, Alignment); } - bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) const { + bool forceScalarizeMaskedGather(VectorType *VTy, + Align Alignment) const override { // Scalarize masked gather for RV64 if EEW=64 indices aren't supported. return ST->is64Bit() && !ST->hasVInstructionsI64(); } - bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment) const { + bool forceScalarizeMaskedScatter(VectorType *VTy, + Align Alignment) const override { // Scalarize masked scatter for RV64 if EEW=64 indices aren't supported. return ST->is64Bit() && !ST->hasVInstructionsI64(); } - bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const { + bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const override { EVT DataTypeVT = TLI->getValueType(DL, DataType); return TLI->isLegalStridedLoadStore(DataTypeVT, Alignment); } bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, - Align Alignment, unsigned AddrSpace) const { + Align Alignment, + unsigned AddrSpace) const override { return TLI->isLegalInterleavedAccessType(VTy, Factor, Alignment, AddrSpace, DL); } - bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const; + bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const override; - bool isLegalMaskedCompressStore(Type *DataTy, Align Alignment) const; + bool isLegalMaskedCompressStore(Type *DataTy, Align Alignment) const override; - bool isVScaleKnownToBeAPowerOfTwo() const { + bool isVScaleKnownToBeAPowerOfTwo() const override { return TLI->isVScaleKnownToBeAPowerOfTwo(); } /// \returns How the target needs this vector-predicated operation to be /// transformed. TargetTransformInfo::VPLegalization - getVPLegalizationStrategy(const VPIntrinsic &PI) const { + getVPLegalizationStrategy(const VPIntrinsic &PI) const override { using VPLegalization = TargetTransformInfo::VPLegalization; if (!ST->hasVInstructions() || (PI.getIntrinsicID() == Intrinsic::vp_reduce_mul && @@ -347,7 +354,7 @@ class RISCVTTIImpl : public BasicTTIImplBase { } bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, - ElementCount VF) const { + ElementCount VF) const override { if (!VF.isScalable()) return true; @@ -381,7 +388,7 @@ class RISCVTTIImpl : public BasicTTIImplBase { } } - unsigned getMaxInterleaveFactor(ElementCount VF) const { + unsigned getMaxInterleaveFactor(ElementCount VF) const override { // Don't interleave if the loop has been vectorized with scalable vectors. if (VF.isScalable()) return 1; @@ -390,12 +397,12 @@ class RISCVTTIImpl : public BasicTTIImplBase { return VF.isScalar() ? 1 : ST->getMaxInterleaveFactor(); } - bool enableInterleavedAccessVectorization() const { return true; } + bool enableInterleavedAccessVectorization() const override { return true; } - unsigned getMinTripCountTailFoldingThreshold() const; + unsigned getMinTripCountTailFoldingThreshold() const override; enum RISCVRegisterClass { GPRRC, FPRRC, VRRC }; - unsigned getNumberOfRegisters(unsigned ClassID) const { + unsigned getNumberOfRegisters(unsigned ClassID) const override { switch (ClassID) { case RISCVRegisterClass::GPRRC: // 31 = 32 GPR - x0 (zero register) @@ -415,10 +422,11 @@ class RISCVTTIImpl : public BasicTTIImplBase { llvm_unreachable("unknown register class"); } - TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, - ScalarEvolution *SE) const; + TTI::AddressingModeKind + getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const override; - unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const { + unsigned getRegisterClassForType(bool Vector, + Type *Ty = nullptr) const override { if (Vector) return RISCVRegisterClass::VRRC; if (!Ty) @@ -434,7 +442,7 @@ class RISCVTTIImpl : public BasicTTIImplBase { return RISCVRegisterClass::GPRRC; } - const char *getRegisterClassName(unsigned ClassID) const { + const char *getRegisterClassName(unsigned ClassID) const override { switch (ClassID) { case RISCVRegisterClass::GPRRC: return "RISCV::GPRRC"; @@ -447,11 +455,12 @@ class RISCVTTIImpl : public BasicTTIImplBase { } bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, - const TargetTransformInfo::LSRCost &C2) const; + const TargetTransformInfo::LSRCost &C2) const override; bool shouldConsiderAddressTypePromotion( - const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const; - std::optional getMinPageSize() const { return 4096; } + const Instruction &I, + bool &AllowPromotionWithoutCommonHeader) const override; + std::optional getMinPageSize() const override { return 4096; } /// Return true if the (vector) instruction I will be lowered to an /// instruction with a scalar splat operand for the given Operand number. bool canSplatOperand(Instruction *I, int Operand) const; @@ -460,10 +469,10 @@ class RISCVTTIImpl : public BasicTTIImplBase { bool canSplatOperand(unsigned Opcode, int Operand) const; bool isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &Ops) const; + SmallVectorImpl &Ops) const override; - TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, - bool IsZeroCmp) const; + TTI::MemCmpExpansionOptions + enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h b/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h index 5c919c2dd4024..dbc8a35dd21e9 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h +++ b/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h @@ -39,7 +39,7 @@ class SPIRVTTIImpl : public BasicTTIImplBase { : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const { + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override { // SPIR-V natively supports OpBitcount, per 3.53.14 in the spec, as such it // is reasonable to assume the Op is fast / preferable to the expanded loop. // Furthermore, this prevents information being lost if transforms are diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h index cb993b7b2df11..c83f8e2542470 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -40,41 +40,42 @@ class SystemZTTIImpl : public BasicTTIImplBase { /// \name Scalar TTI Implementations /// @{ - unsigned adjustInliningThreshold(const CallBase *CB) const; + unsigned adjustInliningThreshold(const CallBase *CB) const override; InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, - Instruction *Inst = nullptr) const; - InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, - const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + Instruction *Inst = nullptr) const override; + InstructionCost + getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty, TTI::TargetCostKind CostKind) const override; - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const; + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override; void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - TTI::PeelingPreferences &PP) const; + TTI::PeelingPreferences &PP) const override; bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, - const TargetTransformInfo::LSRCost &C2) const; + const TargetTransformInfo::LSRCost &C2) const override; bool areInlineCompatible(const Function *Caller, - const Function *Callee) const; + const Function *Callee) const override; /// @} /// \name Vector TTI Implementations /// @{ - unsigned getNumberOfRegisters(unsigned ClassID) const; - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; + unsigned getNumberOfRegisters(unsigned ClassID) const override; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override; unsigned getCacheLineSize() const override { return 256; } unsigned getPrefetchDistance() const override { return 4500; } @@ -84,73 +85,71 @@ class SystemZTTIImpl : public BasicTTIImplBase { bool HasCall) const override; bool enableWritePrefetching() const override { return true; } - bool hasDivRemOp(Type *DataType, bool IsSigned) const; - bool prefersVectorizedAddressing() const { return false; } - bool LSRWithInstrQueries() const { return true; } - InstructionCost getScalarizationOverhead(VectorType *Ty, - const APInt &DemandedElts, - bool Insert, bool Extract, - TTI::TargetCostKind CostKind, - ArrayRef VL = {}) const; - bool supportsEfficientVectorElementLoadStore() const { return true; } - bool enableInterleavedAccessVectorization() const { return true; } + bool hasDivRemOp(Type *DataType, bool IsSigned) const override; + bool prefersVectorizedAddressing() const override { return false; } + bool LSRWithInstrQueries() const override { return true; } + InstructionCost getScalarizationOverhead( + VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, + TTI::TargetCostKind CostKind, ArrayRef VL = {}) const override; + bool supportsEfficientVectorElementLoadStore() const override { return true; } + bool enableInterleavedAccessVectorization() const override { return true; } InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + const Instruction *CxtI = nullptr) const override; + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override; unsigned getVectorTruncCost(Type *SrcTy, Type *DstTy) const; unsigned getVectorBitmaskConversionCost(Type *SrcTy, Type *DstTy) const; unsigned getBoolVecToIntConversionCost(unsigned Opcode, Type *Dst, const Instruction *I) const; - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + InstructionCost + getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; InstructionCost getCmpSelInstrCost( unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; + Value *Op1) const override; bool isFoldableLoad(const LoadInst *Ld, const Instruction *&FoldedValue) const; InstructionCost getMemoryOpCost( unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond = false, bool UseMaskForGaps = false) const; + bool UseMaskForCond = false, bool UseMaskForGaps = false) const override; InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional FMF, - TTI::TargetCostKind CostKind) const; - InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, - FastMathFlags FMF, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; + InstructionCost + getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, + TTI::TargetCostKind CostKind) const override; - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const; + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override; - bool shouldExpandReduction(const IntrinsicInst *II) const; + bool shouldExpandReduction(const IntrinsicInst *II) const override; /// @} }; diff --git a/llvm/lib/Target/VE/VETargetTransformInfo.h b/llvm/lib/Target/VE/VETargetTransformInfo.h index 93092ae7221b9..d27a66bdd6bd0 100644 --- a/llvm/lib/Target/VE/VETargetTransformInfo.h +++ b/llvm/lib/Target/VE/VETargetTransformInfo.h @@ -85,7 +85,7 @@ class VETTIImpl : public BasicTTIImplBase { : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} - unsigned getNumberOfRegisters(unsigned ClassID) const { + unsigned getNumberOfRegisters(unsigned ClassID) const override { bool VectorRegs = (ClassID == 1); if (VectorRegs) { // TODO report vregs once vector isel is stable. @@ -95,7 +95,8 @@ class VETTIImpl : public BasicTTIImplBase { return 64; } - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override { switch (K) { case TargetTransformInfo::RGK_Scalar: return TypeSize::getFixed(64); @@ -112,17 +113,17 @@ class VETTIImpl : public BasicTTIImplBase { /// \returns How the target needs this vector-predicated operation to be /// transformed. TargetTransformInfo::VPLegalization - getVPLegalizationStrategy(const VPIntrinsic &PI) const { + getVPLegalizationStrategy(const VPIntrinsic &PI) const override { using VPLegalization = TargetTransformInfo::VPLegalization; return VPLegalization(VPLegalization::Legal, VPLegalization::Legal); } - unsigned getMinVectorRegisterBitWidth() const { + unsigned getMinVectorRegisterBitWidth() const override { // TODO report vregs once vector isel is stable. return 0; } - bool shouldBuildRelLookupTables() const { + bool shouldBuildRelLookupTables() const override { // NEC nld doesn't support relative lookup tables. It shows following // errors. So, we disable it at the moment. // /opt/nec/ve/bin/nld: src/CMakeFiles/cxxabi_shared.dir/cxa_demangle.cpp @@ -134,22 +135,22 @@ class VETTIImpl : public BasicTTIImplBase { // Load & Store { bool isLegalMaskedLoad(Type *DataType, Align Alignment, - unsigned /*AddressSpace*/) const { + unsigned /*AddressSpace*/) const override { return isVectorLaneType(*getLaneType(DataType)); } bool isLegalMaskedStore(Type *DataType, Align Alignment, - unsigned /*AddressSpace*/) const { + unsigned /*AddressSpace*/) const override { return isVectorLaneType(*getLaneType(DataType)); } - bool isLegalMaskedGather(Type *DataType, Align Alignment) const { + bool isLegalMaskedGather(Type *DataType, Align Alignment) const override { return isVectorLaneType(*getLaneType(DataType)); }; - bool isLegalMaskedScatter(Type *DataType, Align Alignment) const { + bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override { return isVectorLaneType(*getLaneType(DataType)); } // } Load & Store - bool shouldExpandReduction(const IntrinsicInst *II) const { + bool shouldExpandReduction(const IntrinsicInst *II) const override { if (!enableVPU()) return true; return !isSupportedReduction(II->getIntrinsicID()); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h index cb9adf7d1d5e9..02b4c7c442aaf 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h @@ -46,55 +46,55 @@ class WebAssemblyTTIImpl final : public BasicTTIImplBase { // TODO: Implement more Scalar TTI for WebAssembly - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const; + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override; void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const; + OptimizationRemarkEmitter *ORE) const override; /// @} /// \name Vector TTI Implementations /// @{ - bool enableInterleavedAccessVectorization() const { return true; } + bool enableInterleavedAccessVectorization() const override { return true; } - unsigned getNumberOfRegisters(unsigned ClassID) const; - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; + unsigned getNumberOfRegisters(unsigned ClassID) const override; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override; InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + const Instruction *CxtI = nullptr) const override; - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + InstructionCost + getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; InstructionCost getMemoryOpCost( unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; - InstructionCost - getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, - Type *AccumType, ElementCount VF, - TTI::PartialReductionExtendKind OpAExtend, - TTI::PartialReductionExtendKind OpBExtend, - std::optional BinOp = std::nullopt) const; + Value *Op1) const override; + InstructionCost getPartialReductionCost( + unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, + ElementCount VF, TTI::PartialReductionExtendKind OpAExtend, + TTI::PartialReductionExtendKind OpBExtend, + std::optional BinOp = std::nullopt) const override; TTI::ReductionShuffle - getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const; + getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const override; - bool supportsTailCalls() const; + bool supportsTailCalls() const override; bool isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &Ops) const; + SmallVectorImpl &Ops) const override; /// @} }; diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index ef7b7e90eeb5a..64f552f7976ff 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -116,7 +116,7 @@ class X86TTIImpl : public BasicTTIImplBase { /// \name Scalar TTI Implementations /// @{ - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const; + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override; /// @} @@ -131,107 +131,106 @@ class X86TTIImpl : public BasicTTIImplBase { /// \name Vector TTI Implementations /// @{ - unsigned getNumberOfRegisters(unsigned ClassID) const; - bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const; - TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; - unsigned getLoadStoreVecRegBitWidth(unsigned AS) const; - unsigned getMaxInterleaveFactor(ElementCount VF) const; + unsigned getNumberOfRegisters(unsigned ClassID) const override; + bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const override; + TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override; + unsigned getLoadStoreVecRegBitWidth(unsigned AS) const override; + unsigned getMaxInterleaveFactor(ElementCount VF) const override; InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; + const Instruction *CxtI = nullptr) const override; InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, - TTI::TargetCostKind CostKind) const; - - InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, - VectorType *SubTp, - ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const; - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + TTI::TargetCostKind CostKind) const override; + + InstructionCost + getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args = {}, + const Instruction *CxtI = nullptr) const override; + InstructionCost + getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, + TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const override; InstructionCost getCmpSelInstrCost( unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, - Value *Op1) const; - InstructionCost getScalarizationOverhead(VectorType *Ty, - const APInt &DemandedElts, - bool Insert, bool Extract, - TTI::TargetCostKind CostKind, - ArrayRef VL = {}) const; - InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, - int VF, - const APInt &DemandedDstElts, - TTI::TargetCostKind CostKind) const; + Value *Op1) const override; + InstructionCost getScalarizationOverhead( + VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, + TTI::TargetCostKind CostKind, ArrayRef VL = {}) const override; + InstructionCost + getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, + const APInt &DemandedDstElts, + TTI::TargetCostKind CostKind) const override; InstructionCost getMemoryOpCost( unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None}, - const Instruction *I = nullptr) const; - InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, - Align Alignment, unsigned AddressSpace, - TTI::TargetCostKind CostKind) const; + const Instruction *I = nullptr) const override; + InstructionCost + getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind) const override; InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, - const Instruction *I) const; - InstructionCost getPointersChainCost(ArrayRef Ptrs, - const Value *Base, - const TTI::PointersChainInfo &Info, - Type *AccessTy, - TTI::TargetCostKind CostKind) const; + const Instruction *I) const override; + InstructionCost + getPointersChainCost(ArrayRef Ptrs, const Value *Base, + const TTI::PointersChainInfo &Info, Type *AccessTy, + TTI::TargetCostKind CostKind) const override; InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, - const SCEV *Ptr) const; + const SCEV *Ptr) const override; - std::optional instCombineIntrinsic(InstCombiner &IC, - IntrinsicInst &II) const; + std::optional + instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override; std::optional simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, - bool &KnownBitsComputed) const; + bool &KnownBitsComputed) const override; std::optional simplifyDemandedVectorEltsIntrinsic( InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function - SimplifyAndSetOp) const; + SimplifyAndSetOp) const override; - unsigned getAtomicMemIntrinsicMaxElementSize() const; + unsigned getAtomicMemIntrinsicMaxElementSize() const override; - InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const; + InstructionCost + getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, + TTI::TargetCostKind CostKind) const override; InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional FMF, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; InstructionCost getMinMaxCost(Intrinsic::ID IID, Type *Ty, TTI::TargetCostKind CostKind, FastMathFlags FMF) const; - InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, - FastMathFlags FMF, - TTI::TargetCostKind CostKind) const; + InstructionCost + getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, + TTI::TargetCostKind CostKind) const override; InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond = false, bool UseMaskForGaps = false) const; + bool UseMaskForCond = false, bool UseMaskForGaps = false) const override; InstructionCost getInterleavedMemoryOpCostAVX512( unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, @@ -241,18 +240,18 @@ class X86TTIImpl : public BasicTTIImplBase { InstructionCost getIntImmCost(int64_t) const; InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + TTI::TargetCostKind CostKind) const override; InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const; + const Instruction *I = nullptr) const override; InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, - Instruction *Inst = nullptr) const; - InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, - const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const; + Instruction *Inst = nullptr) const override; + InstructionCost + getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty, TTI::TargetCostKind CostKind) const override; /// Return the cost of the scaling factor used in the addressing /// mode represented by AM for this target, for a load/store /// of the specified type. @@ -260,57 +259,62 @@ class X86TTIImpl : public BasicTTIImplBase { /// If the AM is not supported, it returns an invalid cost. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, - int64_t Scale, unsigned AddrSpace) const; + int64_t Scale, + unsigned AddrSpace) const override; bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, - const TargetTransformInfo::LSRCost &C2) const; - bool canMacroFuseCmp() const; + const TargetTransformInfo::LSRCost &C2) const override; + bool canMacroFuseCmp() const override; bool isLegalMaskedLoad(Type *DataType, Align Alignment, - unsigned AddressSpace) const; + unsigned AddressSpace) const override; bool isLegalMaskedStore(Type *DataType, Align Alignment, - unsigned AddressSpace) const; - bool isLegalNTLoad(Type *DataType, Align Alignment) const; - bool isLegalNTStore(Type *DataType, Align Alignment) const; - bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const; - bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) const; - bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment) const { + unsigned AddressSpace) const override; + bool isLegalNTLoad(Type *DataType, Align Alignment) const override; + bool isLegalNTStore(Type *DataType, Align Alignment) const override; + bool isLegalBroadcastLoad(Type *ElementTy, + ElementCount NumElements) const override; + bool forceScalarizeMaskedGather(VectorType *VTy, + Align Alignment) const override; + bool forceScalarizeMaskedScatter(VectorType *VTy, + Align Alignment) const override { return forceScalarizeMaskedGather(VTy, Alignment); } bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment) const; - bool isLegalMaskedGather(Type *DataType, Align Alignment) const; - bool isLegalMaskedScatter(Type *DataType, Align Alignment) const; - bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const; - bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const; + bool isLegalMaskedGather(Type *DataType, Align Alignment) const override; + bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override; + bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const override; + bool isLegalMaskedCompressStore(Type *DataType, + Align Alignment) const override; bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, - const SmallBitVector &OpcodeMask) const; - bool hasDivRemOp(Type *DataType, bool IsSigned) const; - bool isExpensiveToSpeculativelyExecute(const Instruction *I) const; - bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const; + const SmallBitVector &OpcodeMask) const override; + bool hasDivRemOp(Type *DataType, bool IsSigned) const override; + bool isExpensiveToSpeculativelyExecute(const Instruction *I) const override; + bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const override; bool areInlineCompatible(const Function *Caller, - const Function *Callee) const; + const Function *Callee) const override; bool areTypesABICompatible(const Function *Caller, const Function *Callee, - const ArrayRef &Type) const; + const ArrayRef &Type) const override; - uint64_t getMaxMemIntrinsicInlineSizeThreshold() const { + uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override { return ST->getMaxInlineSizeThreshold(); } - TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, - bool IsZeroCmp) const; - bool preferAlternateOpcodeVectorization() const { return false; } - bool prefersVectorizedAddressing() const; - bool supportsEfficientVectorElementLoadStore() const; - bool enableInterleavedAccessVectorization() const; + TTI::MemCmpExpansionOptions + enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override; + bool preferAlternateOpcodeVectorization() const override { return false; } + bool prefersVectorizedAddressing() const override; + bool supportsEfficientVectorElementLoadStore() const override; + bool enableInterleavedAccessVectorization() const override; - InstructionCost getBranchMispredictPenalty() const; + InstructionCost getBranchMispredictPenalty() const override; bool isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &Ops) const; + SmallVectorImpl &Ops) const override; - bool isVectorShiftByScalarCheap(Type *Ty) const; + bool isVectorShiftByScalarCheap(Type *Ty) const override; unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, - Type *ScalarValTy) const; + Type *ScalarValTy) const override; private: bool supportsGather() const; diff --git a/llvm/lib/Target/XCore/XCoreTargetTransformInfo.h b/llvm/lib/Target/XCore/XCoreTargetTransformInfo.h index 2f39884c1c917..1f1325e4ca3bc 100644 --- a/llvm/lib/Target/XCore/XCoreTargetTransformInfo.h +++ b/llvm/lib/Target/XCore/XCoreTargetTransformInfo.h @@ -40,7 +40,7 @@ class XCoreTTIImpl : public BasicTTIImplBase { : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl()), TLI(ST->getTargetLowering()) {} - unsigned getNumberOfRegisters(unsigned ClassID) const { + unsigned getNumberOfRegisters(unsigned ClassID) const override { bool Vector = (ClassID == 1); if (Vector) { return 0; From ead188b3db29b97b1523eecc572c958acf3104fc Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Tue, 22 Apr 2025 11:07:20 +0300 Subject: [PATCH 3/4] Remove TargetTransformInfo::Concept --- .../llvm/Analysis/TargetTransformInfo.h | 466 +----------- .../llvm/Analysis/TargetTransformInfoImpl.h | 718 +++++++++--------- llvm/lib/Analysis/TargetTransformInfo.cpp | 5 +- 3 files changed, 376 insertions(+), 813 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 118ecfb87ec80..76a77737394b8 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -210,15 +210,12 @@ struct TailFoldingInfo { class TargetTransformInfo; typedef TargetTransformInfo TTI; +class TargetTransformInfoImplBase; /// This pass provides access to the codegen interfaces that are needed /// for IR-level transformations. class TargetTransformInfo { public: - /// The abstract base class used to type erase specific TTI - /// implementations. - class Concept; - enum PartialReductionExtendKind { PR_None, PR_SignExtend, PR_ZeroExtend }; /// Get the kind of extension that an instruction represents. @@ -230,7 +227,8 @@ class TargetTransformInfo { /// /// This is used by targets to construct a TTI wrapping their target-specific /// implementation that encodes appropriate costs for their target. - explicit TargetTransformInfo(std::unique_ptr Impl); + explicit TargetTransformInfo( + std::unique_ptr Impl); /// Construct a baseline TTI object using a minimal implementation of /// the \c Concept API below. @@ -1919,463 +1917,7 @@ class TargetTransformInfo { SmallVectorImpl> &LB) const; private: - std::unique_ptr TTIImpl; -}; - -class TargetTransformInfo::Concept { -public: - virtual ~Concept() = 0; - virtual const DataLayout &getDataLayout() const = 0; - virtual InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, - ArrayRef Operands, - Type *AccessType, - TTI::TargetCostKind CostKind) const = 0; - virtual InstructionCost - getPointersChainCost(ArrayRef Ptrs, const Value *Base, - const TTI::PointersChainInfo &Info, Type *AccessTy, - TTI::TargetCostKind CostKind) const = 0; - virtual unsigned getInliningThresholdMultiplier() const = 0; - virtual unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const = 0; - virtual unsigned - getInliningCostBenefitAnalysisProfitableMultiplier() const = 0; - virtual int getInliningLastCallToStaticBonus() const = 0; - virtual unsigned adjustInliningThreshold(const CallBase *CB) const = 0; - virtual int getInlinerVectorBonusPercent() const = 0; - virtual unsigned getCallerAllocaCost(const CallBase *CB, - const AllocaInst *AI) const = 0; - virtual InstructionCost getMemcpyCost(const Instruction *I) const = 0; - virtual uint64_t getMaxMemIntrinsicInlineSizeThreshold() const = 0; - virtual unsigned - getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, - ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI) const = 0; - virtual InstructionCost getInstructionCost(const User *U, - ArrayRef Operands, - TargetCostKind CostKind) const = 0; - virtual BranchProbability getPredictableBranchThreshold() const = 0; - virtual InstructionCost getBranchMispredictPenalty() const = 0; - virtual bool hasBranchDivergence(const Function *F = nullptr) const = 0; - virtual bool isSourceOfDivergence(const Value *V) const = 0; - virtual bool isAlwaysUniform(const Value *V) const = 0; - virtual bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const = 0; - virtual bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const = 0; - virtual unsigned getFlatAddressSpace() const = 0; - virtual bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes, - Intrinsic::ID IID) const = 0; - virtual bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const = 0; - virtual bool - canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const = 0; - virtual unsigned getAssumedAddrSpace(const Value *V) const = 0; - virtual bool isSingleThreaded() const = 0; - virtual std::pair - getPredicatedAddrSpace(const Value *V) const = 0; - virtual Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, - Value *OldV, - Value *NewV) const = 0; - virtual bool isLoweredToCall(const Function *F) const = 0; - virtual void - getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, - OptimizationRemarkEmitter *ORE) const = 0; - virtual void getPeelingPreferences(Loop *L, ScalarEvolution &SE, - PeelingPreferences &PP) const = 0; - virtual bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, - AssumptionCache &AC, - TargetLibraryInfo *LibInfo, - HardwareLoopInfo &HWLoopInfo) const = 0; - virtual unsigned getEpilogueVectorizationMinVF() const = 0; - virtual bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const = 0; - virtual TailFoldingStyle - getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const = 0; - virtual std::optional - instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const = 0; - virtual std::optional - simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, - APInt DemandedMask, KnownBits &Known, - bool &KnownBitsComputed) const = 0; - virtual std::optional simplifyDemandedVectorEltsIntrinsic( - InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, - APInt &UndefElts2, APInt &UndefElts3, - std::function - SimplifyAndSetOp) const = 0; - virtual bool isLegalAddImmediate(int64_t Imm) const = 0; - virtual bool isLegalAddScalableImmediate(int64_t Imm) const = 0; - virtual bool isLegalICmpImmediate(int64_t Imm) const = 0; - virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, - int64_t Scale, unsigned AddrSpace, - Instruction *I, - int64_t ScalableOffset) const = 0; - virtual bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, - const TargetTransformInfo::LSRCost &C2) const = 0; - virtual bool isNumRegsMajorCostOfLSR() const = 0; - virtual bool shouldDropLSRSolutionIfLessProfitable() const = 0; - virtual bool isProfitableLSRChainElement(Instruction *I) const = 0; - virtual bool canMacroFuseCmp() const = 0; - virtual bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, - LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, - TargetLibraryInfo *LibInfo) const = 0; - virtual AddressingModeKind - getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const = 0; - virtual bool isLegalMaskedStore(Type *DataType, Align Alignment, - unsigned AddressSpace) const = 0; - virtual bool isLegalMaskedLoad(Type *DataType, Align Alignment, - unsigned AddressSpace) const = 0; - virtual bool isLegalNTStore(Type *DataType, Align Alignment) const = 0; - virtual bool isLegalNTLoad(Type *DataType, Align Alignment) const = 0; - virtual bool isLegalBroadcastLoad(Type *ElementTy, - ElementCount NumElements) const = 0; - virtual bool isLegalMaskedScatter(Type *DataType, Align Alignment) const = 0; - virtual bool isLegalMaskedGather(Type *DataType, Align Alignment) const = 0; - virtual bool forceScalarizeMaskedGather(VectorType *DataType, - Align Alignment) const = 0; - virtual bool forceScalarizeMaskedScatter(VectorType *DataType, - Align Alignment) const = 0; - virtual bool isLegalMaskedCompressStore(Type *DataType, - Align Alignment) const = 0; - virtual bool isLegalMaskedExpandLoad(Type *DataType, - Align Alignment) const = 0; - virtual bool isLegalStridedLoadStore(Type *DataType, - Align Alignment) const = 0; - virtual bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, - Align Alignment, - unsigned AddrSpace) const = 0; - - virtual bool isLegalMaskedVectorHistogram(Type *AddrType, - Type *DataType) const = 0; - virtual bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, - unsigned Opcode1, - const SmallBitVector &OpcodeMask) const = 0; - virtual bool enableOrderedReductions() const = 0; - virtual bool hasDivRemOp(Type *DataType, bool IsSigned) const = 0; - virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const = 0; - virtual bool prefersVectorizedAddressing() const = 0; - virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - StackOffset BaseOffset, - bool HasBaseReg, int64_t Scale, - unsigned AddrSpace) const = 0; - virtual bool LSRWithInstrQueries() const = 0; - virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const = 0; - virtual bool isProfitableToHoist(Instruction *I) const = 0; - virtual bool useAA() const = 0; - virtual bool isTypeLegal(Type *Ty) const = 0; - virtual unsigned getRegUsageForType(Type *Ty) const = 0; - virtual bool shouldBuildLookupTables() const = 0; - virtual bool shouldBuildLookupTablesForConstant(Constant *C) const = 0; - virtual bool shouldBuildRelLookupTables() const = 0; - virtual bool useColdCCForColdCall(Function &F) const = 0; - virtual bool - isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const = 0; - virtual bool - isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, - unsigned ScalarOpdIdx) const = 0; - virtual bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, - int OpdIdx) const = 0; - virtual bool - isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, - int RetIdx) const = 0; - virtual InstructionCost - getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, - bool Insert, bool Extract, TargetCostKind CostKind, - ArrayRef VL = {}) const = 0; - virtual InstructionCost - getOperandsScalarizationOverhead(ArrayRef Args, - ArrayRef Tys, - TargetCostKind CostKind) const = 0; - virtual bool supportsEfficientVectorElementLoadStore() const = 0; - virtual bool supportsTailCalls() const = 0; - virtual bool supportsTailCallFor(const CallBase *CB) const = 0; - virtual bool enableAggressiveInterleaving(bool LoopHasReductions) const = 0; - virtual MemCmpExpansionOptions - enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const = 0; - virtual bool enableSelectOptimize() const = 0; - virtual bool shouldTreatInstructionLikeSelect(const Instruction *I) const = 0; - virtual bool enableInterleavedAccessVectorization() const = 0; - virtual bool enableMaskedInterleavedAccessVectorization() const = 0; - virtual bool isFPVectorizationPotentiallyUnsafe() const = 0; - virtual bool allowsMisalignedMemoryAccesses(LLVMContext &Context, - unsigned BitWidth, - unsigned AddressSpace, - Align Alignment, - unsigned *Fast) const = 0; - virtual PopcntSupportKind - getPopcntSupport(unsigned IntTyWidthInBit) const = 0; - virtual bool haveFastSqrt(Type *Ty) const = 0; - virtual bool - isExpensiveToSpeculativelyExecute(const Instruction *I) const = 0; - virtual bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const = 0; - virtual InstructionCost getFPOpCost(Type *Ty) const = 0; - virtual InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, - const APInt &Imm, - Type *Ty) const = 0; - virtual InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TargetCostKind CostKind) const = 0; - virtual InstructionCost - getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, - TargetCostKind CostKind, - Instruction *Inst = nullptr) const = 0; - virtual InstructionCost - getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, - Type *Ty, TargetCostKind CostKind) const = 0; - virtual bool preferToKeepConstantsAttached(const Instruction &Inst, - const Function &Fn) const = 0; - virtual unsigned getNumberOfRegisters(unsigned ClassID) const = 0; - virtual bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const = 0; - virtual unsigned getRegisterClassForType(bool Vector, - Type *Ty = nullptr) const = 0; - virtual const char *getRegisterClassName(unsigned ClassID) const = 0; - virtual TypeSize getRegisterBitWidth(RegisterKind K) const = 0; - virtual unsigned getMinVectorRegisterBitWidth() const = 0; - virtual std::optional getMaxVScale() const = 0; - virtual std::optional getVScaleForTuning() const = 0; - virtual bool isVScaleKnownToBeAPowerOfTwo() const = 0; - virtual bool - shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const = 0; - virtual ElementCount getMinimumVF(unsigned ElemWidth, - bool IsScalable) const = 0; - virtual unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const = 0; - virtual unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, - Type *ScalarValTy) const = 0; - virtual bool shouldConsiderAddressTypePromotion( - const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const = 0; - virtual unsigned getCacheLineSize() const = 0; - virtual std::optional getCacheSize(CacheLevel Level) const = 0; - virtual std::optional getCacheAssociativity(CacheLevel Level) - const = 0; - virtual std::optional getMinPageSize() const = 0; - - /// \return How much before a load we should place the prefetch - /// instruction. This is currently measured in number of - /// instructions. - virtual unsigned getPrefetchDistance() const = 0; - - /// \return Some HW prefetchers can handle accesses up to a certain - /// constant stride. This is the minimum stride in bytes where it - /// makes sense to start adding SW prefetches. The default is 1, - /// i.e. prefetch with any stride. Sometimes prefetching is beneficial - /// even below the HW prefetcher limit, and the arguments provided are - /// meant to serve as a basis for deciding this for a particular loop. - virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, - unsigned NumStridedMemAccesses, - unsigned NumPrefetches, - bool HasCall) const = 0; - - /// \return The maximum number of iterations to prefetch ahead. If - /// the required number of iterations is more than this number, no - /// prefetching is performed. - virtual unsigned getMaxPrefetchIterationsAhead() const = 0; - - /// \return True if prefetching should also be done for writes. - virtual bool enableWritePrefetching() const = 0; - - /// \return if target want to issue a prefetch in address space \p AS. - virtual bool shouldPrefetchAddressSpace(unsigned AS) const = 0; - - /// \return The cost of a partial reduction, which is a reduction from a - /// vector to another vector with fewer elements of larger size. They are - /// represented by the llvm.experimental.partial.reduce.add intrinsic, which - /// takes an accumulator and a binary operation operand that itself is fed by - /// two extends. An example of an operation that uses a partial reduction is a - /// dot product, which reduces two vectors to another of 4 times fewer and 4 - /// times larger elements. - virtual InstructionCost - getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, - Type *AccumType, ElementCount VF, - PartialReductionExtendKind OpAExtend, - PartialReductionExtendKind OpBExtend, - std::optional BinOp) const = 0; - - virtual unsigned getMaxInterleaveFactor(ElementCount VF) const = 0; - virtual InstructionCost - getArithmeticInstrCost(unsigned Opcode, Type *Ty, - TTI::TargetCostKind CostKind, - OperandValueInfo Opd1Info, OperandValueInfo Opd2Info, - ArrayRef Args, - const Instruction *CxtI = nullptr) const = 0; - virtual InstructionCost getAltInstrCost( - VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, - const SmallBitVector &OpcodeMask, - TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const = 0; - - virtual InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, - int Index, VectorType *SubTp, - ArrayRef Args, - const Instruction *CxtI) const = 0; - virtual InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, - Type *Src, CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I) const = 0; - virtual InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, - VectorType *VecTy, - unsigned Index) const = 0; - virtual InstructionCost - getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const = 0; - virtual InstructionCost - getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, - CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, - OperandValueInfo Op1Info, OperandValueInfo Op2Info, - const Instruction *I) const = 0; - virtual InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - TTI::TargetCostKind CostKind, - unsigned Index, Value *Op0, - Value *Op1) const = 0; - - /// \param ScalarUserAndIdx encodes the information about extracts from a - /// vector with 'Scalar' being the value being extracted,'User' being the user - /// of the extract(nullptr if user is not known before vectorization) and - /// 'Idx' being the extract lane. - virtual InstructionCost getVectorInstrCost( - unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, - Value *Scalar, - ArrayRef> ScalarUserAndIdx) const = 0; - - virtual InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, - TTI::TargetCostKind CostKind, - unsigned Index) const = 0; - - virtual InstructionCost - getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, - const APInt &DemandedDstElts, - TTI::TargetCostKind CostKind) const = 0; - - virtual InstructionCost - getInsertExtractValueCost(unsigned Opcode, - TTI::TargetCostKind CostKind) const = 0; - - virtual InstructionCost - getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, - unsigned AddressSpace, TTI::TargetCostKind CostKind, - OperandValueInfo OpInfo, const Instruction *I) const = 0; - virtual InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, - Align Alignment, - unsigned AddressSpace, - TTI::TargetCostKind CostKind, - const Instruction *I) const = 0; - virtual InstructionCost - getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, - unsigned AddressSpace, - TTI::TargetCostKind CostKind) const = 0; - virtual InstructionCost - getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, - bool VariableMask, Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const = 0; - virtual InstructionCost getExpandCompressMemoryOpCost( - unsigned Opcode, Type *DataTy, bool VariableMask, Align Alignment, - TTI::TargetCostKind CostKind, const Instruction *I = nullptr) const = 0; - virtual InstructionCost - getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, - bool VariableMask, Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const = 0; - - virtual InstructionCost getInterleavedMemoryOpCost( - unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, - Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond = false, bool UseMaskForGaps = false) const = 0; - virtual InstructionCost - getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, - std::optional FMF, - TTI::TargetCostKind CostKind) const = 0; - virtual InstructionCost - getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, - TTI::TargetCostKind CostKind) const = 0; - virtual InstructionCost getExtendedReductionCost( - unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, - std::optional FMF, - TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const = 0; - virtual InstructionCost getMulAccReductionCost( - bool IsUnsigned, Type *ResTy, VectorType *Ty, - TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const = 0; - virtual InstructionCost - getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const = 0; - virtual InstructionCost - getCallInstrCost(Function *F, Type *RetTy, ArrayRef Tys, - TTI::TargetCostKind CostKind) const = 0; - virtual unsigned getNumberOfParts(Type *Tp) const = 0; - virtual InstructionCost getAddressComputationCost(Type *Ty, - ScalarEvolution *SE, - const SCEV *Ptr) const = 0; - virtual InstructionCost - getCostOfKeepingLiveOverCall(ArrayRef Tys) const = 0; - virtual bool getTgtMemIntrinsic(IntrinsicInst *Inst, - MemIntrinsicInfo &Info) const = 0; - virtual unsigned getAtomicMemIntrinsicMaxElementSize() const = 0; - virtual Value * - getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, - Type *ExpectedType) const = 0; - virtual Type *getMemcpyLoopLoweringType( - LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, - unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, - std::optional AtomicElementSize) const = 0; - - virtual void getMemcpyLoopResidualLoweringType( - SmallVectorImpl &OpsOut, LLVMContext &Context, - unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, - Align SrcAlign, Align DestAlign, - std::optional AtomicCpySize) const = 0; - virtual bool areInlineCompatible(const Function *Caller, - const Function *Callee) const = 0; - virtual unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, - unsigned DefaultCallPenalty) const = 0; - virtual bool areTypesABICompatible(const Function *Caller, - const Function *Callee, - const ArrayRef &Types) const = 0; - virtual bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const = 0; - virtual bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const = 0; - virtual unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const = 0; - virtual bool isLegalToVectorizeLoad(LoadInst *LI) const = 0; - virtual bool isLegalToVectorizeStore(StoreInst *SI) const = 0; - virtual bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, - Align Alignment, - unsigned AddrSpace) const = 0; - virtual bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, - Align Alignment, - unsigned AddrSpace) const = 0; - virtual bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, - ElementCount VF) const = 0; - virtual bool isElementTypeLegalForScalableVector(Type *Ty) const = 0; - virtual unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, - unsigned ChainSizeInBytes, - VectorType *VecTy) const = 0; - virtual unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, - unsigned ChainSizeInBytes, - VectorType *VecTy) const = 0; - virtual bool preferFixedOverScalableIfEqualCost() const = 0; - virtual bool preferInLoopReduction(RecurKind Kind, Type *Ty) const = 0; - virtual bool preferPredicatedReductionSelect(unsigned Opcode, - Type *Ty) const = 0; - virtual bool preferAlternateOpcodeVectorization() const = 0; - virtual bool preferEpilogueVectorization() const = 0; - - virtual bool shouldExpandReduction(const IntrinsicInst *II) const = 0; - virtual ReductionShuffle - getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const = 0; - virtual unsigned getGISelRematGlobalCost() const = 0; - virtual unsigned getMinTripCountTailFoldingThreshold() const = 0; - virtual bool enableScalableVectorization() const = 0; - virtual bool supportsScalableVectors() const = 0; - virtual bool hasActiveVectorLength(unsigned Opcode, Type *DataType, - Align Alignment) const = 0; - virtual bool - isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &OpsToSink) const = 0; - - virtual bool isVectorShiftByScalarCheap(Type *Ty) const = 0; - virtual VPLegalization - getVPLegalizationStrategy(const VPIntrinsic &PI) const = 0; - virtual bool hasArmWideBranch(bool Thumb) const = 0; - virtual uint64_t getFeatureMask(const Function &F) const = 0; - virtual bool isMultiversionedFunction(const Function &F) const = 0; - virtual unsigned getMaxNumArgs() const = 0; - virtual unsigned getNumBytesToPadGlobalArray(unsigned Size, - Type *ArrayType) const = 0; - virtual void collectKernelLaunchBounds( - const Function &F, - SmallVectorImpl> &LB) const = 0; + std::unique_ptr TTIImpl; }; /// Analysis pass providing the \c TargetTransformInfo. diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index 7cf5fc377bfd5..c4892c8f09b5c 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -31,7 +31,7 @@ class Function; /// Base class for use as a mix-in that aids implementing /// a TargetTransformInfo-compatible class. -class TargetTransformInfoImplBase : public TTI::Concept { +class TargetTransformInfoImplBase { protected: typedef TargetTransformInfo TTI; @@ -41,17 +41,20 @@ class TargetTransformInfoImplBase : public TTI::Concept { explicit TargetTransformInfoImplBase(const DataLayout &DL) : DL(DL) {} public: + virtual ~TargetTransformInfoImplBase(); + // Provide value semantics. MSVC requires that we spell all of these out. TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg) = default; TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg) : DL(Arg.DL) {} - const DataLayout &getDataLayout() const override { return DL; } + virtual const DataLayout &getDataLayout() const { return DL; } // FIXME: It looks like this implementation is dead. All clients appear to // use the (non-const) version from `TargetTransformInfoImplCRTPBase`. - InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, - ArrayRef Operands, Type *AccessType, - TTI::TargetCostKind CostKind) const override { + virtual InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, + ArrayRef Operands, + Type *AccessType, + TTI::TargetCostKind CostKind) const { // In the basic model, we just assume that all-constant GEPs will be folded // into their uses via addressing modes. for (const Value *Operand : Operands) @@ -61,43 +64,56 @@ class TargetTransformInfoImplBase : public TTI::Concept { return TTI::TCC_Free; } - unsigned + virtual InstructionCost + getPointersChainCost(ArrayRef Ptrs, const Value *Base, + const TTI::PointersChainInfo &Info, Type *AccessTy, + TTI::TargetCostKind CostKind) const { + llvm_unreachable("Not implemented"); + } + + virtual unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI) const override { + BlockFrequencyInfo *BFI) const { (void)PSI; (void)BFI; JTSize = 0; return SI.getNumCases(); } - unsigned getInliningThresholdMultiplier() const override { return 1; } - unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const override { + virtual InstructionCost + getInstructionCost(const User *U, ArrayRef Operands, + TTI::TargetCostKind CostKind) const { + llvm_unreachable("Not implemented"); + } + + virtual unsigned getInliningThresholdMultiplier() const { return 1; } + virtual unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const { return 8; } - unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const override { + virtual unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const { return 8; } - int getInliningLastCallToStaticBonus() const override { + virtual int getInliningLastCallToStaticBonus() const { // This is the value of InlineConstants::LastCallToStaticBonus before it was // removed along with the introduction of this function. return 15000; } - unsigned adjustInliningThreshold(const CallBase *CB) const override { + virtual unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; } - unsigned getCallerAllocaCost(const CallBase *CB, - const AllocaInst *AI) const override { + virtual unsigned getCallerAllocaCost(const CallBase *CB, + const AllocaInst *AI) const { return 0; }; - int getInlinerVectorBonusPercent() const override { return 150; } + virtual int getInlinerVectorBonusPercent() const { return 150; } - InstructionCost getMemcpyCost(const Instruction *I) const override { + virtual InstructionCost getMemcpyCost(const Instruction *I) const { return TTI::TCC_Expensive; } - uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override { return 64; } + virtual uint64_t getMaxMemIntrinsicInlineSizeThreshold() const { return 64; } // Although this default value is arbitrary, it is not random. It is assumed // that a condition that evaluates the same way by a higher percentage than @@ -105,56 +121,57 @@ class TargetTransformInfoImplBase : public TTI::Concept { // should be set such that the win from N% correct executions is greater than // the loss from (100 - N)% mispredicted executions for the majority of // intended targets. - BranchProbability getPredictableBranchThreshold() const override { + virtual BranchProbability getPredictableBranchThreshold() const { return BranchProbability(99, 100); } - InstructionCost getBranchMispredictPenalty() const override { return 0; } + virtual InstructionCost getBranchMispredictPenalty() const { return 0; } - bool hasBranchDivergence(const Function *F = nullptr) const override { + virtual bool hasBranchDivergence(const Function *F = nullptr) const { return false; } - bool isSourceOfDivergence(const Value *V) const override { return false; } + virtual bool isSourceOfDivergence(const Value *V) const { return false; } - bool isAlwaysUniform(const Value *V) const override { return false; } + virtual bool isAlwaysUniform(const Value *V) const { return false; } - bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override { + virtual bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const { return false; } - bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override { + virtual bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const { return true; } - unsigned getFlatAddressSpace() const override { return -1; } + virtual unsigned getFlatAddressSpace() const { return -1; } - bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes, - Intrinsic::ID IID) const override { + virtual bool collectFlatAddressOperands(SmallVectorImpl &OpIndexes, + Intrinsic::ID IID) const { return false; } - bool isNoopAddrSpaceCast(unsigned, unsigned) const override { return false; } - bool - canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override { + virtual bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; } + virtual bool + canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const { return AS == 0; }; - unsigned getAssumedAddrSpace(const Value *V) const override { return -1; } + virtual unsigned getAssumedAddrSpace(const Value *V) const { return -1; } - bool isSingleThreaded() const override { return false; } + virtual bool isSingleThreaded() const { return false; } - std::pair - getPredicatedAddrSpace(const Value *V) const override { + virtual std::pair + getPredicatedAddrSpace(const Value *V) const { return std::make_pair(nullptr, -1); } - Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, - Value *NewV) const override { + virtual Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, + Value *OldV, + Value *NewV) const { return nullptr; } - bool isLoweredToCall(const Function *F) const override { + virtual bool isLoweredToCall(const Function *F) const { assert(F && "A concrete function must be provided to this routine."); // FIXME: These should almost certainly not be handled here, and instead @@ -201,187 +218,189 @@ class TargetTransformInfoImplBase : public TTI::Concept { return true; } - bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, - AssumptionCache &AC, TargetLibraryInfo *LibInfo, - HardwareLoopInfo &HWLoopInfo) const override { + virtual bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, + AssumptionCache &AC, + TargetLibraryInfo *LibInfo, + HardwareLoopInfo &HWLoopInfo) const { return false; } - unsigned getEpilogueVectorizationMinVF() const override { return 16; } + virtual unsigned getEpilogueVectorizationMinVF() const { return 16; } - bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const override { + virtual bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const { return false; } - TailFoldingStyle - getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const override { + virtual TailFoldingStyle + getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const { return TailFoldingStyle::DataWithoutLaneMask; } - std::optional - instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override { + virtual std::optional + instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { return std::nullopt; } - std::optional + virtual std::optional simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, - bool &KnownBitsComputed) const override { + bool &KnownBitsComputed) const { return std::nullopt; } - std::optional simplifyDemandedVectorEltsIntrinsic( + virtual std::optional simplifyDemandedVectorEltsIntrinsic( InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function - SimplifyAndSetOp) const override { + SimplifyAndSetOp) const { return std::nullopt; } - void getUnrollingPreferences(Loop *, ScalarEvolution &, - TTI::UnrollingPreferences &, - OptimizationRemarkEmitter *) const override {} + virtual void getUnrollingPreferences(Loop *, ScalarEvolution &, + TTI::UnrollingPreferences &, + OptimizationRemarkEmitter *) const {} - void getPeelingPreferences(Loop *, ScalarEvolution &, - TTI::PeelingPreferences &) const override {} + virtual void getPeelingPreferences(Loop *, ScalarEvolution &, + TTI::PeelingPreferences &) const {} - bool isLegalAddImmediate(int64_t Imm) const override { return false; } + virtual bool isLegalAddImmediate(int64_t Imm) const { return false; } - bool isLegalAddScalableImmediate(int64_t Imm) const override { return false; } + virtual bool isLegalAddScalableImmediate(int64_t Imm) const { return false; } - bool isLegalICmpImmediate(int64_t Imm) const override { return false; } + virtual bool isLegalICmpImmediate(int64_t Imm) const { return false; } - bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, - bool HasBaseReg, int64_t Scale, unsigned AddrSpace, - Instruction *I = nullptr, - int64_t ScalableOffset = 0) const override { + virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, + int64_t BaseOffset, bool HasBaseReg, + int64_t Scale, unsigned AddrSpace, + Instruction *I = nullptr, + int64_t ScalableOffset = 0) const { // Guess that only reg and reg+reg addressing is allowed. This heuristic is // taken from the implementation of LSR. return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1); } - bool isLSRCostLess(const TTI::LSRCost &C1, - const TTI::LSRCost &C2) const override { + virtual bool isLSRCostLess(const TTI::LSRCost &C1, + const TTI::LSRCost &C2) const { return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) < std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost); } - bool isNumRegsMajorCostOfLSR() const override { return true; } + virtual bool isNumRegsMajorCostOfLSR() const { return true; } - bool shouldDropLSRSolutionIfLessProfitable() const override { return false; } + virtual bool shouldDropLSRSolutionIfLessProfitable() const { return false; } - bool isProfitableLSRChainElement(Instruction *I) const override { + virtual bool isProfitableLSRChainElement(Instruction *I) const { return false; } - bool canMacroFuseCmp() const override { return false; } + virtual bool canMacroFuseCmp() const { return false; } - bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, - DominatorTree *DT, AssumptionCache *AC, - TargetLibraryInfo *LibInfo) const override { + virtual bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, + LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, + TargetLibraryInfo *LibInfo) const { return false; } - TTI::AddressingModeKind - getPreferredAddressingMode(const Loop *L, - ScalarEvolution *SE) const override { + virtual TTI::AddressingModeKind + getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const { return TTI::AMK_None; } - bool isLegalMaskedStore(Type *DataType, Align Alignment, - unsigned AddressSpace) const override { + virtual bool isLegalMaskedStore(Type *DataType, Align Alignment, + unsigned AddressSpace) const { return false; } - bool isLegalMaskedLoad(Type *DataType, Align Alignment, - unsigned AddressSpace) const override { + virtual bool isLegalMaskedLoad(Type *DataType, Align Alignment, + unsigned AddressSpace) const { return false; } - bool isLegalNTStore(Type *DataType, Align Alignment) const override { + virtual bool isLegalNTStore(Type *DataType, Align Alignment) const { // By default, assume nontemporal memory stores are available for stores // that are aligned and have a size that is a power of 2. unsigned DataSize = DL.getTypeStoreSize(DataType); return Alignment >= DataSize && isPowerOf2_32(DataSize); } - bool isLegalNTLoad(Type *DataType, Align Alignment) const override { + virtual bool isLegalNTLoad(Type *DataType, Align Alignment) const { // By default, assume nontemporal memory loads are available for loads that // are aligned and have a size that is a power of 2. unsigned DataSize = DL.getTypeStoreSize(DataType); return Alignment >= DataSize && isPowerOf2_32(DataSize); } - bool isLegalBroadcastLoad(Type *ElementTy, - ElementCount NumElements) const override { + virtual bool isLegalBroadcastLoad(Type *ElementTy, + ElementCount NumElements) const { return false; } - bool isLegalMaskedScatter(Type *DataType, Align Alignment) const override { + virtual bool isLegalMaskedScatter(Type *DataType, Align Alignment) const { return false; } - bool isLegalMaskedGather(Type *DataType, Align Alignment) const override { + virtual bool isLegalMaskedGather(Type *DataType, Align Alignment) const { return false; } - bool forceScalarizeMaskedGather(VectorType *DataType, - Align Alignment) const override { + virtual bool forceScalarizeMaskedGather(VectorType *DataType, + Align Alignment) const { return false; } - bool forceScalarizeMaskedScatter(VectorType *DataType, - Align Alignment) const override { + virtual bool forceScalarizeMaskedScatter(VectorType *DataType, + Align Alignment) const { return false; } - bool isLegalMaskedCompressStore(Type *DataType, - Align Alignment) const override { + virtual bool isLegalMaskedCompressStore(Type *DataType, + Align Alignment) const { return false; } - bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, - const SmallBitVector &OpcodeMask) const override { + virtual bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, + unsigned Opcode1, + const SmallBitVector &OpcodeMask) const { return false; } - bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const override { + virtual bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const { return false; } - bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const override { + virtual bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const { return false; } - bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, - Align Alignment, - unsigned AddrSpace) const override { + virtual bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, + Align Alignment, + unsigned AddrSpace) const { return false; } - bool isLegalMaskedVectorHistogram(Type *AddrType, - Type *DataType) const override { + virtual bool isLegalMaskedVectorHistogram(Type *AddrType, + Type *DataType) const { return false; } - bool enableOrderedReductions() const override { return false; } + virtual bool enableOrderedReductions() const { return false; } - bool hasDivRemOp(Type *DataType, bool IsSigned) const override { + virtual bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; } - bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const override { + virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const { return false; } - bool prefersVectorizedAddressing() const override { return true; } + virtual bool prefersVectorizedAddressing() const { return true; } - InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - StackOffset BaseOffset, bool HasBaseReg, - int64_t Scale, - unsigned AddrSpace) const override { + virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, + StackOffset BaseOffset, + bool HasBaseReg, int64_t Scale, + unsigned AddrSpace) const { // Guess that all legal addressing mode are free. if (isLegalAddressingMode(Ty, BaseGV, BaseOffset.getFixed(), HasBaseReg, Scale, AddrSpace, /*I=*/nullptr, @@ -390,79 +409,81 @@ class TargetTransformInfoImplBase : public TTI::Concept { return InstructionCost::getInvalid(); } - bool LSRWithInstrQueries() const override { return false; } + virtual bool LSRWithInstrQueries() const { return false; } - bool isTruncateFree(Type *Ty1, Type *Ty2) const override { return false; } + virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; } - bool isProfitableToHoist(Instruction *I) const override { return true; } + virtual bool isProfitableToHoist(Instruction *I) const { return true; } - bool useAA() const override { return false; } + virtual bool useAA() const { return false; } - bool isTypeLegal(Type *Ty) const override { return false; } + virtual bool isTypeLegal(Type *Ty) const { return false; } - unsigned getRegUsageForType(Type *Ty) const override { return 1; } + virtual unsigned getRegUsageForType(Type *Ty) const { return 1; } - bool shouldBuildLookupTables() const override { return true; } + virtual bool shouldBuildLookupTables() const { return true; } - bool shouldBuildLookupTablesForConstant(Constant *C) const override { + virtual bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; } - bool shouldBuildRelLookupTables() const override { return false; } + virtual bool shouldBuildRelLookupTables() const { return false; } - bool useColdCCForColdCall(Function &F) const override { return false; } + virtual bool useColdCCForColdCall(Function &F) const { return false; } - bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const override { + virtual bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const { return false; } - bool - isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, - unsigned ScalarOpdIdx) const override { + virtual bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, + unsigned ScalarOpdIdx) const { return false; } - bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, - int OpdIdx) const override { + virtual bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, + int OpdIdx) const { return OpdIdx == -1; } - bool + virtual bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, - int RetIdx) const override { + int RetIdx) const { return RetIdx == 0; } - InstructionCost getScalarizationOverhead( + virtual InstructionCost getScalarizationOverhead( VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, - TTI::TargetCostKind CostKind, ArrayRef VL = {}) const override { + TTI::TargetCostKind CostKind, ArrayRef VL = {}) const { return 0; } - InstructionCost getOperandsScalarizationOverhead( - ArrayRef Args, ArrayRef Tys, - TTI::TargetCostKind CostKind) const override { + virtual InstructionCost + getOperandsScalarizationOverhead(ArrayRef Args, + ArrayRef Tys, + TTI::TargetCostKind CostKind) const { return 0; } - bool supportsEfficientVectorElementLoadStore() const override { - return false; - } + virtual bool supportsEfficientVectorElementLoadStore() const { return false; } + + virtual bool supportsTailCalls() const { return true; } - bool supportsTailCalls() const override { return true; } + virtual bool supportsTailCallFor(const CallBase *CB) const { + llvm_unreachable("Not implemented"); + } - bool enableAggressiveInterleaving(bool LoopHasReductions) const override { + virtual bool enableAggressiveInterleaving(bool LoopHasReductions) const { return false; } - TTI::MemCmpExpansionOptions - enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override { + virtual TTI::MemCmpExpansionOptions + enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { return {}; } - bool enableSelectOptimize() const override { return true; } + virtual bool enableSelectOptimize() const { return true; } - bool shouldTreatInstructionLikeSelect(const Instruction *I) const override { + virtual bool shouldTreatInstructionLikeSelect(const Instruction *I) const { // A select with two constant operands will usually be better left as a // select. using namespace llvm::PatternMatch; @@ -475,77 +496,79 @@ class TargetTransformInfoImplBase : public TTI::Concept { m_LogicalOr(m_Value(), m_Value()))); } - bool enableInterleavedAccessVectorization() const override { return false; } + virtual bool enableInterleavedAccessVectorization() const { return false; } - bool enableMaskedInterleavedAccessVectorization() const override { + virtual bool enableMaskedInterleavedAccessVectorization() const { return false; } - bool isFPVectorizationPotentiallyUnsafe() const override { return false; } + virtual bool isFPVectorizationPotentiallyUnsafe() const { return false; } - bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, - unsigned AddressSpace, Align Alignment, - unsigned *Fast) const override { + virtual bool allowsMisalignedMemoryAccesses(LLVMContext &Context, + unsigned BitWidth, + unsigned AddressSpace, + Align Alignment, + unsigned *Fast) const { return false; } - TTI::PopcntSupportKind - getPopcntSupport(unsigned IntTyWidthInBit) const override { + virtual TTI::PopcntSupportKind + getPopcntSupport(unsigned IntTyWidthInBit) const { return TTI::PSK_Software; } - bool haveFastSqrt(Type *Ty) const override { return false; } + virtual bool haveFastSqrt(Type *Ty) const { return false; } - bool isExpensiveToSpeculativelyExecute(const Instruction *I) const override { + virtual bool isExpensiveToSpeculativelyExecute(const Instruction *I) const { return true; } - bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const override { return true; } + virtual bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; } - InstructionCost getFPOpCost(Type *Ty) const override { + virtual InstructionCost getFPOpCost(Type *Ty) const { return TargetTransformInfo::TCC_Basic; } - InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, - const APInt &Imm, - Type *Ty) const override { + virtual InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, + const APInt &Imm, + Type *Ty) const { return 0; } - InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind) const override { + virtual InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, + TTI::TargetCostKind CostKind) const { return TTI::TCC_Basic; } - InstructionCost - getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, - TTI::TargetCostKind CostKind, - Instruction *Inst = nullptr) const override { + virtual InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, + const APInt &Imm, Type *Ty, + TTI::TargetCostKind CostKind, + Instruction *Inst = nullptr) const { return TTI::TCC_Free; } - InstructionCost + virtual InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, - Type *Ty, TTI::TargetCostKind CostKind) const override { + Type *Ty, TTI::TargetCostKind CostKind) const { return TTI::TCC_Free; } - bool preferToKeepConstantsAttached(const Instruction &Inst, - const Function &Fn) const override { + virtual bool preferToKeepConstantsAttached(const Instruction &Inst, + const Function &Fn) const { return false; } - unsigned getNumberOfRegisters(unsigned ClassID) const override { return 8; } - bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const override { + virtual unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; } + virtual bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const { return false; } - unsigned getRegisterClassForType(bool Vector, - Type *Ty = nullptr) const override { + virtual unsigned getRegisterClassForType(bool Vector, + Type *Ty = nullptr) const { return Vector ? 1 : 0; } - const char *getRegisterClassName(unsigned ClassID) const override { + virtual const char *getRegisterClassName(unsigned ClassID) const { switch (ClassID) { default: return "Generic::Unknown Register Class"; @@ -556,46 +579,44 @@ class TargetTransformInfoImplBase : public TTI::Concept { } } - TypeSize - getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override { + virtual TypeSize + getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { return TypeSize::getFixed(32); } - unsigned getMinVectorRegisterBitWidth() const override { return 128; } + virtual unsigned getMinVectorRegisterBitWidth() const { return 128; } - std::optional getMaxVScale() const override { return std::nullopt; } - std::optional getVScaleForTuning() const override { + virtual std::optional getMaxVScale() const { return std::nullopt; } + virtual std::optional getVScaleForTuning() const { return std::nullopt; } - bool isVScaleKnownToBeAPowerOfTwo() const override { return false; } + virtual bool isVScaleKnownToBeAPowerOfTwo() const { return false; } - bool shouldMaximizeVectorBandwidth( - TargetTransformInfo::RegisterKind K) const override { + virtual bool + shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const { return false; } - ElementCount getMinimumVF(unsigned ElemWidth, - bool IsScalable) const override { + virtual ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const { return ElementCount::get(0, IsScalable); } - unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override { + virtual unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; } - unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const override { + virtual unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const { return VF; } - bool shouldConsiderAddressTypePromotion( - const Instruction &I, - bool &AllowPromotionWithoutCommonHeader) const override { + virtual bool shouldConsiderAddressTypePromotion( + const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const { AllowPromotionWithoutCommonHeader = false; return false; } - unsigned getCacheLineSize() const override { return 0; } - std::optional - getCacheSize(TargetTransformInfo::CacheLevel Level) const override { + virtual unsigned getCacheLineSize() const { return 0; } + virtual std::optional + getCacheSize(TargetTransformInfo::CacheLevel Level) const { switch (Level) { case TargetTransformInfo::CacheLevel::L1D: [[fallthrough]]; @@ -605,8 +626,8 @@ class TargetTransformInfoImplBase : public TTI::Concept { llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); } - std::optional - getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const override { + virtual std::optional + getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const { switch (Level) { case TargetTransformInfo::CacheLevel::L1D: [[fallthrough]]; @@ -617,34 +638,34 @@ class TargetTransformInfoImplBase : public TTI::Concept { llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); } - std::optional getMinPageSize() const override { return {}; } + virtual std::optional getMinPageSize() const { return {}; } - unsigned getPrefetchDistance() const override { return 0; } - unsigned getMinPrefetchStride(unsigned NumMemAccesses, - unsigned NumStridedMemAccesses, - unsigned NumPrefetches, - bool HasCall) const override { + virtual unsigned getPrefetchDistance() const { return 0; } + virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, + unsigned NumStridedMemAccesses, + unsigned NumPrefetches, + bool HasCall) const { return 1; } - unsigned getMaxPrefetchIterationsAhead() const override { return UINT_MAX; } - bool enableWritePrefetching() const override { return false; } - bool shouldPrefetchAddressSpace(unsigned AS) const override { return !AS; } + virtual unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; } + virtual bool enableWritePrefetching() const { return false; } + virtual bool shouldPrefetchAddressSpace(unsigned AS) const { return !AS; } - InstructionCost getPartialReductionCost( - unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, - ElementCount VF, TTI::PartialReductionExtendKind OpAExtend, - TTI::PartialReductionExtendKind OpBExtend, - std::optional BinOp = std::nullopt) const override { + virtual InstructionCost + getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, + Type *AccumType, ElementCount VF, + TTI::PartialReductionExtendKind OpAExtend, + TTI::PartialReductionExtendKind OpBExtend, + std::optional BinOp = std::nullopt) const { return InstructionCost::getInvalid(); } - unsigned getMaxInterleaveFactor(ElementCount VF) const override { return 1; } + virtual unsigned getMaxInterleaveFactor(ElementCount VF) const { return 1; } - InstructionCost getArithmeticInstrCost( + virtual InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info, - ArrayRef Args, - const Instruction *CxtI = nullptr) const override { + ArrayRef Args, const Instruction *CxtI = nullptr) const { // Widenable conditions will eventually lower into constants, so some // operations with them will be trivially optimized away. auto IsWidenableCondition = [](const Value *V) { @@ -681,25 +702,25 @@ class TargetTransformInfoImplBase : public TTI::Concept { return 1; } - InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, - unsigned Opcode1, - const SmallBitVector &OpcodeMask, - TTI::TargetCostKind CostKind) const override { + virtual InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, + unsigned Opcode1, + const SmallBitVector &OpcodeMask, + TTI::TargetCostKind CostKind) const { return InstructionCost::getInvalid(); } - InstructionCost + virtual InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef Args = {}, - const Instruction *CxtI = nullptr) const override { + const Instruction *CxtI = nullptr) const { return 1; } - InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, - TTI::CastContextHint CCH, - TTI::TargetCostKind CostKind, - const Instruction *I) const override { + virtual InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, + Type *Src, TTI::CastContextHint CCH, + TTI::TargetCostKind CostKind, + const Instruction *I) const { switch (Opcode) { default: break; @@ -734,15 +755,15 @@ class TargetTransformInfoImplBase : public TTI::Concept { return 1; } - InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, - VectorType *VecTy, - unsigned Index) const override { + virtual InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, + VectorType *VecTy, + unsigned Index) const { return 1; } - InstructionCost - getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const override { + virtual InstructionCost getCFInstrCost(unsigned Opcode, + TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) const { // A phi would be free, unless we're costing the throughput because it // will require a register. if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput) @@ -750,19 +771,17 @@ class TargetTransformInfoImplBase : public TTI::Concept { return 1; } - InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, - CmpInst::Predicate VecPred, - TTI::TargetCostKind CostKind, - TTI::OperandValueInfo Op1Info, - TTI::OperandValueInfo Op2Info, - const Instruction *I) const override { + virtual InstructionCost getCmpSelInstrCost( + unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, + TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info, + TTI::OperandValueInfo Op2Info, const Instruction *I) const { return 1; } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - TTI::TargetCostKind CostKind, - unsigned Index, Value *Op0, - Value *Op1) const override { + virtual InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, + TTI::TargetCostKind CostKind, + unsigned Index, Value *Op0, + Value *Op1) const { return 1; } @@ -770,30 +789,29 @@ class TargetTransformInfoImplBase : public TTI::Concept { /// vector with 'Scalar' being the value being extracted,'User' being the user /// of the extract(nullptr if user is not known before vectorization) and /// 'Idx' being the extract lane. - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - TTI::TargetCostKind CostKind, - unsigned Index, Value *Scalar, - ArrayRef> - ScalarUserAndIdx) const override { + virtual InstructionCost getVectorInstrCost( + unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, + Value *Scalar, + ArrayRef> ScalarUserAndIdx) const { return 1; } - InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, - TTI::TargetCostKind CostKind, - unsigned Index) const override { + virtual InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, + TTI::TargetCostKind CostKind, + unsigned Index) const { return 1; } - InstructionCost + virtual InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, - TTI::TargetCostKind CostKind) const override { + TTI::TargetCostKind CostKind) const { return 1; } - InstructionCost + virtual InstructionCost getInsertExtractValueCost(unsigned Opcode, - TTI::TargetCostKind CostKind) const override { + TTI::TargetCostKind CostKind) const { // Note: The `insertvalue` cost here is chosen to match the default case of // getInstructionCost() -- as pior to adding this helper `insertvalue` was // not handled. @@ -802,62 +820,60 @@ class TargetTransformInfoImplBase : public TTI::Concept { return TTI::TCC_Free; } - InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, - unsigned AddressSpace, - TTI::TargetCostKind CostKind, - TTI::OperandValueInfo OpInfo, - const Instruction *I) const override { + virtual InstructionCost + getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, + unsigned AddressSpace, TTI::TargetCostKind CostKind, + TTI::OperandValueInfo OpInfo, const Instruction *I) const { return 1; } - InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, - unsigned AddressSpace, - TTI::TargetCostKind CostKind, - const Instruction *I) const override { + virtual InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, + Align Alignment, + unsigned AddressSpace, + TTI::TargetCostKind CostKind, + const Instruction *I) const { return 1; } - InstructionCost + virtual InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, - TTI::TargetCostKind CostKind) const override { + TTI::TargetCostKind CostKind) const { return 1; } - InstructionCost + virtual InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const override { + const Instruction *I = nullptr) const { return 1; } - InstructionCost - getExpandCompressMemoryOpCost(unsigned Opcode, Type *DataTy, - bool VariableMask, Align Alignment, - TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const override { + virtual InstructionCost getExpandCompressMemoryOpCost( + unsigned Opcode, Type *DataTy, bool VariableMask, Align Alignment, + TTI::TargetCostKind CostKind, const Instruction *I = nullptr) const { return 1; } - InstructionCost + virtual InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, - const Instruction *I = nullptr) const override { + const Instruction *I = nullptr) const { return InstructionCost::getInvalid(); } - InstructionCost getInterleavedMemoryOpCost( + virtual InstructionCost getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, - bool UseMaskForCond, bool UseMaskForGaps) const override { + bool UseMaskForCond, bool UseMaskForGaps) const { return 1; } - InstructionCost + virtual InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, - TTI::TargetCostKind CostKind) const override { + TTI::TargetCostKind CostKind) const { switch (ICA.getID()) { default: break; @@ -907,57 +923,57 @@ class TargetTransformInfoImplBase : public TTI::Concept { return 1; } - InstructionCost - getCallInstrCost(Function *F, Type *RetTy, ArrayRef Tys, - TTI::TargetCostKind CostKind) const override { + virtual InstructionCost getCallInstrCost(Function *F, Type *RetTy, + ArrayRef Tys, + TTI::TargetCostKind CostKind) const { return 1; } // Assume that we have a register of the right size for the type. - unsigned getNumberOfParts(Type *Tp) const override { return 1; } + virtual unsigned getNumberOfParts(Type *Tp) const { return 1; } - InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, - const SCEV *) const override { + virtual InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, + const SCEV *) const { return 0; } - InstructionCost + virtual InstructionCost getArithmeticReductionCost(unsigned, VectorType *, std::optional FMF, - TTI::TargetCostKind) const override { + TTI::TargetCostKind) const { return 1; } - InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *, - FastMathFlags, - TTI::TargetCostKind) const override { + virtual InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, + VectorType *, FastMathFlags, + TTI::TargetCostKind) const { return 1; } - InstructionCost + virtual InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional FMF, - TTI::TargetCostKind CostKind) const override { + TTI::TargetCostKind CostKind) const { return 1; } - InstructionCost + virtual InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, - TTI::TargetCostKind CostKind) const override { + TTI::TargetCostKind CostKind) const { return 1; } - InstructionCost - getCostOfKeepingLiveOverCall(ArrayRef Tys) const override { + virtual InstructionCost + getCostOfKeepingLiveOverCall(ArrayRef Tys) const { return 0; } - bool getTgtMemIntrinsic(IntrinsicInst *Inst, - MemIntrinsicInfo &Info) const override { + virtual bool getTgtMemIntrinsic(IntrinsicInst *Inst, + MemIntrinsicInfo &Info) const { return false; } - unsigned getAtomicMemIntrinsicMaxElementSize() const override { + virtual unsigned getAtomicMemIntrinsicMaxElementSize() const { // Note for overrides: You must ensure for all element unordered-atomic // memory intrinsics that all power-of-2 element sizes up to, and // including, the return value of this method have a corresponding @@ -966,166 +982,170 @@ class TargetTransformInfoImplBase : public TTI::Concept { return 0; } - Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, - Type *ExpectedType) const override { + virtual Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, + Type *ExpectedType) const { return nullptr; } - Type *getMemcpyLoopLoweringType( - LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, - unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, - std::optional AtomicElementSize) const override { + virtual Type * + getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, + unsigned SrcAddrSpace, unsigned DestAddrSpace, + Align SrcAlign, Align DestAlign, + std::optional AtomicElementSize) const { return AtomicElementSize ? Type::getIntNTy(Context, *AtomicElementSize * 8) : Type::getInt8Ty(Context); } - void getMemcpyLoopResidualLoweringType( + virtual void getMemcpyLoopResidualLoweringType( SmallVectorImpl &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, - std::optional AtomicCpySize) const override { + std::optional AtomicCpySize) const { unsigned OpSizeInBytes = AtomicCpySize.value_or(1); Type *OpType = Type::getIntNTy(Context, OpSizeInBytes * 8); for (unsigned i = 0; i != RemainingBytes; i += OpSizeInBytes) OpsOut.push_back(OpType); } - bool areInlineCompatible(const Function *Caller, - const Function *Callee) const override { + virtual bool areInlineCompatible(const Function *Caller, + const Function *Callee) const { return (Caller->getFnAttribute("target-cpu") == Callee->getFnAttribute("target-cpu")) && (Caller->getFnAttribute("target-features") == Callee->getFnAttribute("target-features")); } - unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, - unsigned DefaultCallPenalty) const override { + virtual unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, + unsigned DefaultCallPenalty) const { return DefaultCallPenalty; } - bool areTypesABICompatible(const Function *Caller, const Function *Callee, - const ArrayRef &Types) const override { + virtual bool areTypesABICompatible(const Function *Caller, + const Function *Callee, + const ArrayRef &Types) const { return (Caller->getFnAttribute("target-cpu") == Callee->getFnAttribute("target-cpu")) && (Caller->getFnAttribute("target-features") == Callee->getFnAttribute("target-features")); } - bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty) const override { + virtual bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty) const { return false; } - bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty) const override { + virtual bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty) const { return false; } - unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override { + virtual unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; } - bool isLegalToVectorizeLoad(LoadInst *LI) const override { return true; } + virtual bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; } - bool isLegalToVectorizeStore(StoreInst *SI) const override { return true; } + virtual bool isLegalToVectorizeStore(StoreInst *SI) const { return true; } - bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const override { + virtual bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, + Align Alignment, + unsigned AddrSpace) const { return true; } - bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, - unsigned AddrSpace) const override { + virtual bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, + Align Alignment, + unsigned AddrSpace) const { return true; } - bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, - ElementCount VF) const override { + virtual bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, + ElementCount VF) const { return true; } - bool isElementTypeLegalForScalableVector(Type *Ty) const override { + virtual bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; } - unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, - unsigned ChainSizeInBytes, - VectorType *VecTy) const override { + virtual unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, + unsigned ChainSizeInBytes, + VectorType *VecTy) const { return VF; } - unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, - unsigned ChainSizeInBytes, - VectorType *VecTy) const override { + virtual unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, + unsigned ChainSizeInBytes, + VectorType *VecTy) const { return VF; } - bool preferFixedOverScalableIfEqualCost() const override { return false; } + virtual bool preferFixedOverScalableIfEqualCost() const { return false; } - bool preferInLoopReduction(RecurKind Kind, Type *Ty) const override { + virtual bool preferInLoopReduction(RecurKind Kind, Type *Ty) const { return false; } - bool preferAlternateOpcodeVectorization() const override { return true; } + virtual bool preferAlternateOpcodeVectorization() const { return true; } - bool preferPredicatedReductionSelect(unsigned Opcode, - Type *Ty) const override { + virtual bool preferPredicatedReductionSelect(unsigned Opcode, + Type *Ty) const { return false; } - bool preferEpilogueVectorization() const override { return true; } + virtual bool preferEpilogueVectorization() const { return true; } - bool shouldExpandReduction(const IntrinsicInst *II) const override { + virtual bool shouldExpandReduction(const IntrinsicInst *II) const { return true; } - TTI::ReductionShuffle - getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const override { + virtual TTI::ReductionShuffle + getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const { return TTI::ReductionShuffle::SplitHalf; } - unsigned getGISelRematGlobalCost() const override { return 1; } + virtual unsigned getGISelRematGlobalCost() const { return 1; } - unsigned getMinTripCountTailFoldingThreshold() const override { return 0; } + virtual unsigned getMinTripCountTailFoldingThreshold() const { return 0; } - bool supportsScalableVectors() const override { return false; } + virtual bool supportsScalableVectors() const { return false; } - bool enableScalableVectorization() const override { return false; } + virtual bool enableScalableVectorization() const { return false; } - bool hasActiveVectorLength(unsigned Opcode, Type *DataType, - Align Alignment) const override { + virtual bool hasActiveVectorLength(unsigned Opcode, Type *DataType, + Align Alignment) const { return false; } - bool isProfitableToSinkOperands(Instruction *I, - SmallVectorImpl &Ops) const override { + virtual bool isProfitableToSinkOperands(Instruction *I, + SmallVectorImpl &Ops) const { return false; } - bool isVectorShiftByScalarCheap(Type *Ty) const override { return false; } + virtual bool isVectorShiftByScalarCheap(Type *Ty) const { return false; } - TargetTransformInfo::VPLegalization - getVPLegalizationStrategy(const VPIntrinsic &PI) const override { + virtual TargetTransformInfo::VPLegalization + getVPLegalizationStrategy(const VPIntrinsic &PI) const { return TargetTransformInfo::VPLegalization( /* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard, /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert); } - bool hasArmWideBranch(bool) const override { return false; } + virtual bool hasArmWideBranch(bool) const { return false; } - uint64_t getFeatureMask(const Function &F) const override { return 0; } + virtual uint64_t getFeatureMask(const Function &F) const { return 0; } - bool isMultiversionedFunction(const Function &F) const override { + virtual bool isMultiversionedFunction(const Function &F) const { return false; } - unsigned getMaxNumArgs() const override { return UINT_MAX; } + virtual unsigned getMaxNumArgs() const { return UINT_MAX; } - unsigned getNumBytesToPadGlobalArray(unsigned Size, - Type *ArrayType) const override { + virtual unsigned getNumBytesToPadGlobalArray(unsigned Size, + Type *ArrayType) const { return 0; } - void collectKernelLaunchBounds( + virtual void collectKernelLaunchBounds( const Function &F, - SmallVectorImpl> &LB) const override {} + SmallVectorImpl> &LB) const {} protected: // Obtain the minimum required size to hold the value (without the sign) diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index f5426cae42228..33f4056467cad 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -57,7 +57,8 @@ struct NoTTIImpl : TargetTransformInfoImplCRTPBase { }; } // namespace -TargetTransformInfo::TargetTransformInfo(std::unique_ptr Impl) +TargetTransformInfo::TargetTransformInfo( + std::unique_ptr Impl) : TTIImpl(std::move(Impl)) {} bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) { @@ -1474,7 +1475,7 @@ void TargetTransformInfo::collectKernelLaunchBounds( return TTIImpl->collectKernelLaunchBounds(F, LB); } -TargetTransformInfo::Concept::~Concept() = default; +TargetTransformInfoImplBase::~TargetTransformInfoImplBase() = default; TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {} From c04273237d180a82a36f8c813c367d35b6274ee4 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Sat, 26 Apr 2025 14:30:44 +0300 Subject: [PATCH 4/4] Update code comments --- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 2 +- llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h | 2 +- llvm/lib/Target/ARC/ARCTargetTransformInfo.h | 2 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 2 +- llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h | 2 +- llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h | 2 +- llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h | 2 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h | 2 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 2 +- llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h | 2 +- llvm/lib/Target/VE/VETargetTransformInfo.h | 2 +- llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h | 2 +- llvm/lib/Target/X86/X86TargetTransformInfo.h | 2 +- llvm/lib/Target/XCore/XCoreTargetTransformInfo.h | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index 4bdf14d3372d6..adfaec0ea618b 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// AArch64 target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h index 1a27cb6f814d2..f6f7bd4bfcf5b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// AMDGPU target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h index 5be87c6d10299..f3128942a640b 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// R600 target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/ARC/ARCTargetTransformInfo.h b/llvm/lib/Target/ARC/ARCTargetTransformInfo.h index 24c0dd053efd8..bb7f2a0a459c2 100644 --- a/llvm/lib/Target/ARC/ARCTargetTransformInfo.h +++ b/llvm/lib/Target/ARC/ARCTargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // \file -// This file contains a TargetTransformInfo::Concept conforming object specific +// This file contains a TargetTransformInfoImplBase conforming object specific // to the ARC target machine. It uses the target's detailed information to // provide more precise answers to certain TTI queries, while letting the // target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index c94c56c195685..6f25f4a26e81b 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// ARM target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h index 3c005cd5bdb36..f17abf4c8af04 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h +++ b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file a TargetTransformInfo::Concept conforming object specific to the +// This file a TargetTransformInfoImplBase conforming object specific to the // Lanai target machine. It uses the target's detailed information to // provide more precise answers to certain TTI queries, while letting the // target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h index fdf57933cfdda..d43d2cb0eb124 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h +++ b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// LoongArch target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h index 324e4127e1013..182f9f5b55d9f 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// NVPTX target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h index c8eda22f847ad..9af432512407f 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// PPC target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 9a75431cee831..ca4c0ccd27a74 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file defines a TargetTransformInfo::Concept conforming object specific +/// This file defines a TargetTransformInfoImplBase conforming object specific /// to the RISC-V target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h b/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h index dbc8a35dd21e9..4bb8d8d16c394 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h +++ b/llvm/lib/Target/SPIRV/SPIRVTargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // \file -// This file contains a TargetTransformInfo::Concept conforming object specific +// This file contains a TargetTransformInfoImplBase conforming object specific // to the SPIRV target machine. It uses the target's detailed information to // provide more precise answers to certain TTI queries, while letting the // target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/VE/VETargetTransformInfo.h b/llvm/lib/Target/VE/VETargetTransformInfo.h index d27a66bdd6bd0..5cb0286087821 100644 --- a/llvm/lib/Target/VE/VETargetTransformInfo.h +++ b/llvm/lib/Target/VE/VETargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// VE target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h index 02b4c7c442aaf..75ecb97b37131 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// /// /// \file -/// This file a TargetTransformInfo::Concept conforming object specific +/// This file a TargetTransformInfoImplBase conforming object specific /// to the WebAssembly target machine. /// /// It uses the target's detailed information to provide more precise answers to diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index 64f552f7976ff..be2ede504f322 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// X86 target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. diff --git a/llvm/lib/Target/XCore/XCoreTargetTransformInfo.h b/llvm/lib/Target/XCore/XCoreTargetTransformInfo.h index 1f1325e4ca3bc..f2c10518109dc 100644 --- a/llvm/lib/Target/XCore/XCoreTargetTransformInfo.h +++ b/llvm/lib/Target/XCore/XCoreTargetTransformInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file a TargetTransformInfo::Concept conforming object specific to the +/// This file a TargetTransformInfoImplBase conforming object specific to the /// XCore target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest.