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[X86][GlobalIsel] support G_FABS #136718

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Merged
merged 16 commits into from
Jun 25, 2025
Merged

[X86][GlobalIsel] support G_FABS #136718

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d4475cb
[X86][GlobalIsel] support fabs for f80
Apr 22, 2025
22e2c83
add float and double
Apr 24, 2025
0ed32a7
update test
May 1, 2025
8221bc6
remove s8
May 1, 2025
6a58699
update fabs for f32 and f64
May 27, 2025
db0e1cb
fix indent
May 27, 2025
f35b674
add x87 specific runs
Jun 3, 2025
2782568
fix tst
Jun 5, 2025
860903d
remove unused marker
Jun 5, 2025
d4d3d44
fix clang format
Jun 7, 2025
4838b22
fix clang format
Jun 7, 2025
63eebe0
remove const pool
Jun 11, 2025
a718a5b
remove noise
Jun 11, 2025
e57ab03
add fallback
Jun 19, 2025
f5e5274
format extension issue
Jun 19, 2025
ac44b20
Merge branch 'main' into gisel_fabs
RKSimon Jun 25, 2025
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43 changes: 43 additions & 0 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -466,6 +466,10 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
(UseX87 && typeInSet(0, {s80})(Query));
});

getActionDefinitionsBuilder(G_FABS)
.legalFor(UseX87 && !HasSSE2, {s32, s64, s80})
.custom();

// fp comparison
getActionDefinitionsBuilder(G_FCMP)
.legalFor(HasSSE1 || UseX87, {s8, s32})
Expand Down Expand Up @@ -669,6 +673,8 @@ bool X86LegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
return legalizeSITOFP(MI, MRI, Helper);
case TargetOpcode::G_FPTOSI:
return legalizeFPTOSI(MI, MRI, Helper);
case TargetOpcode::G_FABS:
return legalizeFAbs(MI, MRI, Helper);
}
llvm_unreachable("expected switch to return");
}
Expand Down Expand Up @@ -835,6 +841,43 @@ bool X86LegalizerInfo::legalizeNarrowingStore(MachineInstr &MI,
return true;
}

bool X86LegalizerInfo::legalizeFAbs(MachineInstr &MI,
MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const {
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@RKSimon RKSimon Jun 6, 2025

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clang-format this ?


MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
Register SrcReg = MI.getOperand(1).getReg();
Register DstReg = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(DstReg);
if (Subtarget.is32Bit()) {
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@RKSimon RKSimon Jun 6, 2025

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I don't understand - why are you making x86_64 use a constant pool for all float types?

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@mahesh-attarde mahesh-attarde Jun 7, 2025

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For functionality of abs we are using mask, in 64 bit we have masks spans 64 bit. From ISA spec, we can only encode 32 bit immediate in instruction. so we need to load 64 bit into reg and then use reg.
Are you suggesting we only use it to double type?

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@e-kud e-kud Jun 10, 2025

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@mahesh-attarde I think SDAG uses constant pool because of working with xmm registers. When we don't have them we still do just a simple movabs: https://godbolt.org/z/966EGMWah

// Reset sign bit
MIRBuilder.buildAnd(
DstReg, SrcReg,
MIRBuilder.buildConstant(
Ty, APInt::getSignedMaxValue(Ty.getScalarSizeInBits())));
} else {
// In 64 bit mode, constant pool is used.
auto &MF = MIRBuilder.getMF();
Type *IRTy = getTypeForLLT(Ty, MF.getFunction().getContext());
Constant *ConstMask = ConstantInt::get(
IRTy, APInt::getSignedMaxValue(Ty.getScalarSizeInBits()));
LLT DstTy = MRI.getType(DstReg);
const DataLayout &DL = MIRBuilder.getDataLayout();
unsigned AddrSpace = DL.getDefaultGlobalsAddressSpace();
Align Alignment(DL.getABITypeAlign(
getTypeForLLT(DstTy, MF.getFunction().getContext())));
auto Addr = MIRBuilder.buildConstantPool(
LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)),
MF.getConstantPool()->getConstantPoolIndex(ConstMask, Alignment));
MachineMemOperand *MMO =
MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
MachineMemOperand::MOLoad, DstTy, Alignment);
auto LoadedMask = MIRBuilder.buildLoad(DstTy, Addr, *MMO);
MIRBuilder.buildAnd(DstReg, SrcReg, LoadedMask);
}
MI.eraseFromParent();
return true;
}
bool X86LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
return true;
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,8 @@ class X86LegalizerInfo : public LegalizerInfo {

bool legalizeFPTOSI(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
bool legalizeFAbs(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
};
} // namespace llvm
#endif
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/X86/isel-fabs-x87.ll
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Original file line number Diff line number Diff line change
@@ -1,8 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=X86
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@RKSimon RKSimon Jun 11, 2025

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can we add f32/f64 test coverage here? otherwise we've lost all x87-only fabs tests

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@mahesh-attarde mahesh-attarde Jun 12, 2025

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This is known issue, we discussed it earlier while submitting test review.
#142558 (comment)

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@e-kud e-kud Jun 13, 2025

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We can store the value instead of returning.

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@mahesh-attarde mahesh-attarde Jun 19, 2025

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done


define x86_fp80 @test_x86_fp80_abs(x86_fp80 %arg) {
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@e-kud e-kud Jun 11, 2025

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Probably would be nice to see how we handle floats and double without SSE.

; X64-LABEL: test_x86_fp80_abs:
Expand Down
42 changes: 41 additions & 1 deletion llvm/test/CodeGen/X86/isel-fabs.ll
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Original file line number Diff line number Diff line change
@@ -1,16 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87 -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X64
; RUN: llc < %s -mtriple=i686-- -mattr=-x87 | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=i686-- -mattr=-x87 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=FASTISEL-X86

; RUN: llc < %s -mtriple=i686-- -mattr=-x87 -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X86

define float @test_float_abs(float %arg) {
; SDAG-X64-LABEL: test_float_abs:
; SDAG-X64: # %bb.0:
; SDAG-X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SDAG-X64-NEXT: retq
;
; X64-LABEL: test_float_abs:
; X64: # %bb.0:
; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
;
; GISEL-X64-LABEL: test_float_abs:
; GISEL-X64: # %bb.0:
; GISEL-X64-NEXT: movd %xmm0, %eax
; GISEL-X64-NEXT: andl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax
; GISEL-X64-NEXT: movd %eax, %xmm0
; GISEL-X64-NEXT: retq
;
; X86-LABEL: test_float_abs:
; X86: # %bb.0:
; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
Expand All @@ -22,16 +35,34 @@ define float @test_float_abs(float %arg) {
; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; FASTISEL-X86-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; FASTISEL-X86-NEXT: retl
;
; GISEL-X86-LABEL: test_float_abs:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
%abs = tail call float @llvm.fabs.f32(float %arg)
ret float %abs
}

define double @test_double_abs(double %arg) {
; SDAG-X64-LABEL: test_double_abs:
; SDAG-X64: # %bb.0:
; SDAG-X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SDAG-X64-NEXT: retq
;
; X64-LABEL: test_double_abs:
; X64: # %bb.0:
; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
;
; GISEL-X64-LABEL: test_double_abs:
; GISEL-X64: # %bb.0:
; GISEL-X64-NEXT: movq %xmm0, %rax
; GISEL-X64-NEXT: andq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %rax
; GISEL-X64-NEXT: movq %rax, %xmm0
; GISEL-X64-NEXT: retq
;
; X86-LABEL: test_double_abs:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand All @@ -45,6 +76,15 @@ define double @test_double_abs(double %arg) {
; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; FASTISEL-X86-NEXT: andl $2147483647, %edx # imm = 0x7FFFFFFF
; FASTISEL-X86-NEXT: retl
;
; GISEL-X86-LABEL: test_double_abs:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl $-1, %eax
; GISEL-X86-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl

%abs = tail call double @llvm.fabs.f64(double %arg)
ret double %abs
}
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