[RISCV] Add Andes A45/AX45 processor definition #136832
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Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline linux-capable CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for A45/AX45: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a45/ https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45/ Scheduling model will be implemented in a later PR.
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@llvm/pr-subscribers-clang @llvm/pr-subscribers-backend-risc-v Author: Jim Lin (tclin914) ChangesAndes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline linux-capable CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for A45/AX45: Scheduling model will be implemented in a later PR. Full diff: https://github.com/llvm/llvm-project/pull/136832.diff 4 Files Affected:
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 19da8ede26a40..bb3a9d38be673 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -726,3 +726,37 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck -check-prefix=MTUNE-ANDES-NX45 %s
// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a45 | FileCheck -check-prefix=MCPU-ANDES-A45 %s
+// MCPU-ANDES-A45: "-target-cpu" "andes-a45"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-A45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-A45-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a45 | FileCheck -check-prefix=MTUNE-ANDES-A45 %s
+// MTUNE-ANDES-A45: "-tune-cpu" "andes-a45"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax45 | FileCheck -check-prefix=MCPU-ANDES-AX45 %s
+// MCPU-ANDES-AX45: "-target-cpu" "andes-ax45"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+m"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+a"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+f"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+d"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+c"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zicsr"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zifencei"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zba"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbb"
+// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbs"
+// MCPU-ANDES-AX45-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax45 | FileCheck -check-prefix=MTUNE-ANDES-AX45 %s
+// MTUNE-ANDES-AX45: "-tune-cpu" "andes-ax45"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index cd8a8bf95dd7a..f0c4173e18022 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -5,7 +5,8 @@
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
// RISCV32-NEXT: note: valid target CPU values are:
-// RISCV32-SAME: {{^}} andes-n45
+// RISCV32-SAME: {{^}} andes-a45
+// RISCV32-SAME: {{^}}, andes-n45
// RISCV32-SAME: {{^}}, generic-rv32
// RISCV32-SAME: {{^}}, rocket-rv32
// RISCV32-SAME: {{^}}, rp2350-hazard3
@@ -25,7 +26,8 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
// RISCV64-NEXT: note: valid target CPU values are:
-// RISCV64-SAME: {{^}} andes-nx45
+// RISCV64-SAME: {{^}} andes-ax45
+// RISCV64-SAME: {{^}}, andes-nx45
// RISCV64-SAME: {{^}}, generic-rv64
// RISCV64-SAME: {{^}}, mips-p8700
// RISCV64-SAME: {{^}}, rocket-rv64
@@ -54,7 +56,8 @@
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV32-NEXT: note: valid target CPU values are:
-// TUNE-RISCV32-SAME: {{^}} andes-n45
+// TUNE-RISCV32-SAME: {{^}} andes-a45
+// TUNE-RISCV32-SAME: {{^}}, andes-n45
// TUNE-RISCV32-SAME: {{^}}, generic-rv32
// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
// TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
@@ -78,7 +81,8 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV64-NEXT: note: valid target CPU values are:
-// TUNE-RISCV64-SAME: {{^}} andes-nx45
+// TUNE-RISCV64-SAME: {{^}} andes-ax45
+// TUNE-RISCV64-SAME: {{^}}, andes-nx45
// TUNE-RISCV64-SAME: {{^}}, generic-rv64
// TUNE-RISCV64-SAME: {{^}}, mips-p8700
// TUNE-RISCV64-SAME: {{^}}, rocket-rv64
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index a3f91224ca24e..63ca70e0acbbc 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -169,6 +169,7 @@ Changes to the RISC-V Backend
which is also the default.
* `-mcpu=xiangshan-kunminghu` was added.
* `-mcpu=andes-n45` and `-mcpu=andes-nx45` were added.
+* `-mcpu=andes-a45` and `-mcpu=andes-ax45` were added.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 5e52ba87cb346..1ad94228bcbaa 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -651,3 +651,29 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB]>;
+
+def ANDES_A45 : RISCVProcessorModel<"andes-a45",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtB]>;
+
+def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtB]>;
|
IanWood1
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May 6, 2025
Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline linux-capable CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for A45/AX45: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a45/ https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45/ Scheduling model will be implemented in a later PR.
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Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline linux-capable CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider.
The overviews for A45/AX45:
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a45/
https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45/
Scheduling model will be implemented in a later PR.