diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index bdebd842b011c..03364d9025208 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1221,8 +1221,10 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::ROTR, VT, Expand); } setOperationAction(ISD::CTTZ, MVT::i32, Custom); - setOperationAction(ISD::CTPOP, MVT::i32, LibCall); - setOperationAction(ISD::CTPOP, MVT::i64, LibCall); + // TODO: These two should be set to LibCall, but this currently breaks + // the Linux kernel build. See #101786. + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i64, Expand); if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) { setOperationAction(ISD::CTLZ, MVT::i32, Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 099ba5c9943ac..02451ee716865 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -396,11 +396,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom); } else { setOperationAction(ISD::CTTZ, XLenVT, Expand); + // TODO: These should be set to LibCall, but this currently breaks + // the Linux kernel build. See #101786. Lacks i128 tests, too. if (Subtarget.is64Bit()) - setOperationAction(ISD::CTPOP, MVT::i128, LibCall); + setOperationAction(ISD::CTPOP, MVT::i128, Expand); else - setOperationAction(ISD::CTPOP, MVT::i32, LibCall); - setOperationAction(ISD::CTPOP, MVT::i64, LibCall); + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i64, Expand); } if (Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() || diff --git a/llvm/test/CodeGen/ARM/popcnt.ll b/llvm/test/CodeGen/ARM/popcnt.ll index fc4387320ef77..a70fdc580ca9b 100644 --- a/llvm/test/CodeGen/ARM/popcnt.ll +++ b/llvm/test/CodeGen/ARM/popcnt.ll @@ -324,7 +324,30 @@ define i32 @ctpop16(i16 %x) nounwind readnone { define i32 @ctpop32(i32 %x) nounwind readnone { ; CHECK-LABEL: ctpop32: ; CHECK: @ %bb.0: -; CHECK-NEXT: b __popcountsi2 +; CHECK-NEXT: ldr r1, .LCPI22_0 +; CHECK-NEXT: ldr r2, .LCPI22_3 +; CHECK-NEXT: and r1, r1, r0, lsr #1 +; CHECK-NEXT: ldr r12, .LCPI22_1 +; CHECK-NEXT: sub r0, r0, r1 +; CHECK-NEXT: ldr r3, .LCPI22_2 +; CHECK-NEXT: and r1, r0, r2 +; CHECK-NEXT: and r0, r2, r0, lsr #2 +; CHECK-NEXT: add r0, r1, r0 +; CHECK-NEXT: add r0, r0, r0, lsr #4 +; CHECK-NEXT: and r0, r0, r12 +; CHECK-NEXT: mul r1, r0, r3 +; CHECK-NEXT: lsr r0, r1, #24 +; CHECK-NEXT: mov pc, lr +; CHECK-NEXT: .p2align 2 +; CHECK-NEXT: @ %bb.1: +; CHECK-NEXT: .LCPI22_0: +; CHECK-NEXT: .long 1431655765 @ 0x55555555 +; CHECK-NEXT: .LCPI22_1: +; CHECK-NEXT: .long 252645135 @ 0xf0f0f0f +; CHECK-NEXT: .LCPI22_2: +; CHECK-NEXT: .long 16843009 @ 0x1010101 +; CHECK-NEXT: .LCPI22_3: +; CHECK-NEXT: .long 858993459 @ 0x33333333 %count = tail call i32 @llvm.ctpop.i32(i32 %x) ret i32 %count } @@ -332,12 +355,43 @@ define i32 @ctpop32(i32 %x) nounwind readnone { define i64 @ctpop64(i64 %x) nounwind readnone { ; CHECK-LABEL: ctpop64: ; CHECK: @ %bb.0: -; CHECK-NEXT: .save {r11, lr} -; CHECK-NEXT: push {r11, lr} -; CHECK-NEXT: bl __popcountdi2 -; CHECK-NEXT: asr r1, r0, #31 -; CHECK-NEXT: pop {r11, lr} +; CHECK-NEXT: .save {r4, lr} +; CHECK-NEXT: push {r4, lr} +; CHECK-NEXT: ldr r2, .LCPI23_0 +; CHECK-NEXT: ldr r3, .LCPI23_3 +; CHECK-NEXT: and r4, r2, r0, lsr #1 +; CHECK-NEXT: and r2, r2, r1, lsr #1 +; CHECK-NEXT: sub r0, r0, r4 +; CHECK-NEXT: sub r1, r1, r2 +; CHECK-NEXT: and r4, r0, r3 +; CHECK-NEXT: and r2, r1, r3 +; CHECK-NEXT: and r0, r3, r0, lsr #2 +; CHECK-NEXT: and r1, r3, r1, lsr #2 +; CHECK-NEXT: add r0, r4, r0 +; CHECK-NEXT: ldr lr, .LCPI23_1 +; CHECK-NEXT: add r1, r2, r1 +; CHECK-NEXT: ldr r12, .LCPI23_2 +; CHECK-NEXT: add r0, r0, r0, lsr #4 +; CHECK-NEXT: and r0, r0, lr +; CHECK-NEXT: add r1, r1, r1, lsr #4 +; CHECK-NEXT: mul r2, r0, r12 +; CHECK-NEXT: and r0, r1, lr +; CHECK-NEXT: mul r1, r0, r12 +; CHECK-NEXT: lsr r0, r2, #24 +; CHECK-NEXT: add r0, r0, r1, lsr #24 +; CHECK-NEXT: mov r1, #0 +; CHECK-NEXT: pop {r4, lr} ; CHECK-NEXT: mov pc, lr +; CHECK-NEXT: .p2align 2 +; CHECK-NEXT: @ %bb.1: +; CHECK-NEXT: .LCPI23_0: +; CHECK-NEXT: .long 1431655765 @ 0x55555555 +; CHECK-NEXT: .LCPI23_1: +; CHECK-NEXT: .long 252645135 @ 0xf0f0f0f +; CHECK-NEXT: .LCPI23_2: +; CHECK-NEXT: .long 16843009 @ 0x1010101 +; CHECK-NEXT: .LCPI23_3: +; CHECK-NEXT: .long 858993459 @ 0x33333333 %count = tail call i64 @llvm.ctpop.i64(i64 %x) ret i64 %count } diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll index f8c3a75f844db..a46168f114bb9 100644 --- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll +++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll @@ -1156,30 +1156,46 @@ define i16 @test_ctlz_i16(i16 %a) nounwind { } define i32 @test_ctlz_i32(i32 %a) nounwind { -; RV32_NOZBB-LABEL: test_ctlz_i32: -; RV32_NOZBB: # %bb.0: -; RV32_NOZBB-NEXT: beqz a0, .LBB10_2 -; RV32_NOZBB-NEXT: # %bb.1: # %cond.false -; RV32_NOZBB-NEXT: addi sp, sp, -16 -; RV32_NOZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32_NOZBB-NEXT: srli a1, a0, 1 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 2 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 4 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 8 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 16 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: not a0, a0 -; RV32_NOZBB-NEXT: call __popcountsi2 -; RV32_NOZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32_NOZBB-NEXT: addi sp, sp, 16 -; RV32_NOZBB-NEXT: ret -; RV32_NOZBB-NEXT: .LBB10_2: -; RV32_NOZBB-NEXT: li a0, 32 -; RV32_NOZBB-NEXT: ret +; RV32I-LABEL: test_ctlz_i32: +; RV32I: # %bb.0: +; RV32I-NEXT: beqz a0, .LBB10_2 +; RV32I-NEXT: # %bb.1: # %cond.false +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: addi a1, a2, 1365 +; RV32I-NEXT: srli a2, a0, 2 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 4 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 8 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 16 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: srli a2, a0, 1 +; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: lui a2, 209715 +; RV32I-NEXT: addi a2, a2, 819 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: lui a2, 61681 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: addi a1, a2, -241 +; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB10_2: +; RV32I-NEXT: li a0, 32 +; RV32I-NEXT: ret ; ; RV64I-LABEL: test_ctlz_i32: ; RV64I: # %bb.0: @@ -1223,6 +1239,46 @@ define i32 @test_ctlz_i32(i32 %a) nounwind { ; RV64I-NEXT: li a0, 32 ; RV64I-NEXT: ret ; +; RV32M-LABEL: test_ctlz_i32: +; RV32M: # %bb.0: +; RV32M-NEXT: beqz a0, .LBB10_2 +; RV32M-NEXT: # %bb.1: # %cond.false +; RV32M-NEXT: srli a1, a0, 1 +; RV32M-NEXT: lui a2, 349525 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: addi a1, a2, 1365 +; RV32M-NEXT: srli a2, a0, 2 +; RV32M-NEXT: or a0, a0, a2 +; RV32M-NEXT: srli a2, a0, 4 +; RV32M-NEXT: or a0, a0, a2 +; RV32M-NEXT: srli a2, a0, 8 +; RV32M-NEXT: or a0, a0, a2 +; RV32M-NEXT: srli a2, a0, 16 +; RV32M-NEXT: or a0, a0, a2 +; RV32M-NEXT: not a0, a0 +; RV32M-NEXT: srli a2, a0, 1 +; RV32M-NEXT: and a1, a2, a1 +; RV32M-NEXT: lui a2, 209715 +; RV32M-NEXT: addi a2, a2, 819 +; RV32M-NEXT: sub a0, a0, a1 +; RV32M-NEXT: and a1, a0, a2 +; RV32M-NEXT: srli a0, a0, 2 +; RV32M-NEXT: and a0, a0, a2 +; RV32M-NEXT: lui a2, 61681 +; RV32M-NEXT: add a0, a1, a0 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: add a0, a0, a1 +; RV32M-NEXT: lui a1, 4112 +; RV32M-NEXT: addi a2, a2, -241 +; RV32M-NEXT: and a0, a0, a2 +; RV32M-NEXT: addi a1, a1, 257 +; RV32M-NEXT: mul a0, a0, a1 +; RV32M-NEXT: srli a0, a0, 24 +; RV32M-NEXT: ret +; RV32M-NEXT: .LBB10_2: +; RV32M-NEXT: li a0, 32 +; RV32M-NEXT: ret +; ; RV64M-LABEL: test_ctlz_i32: ; RV64M: # %bb.0: ; RV64M-NEXT: sext.w a1, a0 @@ -1290,75 +1346,240 @@ define i32 @test_ctlz_i32(i32 %a) nounwind { } define i64 @test_ctlz_i64(i64 %a) nounwind { -; RV32_NOZBB-LABEL: test_ctlz_i64: -; RV32_NOZBB: # %bb.0: -; RV32_NOZBB-NEXT: addi sp, sp, -16 -; RV32_NOZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32_NOZBB-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32_NOZBB-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32_NOZBB-NEXT: mv s1, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 1 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 2 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 4 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 8 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 16 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: not a0, a0 -; RV32_NOZBB-NEXT: call __popcountsi2 -; RV32_NOZBB-NEXT: mv s0, a0 -; RV32_NOZBB-NEXT: srli a0, s1, 1 -; RV32_NOZBB-NEXT: or a0, s1, a0 -; RV32_NOZBB-NEXT: srli a1, a0, 2 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 4 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 8 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 16 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: not a0, a0 -; RV32_NOZBB-NEXT: call __popcountsi2 -; RV32_NOZBB-NEXT: bnez s1, .LBB11_2 -; RV32_NOZBB-NEXT: # %bb.1: -; RV32_NOZBB-NEXT: addi a0, s0, 32 -; RV32_NOZBB-NEXT: .LBB11_2: -; RV32_NOZBB-NEXT: li a1, 0 -; RV32_NOZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32_NOZBB-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32_NOZBB-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32_NOZBB-NEXT: addi sp, sp, 16 -; RV32_NOZBB-NEXT: ret +; RV32I-LABEL: test_ctlz_i64: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: lui a3, 209715 +; RV32I-NEXT: lui a5, 61681 +; RV32I-NEXT: addi a4, a2, 1365 +; RV32I-NEXT: addi a3, a3, 819 +; RV32I-NEXT: addi a2, a5, -241 +; RV32I-NEXT: bnez a1, .LBB11_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 2 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 8 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 16 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: addi a0, a0, 32 +; RV32I-NEXT: li a1, 0 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB11_2: +; RV32I-NEXT: srli a0, a1, 1 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 2 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 8 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 16 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: li a1, 0 +; RV32I-NEXT: ret ; -; RV64NOZBB-LABEL: test_ctlz_i64: -; RV64NOZBB: # %bb.0: -; RV64NOZBB-NEXT: beqz a0, .LBB11_2 -; RV64NOZBB-NEXT: # %bb.1: # %cond.false -; RV64NOZBB-NEXT: addi sp, sp, -16 -; RV64NOZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64NOZBB-NEXT: srli a1, a0, 1 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 2 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 4 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 8 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 16 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 32 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: not a0, a0 -; RV64NOZBB-NEXT: call __popcountdi2 -; RV64NOZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64NOZBB-NEXT: addi sp, sp, 16 -; RV64NOZBB-NEXT: ret -; RV64NOZBB-NEXT: .LBB11_2: -; RV64NOZBB-NEXT: li a0, 64 -; RV64NOZBB-NEXT: ret +; RV64I-LABEL: test_ctlz_i64: +; RV64I: # %bb.0: +; RV64I-NEXT: beqz a0, .LBB11_2 +; RV64I-NEXT: # %bb.1: # %cond.false +; RV64I-NEXT: srli a1, a0, 1 +; RV64I-NEXT: lui a2, 349525 +; RV64I-NEXT: lui a3, 209715 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addiw a2, a3, 819 +; RV64I-NEXT: srli a3, a0, 2 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: slli a3, a1, 32 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: slli a3, a2, 32 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: srli a3, a0, 4 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 8 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 16 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 32 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: not a0, a0 +; RV64I-NEXT: srli a3, a0, 1 +; RV64I-NEXT: and a1, a3, a1 +; RV64I-NEXT: lui a3, 61681 +; RV64I-NEXT: addiw a3, a3, -241 +; RV64I-NEXT: sub a0, a0, a1 +; RV64I-NEXT: and a1, a0, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a2, a3, 32 +; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: srli a1, a0, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a3, a2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a1, a0, 8 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 16 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 32 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: srli a0, a0, 56 +; RV64I-NEXT: ret +; RV64I-NEXT: .LBB11_2: +; RV64I-NEXT: li a0, 64 +; RV64I-NEXT: ret +; +; RV32M-LABEL: test_ctlz_i64: +; RV32M: # %bb.0: +; RV32M-NEXT: lui a2, 349525 +; RV32M-NEXT: lui a3, 209715 +; RV32M-NEXT: lui a6, 61681 +; RV32M-NEXT: lui a7, 4112 +; RV32M-NEXT: addi a5, a2, 1365 +; RV32M-NEXT: addi a4, a3, 819 +; RV32M-NEXT: addi a3, a6, -241 +; RV32M-NEXT: addi a2, a7, 257 +; RV32M-NEXT: bnez a1, .LBB11_2 +; RV32M-NEXT: # %bb.1: +; RV32M-NEXT: srli a1, a0, 1 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 2 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 8 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 16 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: not a0, a0 +; RV32M-NEXT: srli a1, a0, 1 +; RV32M-NEXT: and a1, a1, a5 +; RV32M-NEXT: sub a0, a0, a1 +; RV32M-NEXT: and a1, a0, a4 +; RV32M-NEXT: srli a0, a0, 2 +; RV32M-NEXT: and a0, a0, a4 +; RV32M-NEXT: add a0, a1, a0 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: add a0, a0, a1 +; RV32M-NEXT: and a0, a0, a3 +; RV32M-NEXT: mul a0, a0, a2 +; RV32M-NEXT: srli a0, a0, 24 +; RV32M-NEXT: addi a0, a0, 32 +; RV32M-NEXT: li a1, 0 +; RV32M-NEXT: ret +; RV32M-NEXT: .LBB11_2: +; RV32M-NEXT: srli a0, a1, 1 +; RV32M-NEXT: or a0, a1, a0 +; RV32M-NEXT: srli a1, a0, 2 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 8 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 16 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: not a0, a0 +; RV32M-NEXT: srli a1, a0, 1 +; RV32M-NEXT: and a1, a1, a5 +; RV32M-NEXT: sub a0, a0, a1 +; RV32M-NEXT: and a1, a0, a4 +; RV32M-NEXT: srli a0, a0, 2 +; RV32M-NEXT: and a0, a0, a4 +; RV32M-NEXT: add a0, a1, a0 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: add a0, a0, a1 +; RV32M-NEXT: and a0, a0, a3 +; RV32M-NEXT: mul a0, a0, a2 +; RV32M-NEXT: srli a0, a0, 24 +; RV32M-NEXT: li a1, 0 +; RV32M-NEXT: ret +; +; RV64M-LABEL: test_ctlz_i64: +; RV64M: # %bb.0: +; RV64M-NEXT: beqz a0, .LBB11_2 +; RV64M-NEXT: # %bb.1: # %cond.false +; RV64M-NEXT: srli a1, a0, 1 +; RV64M-NEXT: lui a2, 349525 +; RV64M-NEXT: lui a3, 209715 +; RV64M-NEXT: lui a4, 61681 +; RV64M-NEXT: or a0, a0, a1 +; RV64M-NEXT: addiw a1, a2, 1365 +; RV64M-NEXT: addiw a2, a3, 819 +; RV64M-NEXT: addiw a3, a4, -241 +; RV64M-NEXT: srli a4, a0, 2 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: slli a4, a1, 32 +; RV64M-NEXT: add a1, a1, a4 +; RV64M-NEXT: slli a4, a2, 32 +; RV64M-NEXT: add a2, a2, a4 +; RV64M-NEXT: slli a4, a3, 32 +; RV64M-NEXT: add a3, a3, a4 +; RV64M-NEXT: srli a4, a0, 4 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: srli a4, a0, 8 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: srli a4, a0, 16 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: srli a4, a0, 32 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: not a0, a0 +; RV64M-NEXT: srli a4, a0, 1 +; RV64M-NEXT: and a1, a4, a1 +; RV64M-NEXT: sub a0, a0, a1 +; RV64M-NEXT: and a1, a0, a2 +; RV64M-NEXT: srli a0, a0, 2 +; RV64M-NEXT: and a0, a0, a2 +; RV64M-NEXT: lui a2, 4112 +; RV64M-NEXT: addiw a2, a2, 257 +; RV64M-NEXT: add a0, a1, a0 +; RV64M-NEXT: srli a1, a0, 4 +; RV64M-NEXT: add a0, a0, a1 +; RV64M-NEXT: slli a1, a2, 32 +; RV64M-NEXT: and a0, a0, a3 +; RV64M-NEXT: add a1, a2, a1 +; RV64M-NEXT: mul a0, a0, a1 +; RV64M-NEXT: srli a0, a0, 56 +; RV64M-NEXT: ret +; RV64M-NEXT: .LBB11_2: +; RV64M-NEXT: li a0, 64 +; RV64M-NEXT: ret ; ; RV32ZBB-LABEL: test_ctlz_i64: ; RV32ZBB: # %bb.0: @@ -1572,20 +1793,41 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind { } define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind { -; RV32_NOZBB-LABEL: test_ctlz_i32_zero_undef: -; RV32_NOZBB: # %bb.0: -; RV32_NOZBB-NEXT: srli a1, a0, 1 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 2 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 4 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 8 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 16 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: not a0, a0 -; RV32_NOZBB-NEXT: tail __popcountsi2 +; RV32I-LABEL: test_ctlz_i32_zero_undef: +; RV32I: # %bb.0: +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: addi a1, a2, 1365 +; RV32I-NEXT: srli a2, a0, 2 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 4 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 8 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 16 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: srli a2, a0, 1 +; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: lui a2, 209715 +; RV32I-NEXT: addi a2, a2, 819 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: lui a2, 61681 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: addi a1, a2, -241 +; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: ret ; ; RV64I-LABEL: test_ctlz_i32_zero_undef: ; RV64I: # %bb.0: @@ -1623,6 +1865,41 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind { ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ret ; +; RV32M-LABEL: test_ctlz_i32_zero_undef: +; RV32M: # %bb.0: +; RV32M-NEXT: srli a1, a0, 1 +; RV32M-NEXT: lui a2, 349525 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: addi a1, a2, 1365 +; RV32M-NEXT: srli a2, a0, 2 +; RV32M-NEXT: or a0, a0, a2 +; RV32M-NEXT: srli a2, a0, 4 +; RV32M-NEXT: or a0, a0, a2 +; RV32M-NEXT: srli a2, a0, 8 +; RV32M-NEXT: or a0, a0, a2 +; RV32M-NEXT: srli a2, a0, 16 +; RV32M-NEXT: or a0, a0, a2 +; RV32M-NEXT: not a0, a0 +; RV32M-NEXT: srli a2, a0, 1 +; RV32M-NEXT: and a1, a2, a1 +; RV32M-NEXT: lui a2, 209715 +; RV32M-NEXT: addi a2, a2, 819 +; RV32M-NEXT: sub a0, a0, a1 +; RV32M-NEXT: and a1, a0, a2 +; RV32M-NEXT: srli a0, a0, 2 +; RV32M-NEXT: and a0, a0, a2 +; RV32M-NEXT: lui a2, 61681 +; RV32M-NEXT: add a0, a1, a0 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: add a0, a0, a1 +; RV32M-NEXT: lui a1, 4112 +; RV32M-NEXT: addi a2, a2, -241 +; RV32M-NEXT: and a0, a0, a2 +; RV32M-NEXT: addi a1, a1, 257 +; RV32M-NEXT: mul a0, a0, a1 +; RV32M-NEXT: srli a0, a0, 24 +; RV32M-NEXT: ret +; ; RV64M-LABEL: test_ctlz_i32_zero_undef: ; RV64M: # %bb.0: ; RV64M-NEXT: srliw a1, a0, 1 @@ -1684,70 +1961,230 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind { } define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind { -; RV32_NOZBB-LABEL: test_ctlz_i64_zero_undef: -; RV32_NOZBB: # %bb.0: -; RV32_NOZBB-NEXT: addi sp, sp, -16 -; RV32_NOZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32_NOZBB-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32_NOZBB-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32_NOZBB-NEXT: mv s1, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 1 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 2 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 4 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 8 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 16 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: not a0, a0 -; RV32_NOZBB-NEXT: call __popcountsi2 -; RV32_NOZBB-NEXT: mv s0, a0 -; RV32_NOZBB-NEXT: srli a0, s1, 1 -; RV32_NOZBB-NEXT: or a0, s1, a0 -; RV32_NOZBB-NEXT: srli a1, a0, 2 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 4 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 8 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: srli a1, a0, 16 -; RV32_NOZBB-NEXT: or a0, a0, a1 -; RV32_NOZBB-NEXT: not a0, a0 -; RV32_NOZBB-NEXT: call __popcountsi2 -; RV32_NOZBB-NEXT: bnez s1, .LBB15_2 -; RV32_NOZBB-NEXT: # %bb.1: -; RV32_NOZBB-NEXT: addi a0, s0, 32 -; RV32_NOZBB-NEXT: .LBB15_2: -; RV32_NOZBB-NEXT: li a1, 0 -; RV32_NOZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32_NOZBB-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32_NOZBB-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32_NOZBB-NEXT: addi sp, sp, 16 -; RV32_NOZBB-NEXT: ret +; RV32I-LABEL: test_ctlz_i64_zero_undef: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: lui a3, 209715 +; RV32I-NEXT: lui a5, 61681 +; RV32I-NEXT: addi a4, a2, 1365 +; RV32I-NEXT: addi a3, a3, 819 +; RV32I-NEXT: addi a2, a5, -241 +; RV32I-NEXT: bnez a1, .LBB15_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 2 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 8 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 16 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: addi a0, a0, 32 +; RV32I-NEXT: li a1, 0 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB15_2: +; RV32I-NEXT: srli a0, a1, 1 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 2 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 8 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: srli a1, a0, 16 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: not a0, a0 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: li a1, 0 +; RV32I-NEXT: ret ; -; RV64NOZBB-LABEL: test_ctlz_i64_zero_undef: -; RV64NOZBB: # %bb.0: -; RV64NOZBB-NEXT: addi sp, sp, -16 -; RV64NOZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64NOZBB-NEXT: srli a1, a0, 1 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 2 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 4 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 8 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 16 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: srli a1, a0, 32 -; RV64NOZBB-NEXT: or a0, a0, a1 -; RV64NOZBB-NEXT: not a0, a0 -; RV64NOZBB-NEXT: call __popcountdi2 -; RV64NOZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64NOZBB-NEXT: addi sp, sp, 16 -; RV64NOZBB-NEXT: ret +; RV64I-LABEL: test_ctlz_i64_zero_undef: +; RV64I: # %bb.0: +; RV64I-NEXT: srli a1, a0, 1 +; RV64I-NEXT: lui a2, 349525 +; RV64I-NEXT: lui a3, 209715 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addiw a2, a3, 819 +; RV64I-NEXT: srli a3, a0, 2 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: slli a3, a1, 32 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: slli a3, a2, 32 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: srli a3, a0, 4 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 8 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 16 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 32 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: not a0, a0 +; RV64I-NEXT: srli a3, a0, 1 +; RV64I-NEXT: and a1, a3, a1 +; RV64I-NEXT: lui a3, 61681 +; RV64I-NEXT: addiw a3, a3, -241 +; RV64I-NEXT: sub a0, a0, a1 +; RV64I-NEXT: and a1, a0, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a2, a3, 32 +; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: srli a1, a0, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a3, a2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a1, a0, 8 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 16 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 32 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: srli a0, a0, 56 +; RV64I-NEXT: ret +; +; RV32M-LABEL: test_ctlz_i64_zero_undef: +; RV32M: # %bb.0: +; RV32M-NEXT: lui a2, 349525 +; RV32M-NEXT: lui a3, 209715 +; RV32M-NEXT: lui a6, 61681 +; RV32M-NEXT: lui a7, 4112 +; RV32M-NEXT: addi a5, a2, 1365 +; RV32M-NEXT: addi a4, a3, 819 +; RV32M-NEXT: addi a3, a6, -241 +; RV32M-NEXT: addi a2, a7, 257 +; RV32M-NEXT: bnez a1, .LBB15_2 +; RV32M-NEXT: # %bb.1: +; RV32M-NEXT: srli a1, a0, 1 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 2 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 8 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 16 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: not a0, a0 +; RV32M-NEXT: srli a1, a0, 1 +; RV32M-NEXT: and a1, a1, a5 +; RV32M-NEXT: sub a0, a0, a1 +; RV32M-NEXT: and a1, a0, a4 +; RV32M-NEXT: srli a0, a0, 2 +; RV32M-NEXT: and a0, a0, a4 +; RV32M-NEXT: add a0, a1, a0 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: add a0, a0, a1 +; RV32M-NEXT: and a0, a0, a3 +; RV32M-NEXT: mul a0, a0, a2 +; RV32M-NEXT: srli a0, a0, 24 +; RV32M-NEXT: addi a0, a0, 32 +; RV32M-NEXT: li a1, 0 +; RV32M-NEXT: ret +; RV32M-NEXT: .LBB15_2: +; RV32M-NEXT: srli a0, a1, 1 +; RV32M-NEXT: or a0, a1, a0 +; RV32M-NEXT: srli a1, a0, 2 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 8 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: srli a1, a0, 16 +; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: not a0, a0 +; RV32M-NEXT: srli a1, a0, 1 +; RV32M-NEXT: and a1, a1, a5 +; RV32M-NEXT: sub a0, a0, a1 +; RV32M-NEXT: and a1, a0, a4 +; RV32M-NEXT: srli a0, a0, 2 +; RV32M-NEXT: and a0, a0, a4 +; RV32M-NEXT: add a0, a1, a0 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: add a0, a0, a1 +; RV32M-NEXT: and a0, a0, a3 +; RV32M-NEXT: mul a0, a0, a2 +; RV32M-NEXT: srli a0, a0, 24 +; RV32M-NEXT: li a1, 0 +; RV32M-NEXT: ret +; +; RV64M-LABEL: test_ctlz_i64_zero_undef: +; RV64M: # %bb.0: +; RV64M-NEXT: srli a1, a0, 1 +; RV64M-NEXT: lui a2, 349525 +; RV64M-NEXT: lui a3, 209715 +; RV64M-NEXT: lui a4, 61681 +; RV64M-NEXT: or a0, a0, a1 +; RV64M-NEXT: addiw a1, a2, 1365 +; RV64M-NEXT: addiw a2, a3, 819 +; RV64M-NEXT: addiw a3, a4, -241 +; RV64M-NEXT: srli a4, a0, 2 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: slli a4, a1, 32 +; RV64M-NEXT: add a1, a1, a4 +; RV64M-NEXT: slli a4, a2, 32 +; RV64M-NEXT: add a2, a2, a4 +; RV64M-NEXT: slli a4, a3, 32 +; RV64M-NEXT: add a3, a3, a4 +; RV64M-NEXT: srli a4, a0, 4 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: srli a4, a0, 8 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: srli a4, a0, 16 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: srli a4, a0, 32 +; RV64M-NEXT: or a0, a0, a4 +; RV64M-NEXT: not a0, a0 +; RV64M-NEXT: srli a4, a0, 1 +; RV64M-NEXT: and a1, a4, a1 +; RV64M-NEXT: sub a0, a0, a1 +; RV64M-NEXT: and a1, a0, a2 +; RV64M-NEXT: srli a0, a0, 2 +; RV64M-NEXT: and a0, a0, a2 +; RV64M-NEXT: lui a2, 4112 +; RV64M-NEXT: addiw a2, a2, 257 +; RV64M-NEXT: add a0, a1, a0 +; RV64M-NEXT: srli a1, a0, 4 +; RV64M-NEXT: add a0, a0, a1 +; RV64M-NEXT: slli a1, a2, 32 +; RV64M-NEXT: and a0, a0, a3 +; RV64M-NEXT: add a1, a2, a1 +; RV64M-NEXT: mul a0, a0, a1 +; RV64M-NEXT: srli a0, a0, 56 +; RV64M-NEXT: ret ; ; RV32ZBB-LABEL: test_ctlz_i64_zero_undef: ; RV32ZBB: # %bb.0: @@ -1959,9 +2396,30 @@ define i16 @test_ctpop_i16(i16 %a) nounwind { } define i32 @test_ctpop_i32(i32 %a) nounwind { -; RV32_NOZBB-LABEL: test_ctpop_i32: -; RV32_NOZBB: # %bb.0: -; RV32_NOZBB-NEXT: tail __popcountsi2 +; RV32I-LABEL: test_ctpop_i32: +; RV32I: # %bb.0: +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: lui a2, 209715 +; RV32I-NEXT: addi a2, a2, 819 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: lui a2, 61681 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: addi a1, a2, -241 +; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: ret ; ; RV64I-LABEL: test_ctpop_i32: ; RV64I: # %bb.0: @@ -1988,6 +2446,30 @@ define i32 @test_ctpop_i32(i32 %a) nounwind { ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: ret ; +; RV32M-LABEL: test_ctpop_i32: +; RV32M: # %bb.0: +; RV32M-NEXT: srli a1, a0, 1 +; RV32M-NEXT: lui a2, 349525 +; RV32M-NEXT: addi a2, a2, 1365 +; RV32M-NEXT: and a1, a1, a2 +; RV32M-NEXT: lui a2, 209715 +; RV32M-NEXT: addi a2, a2, 819 +; RV32M-NEXT: sub a0, a0, a1 +; RV32M-NEXT: and a1, a0, a2 +; RV32M-NEXT: srli a0, a0, 2 +; RV32M-NEXT: and a0, a0, a2 +; RV32M-NEXT: lui a2, 61681 +; RV32M-NEXT: add a0, a1, a0 +; RV32M-NEXT: srli a1, a0, 4 +; RV32M-NEXT: add a0, a0, a1 +; RV32M-NEXT: lui a1, 4112 +; RV32M-NEXT: addi a2, a2, -241 +; RV32M-NEXT: and a0, a0, a2 +; RV32M-NEXT: addi a1, a1, 257 +; RV32M-NEXT: mul a0, a0, a1 +; RV32M-NEXT: srli a0, a0, 24 +; RV32M-NEXT: ret +; ; RV64M-LABEL: test_ctpop_i32: ; RV64M: # %bb.0: ; RV64M-NEXT: srli a1, a0, 1 @@ -2024,7 +2506,28 @@ define i32 @test_ctpop_i32(i32 %a) nounwind { ; ; RV32XTHEADBB-LABEL: test_ctpop_i32: ; RV32XTHEADBB: # %bb.0: -; RV32XTHEADBB-NEXT: tail __popcountsi2 +; RV32XTHEADBB-NEXT: srli a1, a0, 1 +; RV32XTHEADBB-NEXT: lui a2, 349525 +; RV32XTHEADBB-NEXT: addi a2, a2, 1365 +; RV32XTHEADBB-NEXT: and a1, a1, a2 +; RV32XTHEADBB-NEXT: lui a2, 209715 +; RV32XTHEADBB-NEXT: addi a2, a2, 819 +; RV32XTHEADBB-NEXT: sub a0, a0, a1 +; RV32XTHEADBB-NEXT: and a1, a0, a2 +; RV32XTHEADBB-NEXT: srli a0, a0, 2 +; RV32XTHEADBB-NEXT: and a0, a0, a2 +; RV32XTHEADBB-NEXT: lui a2, 61681 +; RV32XTHEADBB-NEXT: add a0, a1, a0 +; RV32XTHEADBB-NEXT: srli a1, a0, 4 +; RV32XTHEADBB-NEXT: add a0, a0, a1 +; RV32XTHEADBB-NEXT: addi a1, a2, -241 +; RV32XTHEADBB-NEXT: and a0, a0, a1 +; RV32XTHEADBB-NEXT: slli a1, a0, 8 +; RV32XTHEADBB-NEXT: add a0, a0, a1 +; RV32XTHEADBB-NEXT: slli a1, a0, 16 +; RV32XTHEADBB-NEXT: add a0, a0, a1 +; RV32XTHEADBB-NEXT: srli a0, a0, 24 +; RV32XTHEADBB-NEXT: ret ; ; RV64XTHEADBB-LABEL: test_ctpop_i32: ; RV64XTHEADBB: # %bb.0: @@ -2055,24 +2558,150 @@ define i32 @test_ctpop_i32(i32 %a) nounwind { } define i64 @test_ctpop_i64(i64 %a) nounwind { -; RV32_NOZBB-LABEL: test_ctpop_i64: -; RV32_NOZBB: # %bb.0: -; RV32_NOZBB-NEXT: addi sp, sp, -16 -; RV32_NOZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32_NOZBB-NEXT: call __popcountdi2 -; RV32_NOZBB-NEXT: srai a1, a0, 31 -; RV32_NOZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32_NOZBB-NEXT: addi sp, sp, 16 -; RV32_NOZBB-NEXT: ret +; RV32I-LABEL: test_ctpop_i64: +; RV32I: # %bb.0: +; RV32I-NEXT: srli a2, a1, 1 +; RV32I-NEXT: lui a3, 349525 +; RV32I-NEXT: lui a4, 209715 +; RV32I-NEXT: srli a5, a0, 1 +; RV32I-NEXT: addi a3, a3, 1365 +; RV32I-NEXT: and a2, a2, a3 +; RV32I-NEXT: and a3, a5, a3 +; RV32I-NEXT: lui a5, 61681 +; RV32I-NEXT: addi a4, a4, 819 +; RV32I-NEXT: addi a5, a5, -241 +; RV32I-NEXT: sub a1, a1, a2 +; RV32I-NEXT: sub a0, a0, a3 +; RV32I-NEXT: and a2, a1, a4 +; RV32I-NEXT: srli a1, a1, 2 +; RV32I-NEXT: and a3, a0, a4 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: and a0, a0, a4 +; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: add a0, a3, a0 +; RV32I-NEXT: srli a2, a1, 4 +; RV32I-NEXT: srli a3, a0, 4 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: add a0, a0, a3 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: and a0, a0, a5 +; RV32I-NEXT: slli a2, a1, 8 +; RV32I-NEXT: slli a3, a0, 8 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: add a0, a0, a3 +; RV32I-NEXT: slli a2, a1, 16 +; RV32I-NEXT: slli a3, a0, 16 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: add a0, a0, a3 +; RV32I-NEXT: srli a1, a1, 24 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: li a1, 0 +; RV32I-NEXT: ret ; -; RV64NOZBB-LABEL: test_ctpop_i64: -; RV64NOZBB: # %bb.0: -; RV64NOZBB-NEXT: addi sp, sp, -16 -; RV64NOZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64NOZBB-NEXT: call __popcountdi2 -; RV64NOZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64NOZBB-NEXT: addi sp, sp, 16 -; RV64NOZBB-NEXT: ret +; RV64I-LABEL: test_ctpop_i64: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a1, 349525 +; RV64I-NEXT: lui a2, 209715 +; RV64I-NEXT: addiw a1, a1, 1365 +; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: slli a3, a1, 32 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: slli a3, a2, 32 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: srli a3, a0, 1 +; RV64I-NEXT: and a1, a3, a1 +; RV64I-NEXT: lui a3, 61681 +; RV64I-NEXT: addiw a3, a3, -241 +; RV64I-NEXT: sub a0, a0, a1 +; RV64I-NEXT: and a1, a0, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a2, a3, 32 +; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: srli a1, a0, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a3, a2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a1, a0, 8 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 16 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 32 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: srli a0, a0, 56 +; RV64I-NEXT: ret +; +; RV32M-LABEL: test_ctpop_i64: +; RV32M: # %bb.0: +; RV32M-NEXT: srli a2, a1, 1 +; RV32M-NEXT: lui a3, 349525 +; RV32M-NEXT: lui a4, 209715 +; RV32M-NEXT: lui a5, 61681 +; RV32M-NEXT: srli a6, a0, 1 +; RV32M-NEXT: addi a3, a3, 1365 +; RV32M-NEXT: and a2, a2, a3 +; RV32M-NEXT: and a3, a6, a3 +; RV32M-NEXT: lui a6, 4112 +; RV32M-NEXT: addi a4, a4, 819 +; RV32M-NEXT: addi a5, a5, -241 +; RV32M-NEXT: addi a6, a6, 257 +; RV32M-NEXT: sub a1, a1, a2 +; RV32M-NEXT: sub a0, a0, a3 +; RV32M-NEXT: and a2, a1, a4 +; RV32M-NEXT: srli a1, a1, 2 +; RV32M-NEXT: and a3, a0, a4 +; RV32M-NEXT: srli a0, a0, 2 +; RV32M-NEXT: and a1, a1, a4 +; RV32M-NEXT: and a0, a0, a4 +; RV32M-NEXT: add a1, a2, a1 +; RV32M-NEXT: add a0, a3, a0 +; RV32M-NEXT: srli a2, a1, 4 +; RV32M-NEXT: srli a3, a0, 4 +; RV32M-NEXT: add a1, a1, a2 +; RV32M-NEXT: add a0, a0, a3 +; RV32M-NEXT: and a1, a1, a5 +; RV32M-NEXT: and a0, a0, a5 +; RV32M-NEXT: mul a1, a1, a6 +; RV32M-NEXT: mul a0, a0, a6 +; RV32M-NEXT: srli a1, a1, 24 +; RV32M-NEXT: srli a0, a0, 24 +; RV32M-NEXT: add a0, a0, a1 +; RV32M-NEXT: li a1, 0 +; RV32M-NEXT: ret +; +; RV64M-LABEL: test_ctpop_i64: +; RV64M: # %bb.0: +; RV64M-NEXT: lui a1, 349525 +; RV64M-NEXT: lui a2, 209715 +; RV64M-NEXT: lui a3, 61681 +; RV64M-NEXT: addiw a1, a1, 1365 +; RV64M-NEXT: addiw a2, a2, 819 +; RV64M-NEXT: addiw a3, a3, -241 +; RV64M-NEXT: slli a4, a1, 32 +; RV64M-NEXT: add a1, a1, a4 +; RV64M-NEXT: slli a4, a2, 32 +; RV64M-NEXT: add a2, a2, a4 +; RV64M-NEXT: slli a4, a3, 32 +; RV64M-NEXT: add a3, a3, a4 +; RV64M-NEXT: srli a4, a0, 1 +; RV64M-NEXT: and a1, a4, a1 +; RV64M-NEXT: sub a0, a0, a1 +; RV64M-NEXT: and a1, a0, a2 +; RV64M-NEXT: srli a0, a0, 2 +; RV64M-NEXT: and a0, a0, a2 +; RV64M-NEXT: lui a2, 4112 +; RV64M-NEXT: addiw a2, a2, 257 +; RV64M-NEXT: add a0, a1, a0 +; RV64M-NEXT: srli a1, a0, 4 +; RV64M-NEXT: add a0, a0, a1 +; RV64M-NEXT: slli a1, a2, 32 +; RV64M-NEXT: and a0, a0, a3 +; RV64M-NEXT: add a1, a2, a1 +; RV64M-NEXT: mul a0, a0, a1 +; RV64M-NEXT: srli a0, a0, 56 +; RV64M-NEXT: ret ; ; RV32ZBB-LABEL: test_ctpop_i64: ; RV32ZBB: # %bb.0: @@ -2089,21 +2718,77 @@ define i64 @test_ctpop_i64(i64 %a) nounwind { ; ; RV32XTHEADBB-LABEL: test_ctpop_i64: ; RV32XTHEADBB: # %bb.0: -; RV32XTHEADBB-NEXT: addi sp, sp, -16 -; RV32XTHEADBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32XTHEADBB-NEXT: call __popcountdi2 -; RV32XTHEADBB-NEXT: srai a1, a0, 31 -; RV32XTHEADBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32XTHEADBB-NEXT: addi sp, sp, 16 +; RV32XTHEADBB-NEXT: srli a2, a1, 1 +; RV32XTHEADBB-NEXT: lui a3, 349525 +; RV32XTHEADBB-NEXT: lui a4, 209715 +; RV32XTHEADBB-NEXT: srli a5, a0, 1 +; RV32XTHEADBB-NEXT: addi a3, a3, 1365 +; RV32XTHEADBB-NEXT: and a2, a2, a3 +; RV32XTHEADBB-NEXT: and a3, a5, a3 +; RV32XTHEADBB-NEXT: lui a5, 61681 +; RV32XTHEADBB-NEXT: addi a4, a4, 819 +; RV32XTHEADBB-NEXT: addi a5, a5, -241 +; RV32XTHEADBB-NEXT: sub a1, a1, a2 +; RV32XTHEADBB-NEXT: sub a0, a0, a3 +; RV32XTHEADBB-NEXT: and a2, a1, a4 +; RV32XTHEADBB-NEXT: srli a1, a1, 2 +; RV32XTHEADBB-NEXT: and a3, a0, a4 +; RV32XTHEADBB-NEXT: srli a0, a0, 2 +; RV32XTHEADBB-NEXT: and a1, a1, a4 +; RV32XTHEADBB-NEXT: and a0, a0, a4 +; RV32XTHEADBB-NEXT: add a1, a2, a1 +; RV32XTHEADBB-NEXT: add a0, a3, a0 +; RV32XTHEADBB-NEXT: srli a2, a1, 4 +; RV32XTHEADBB-NEXT: srli a3, a0, 4 +; RV32XTHEADBB-NEXT: add a1, a1, a2 +; RV32XTHEADBB-NEXT: add a0, a0, a3 +; RV32XTHEADBB-NEXT: and a1, a1, a5 +; RV32XTHEADBB-NEXT: and a0, a0, a5 +; RV32XTHEADBB-NEXT: slli a2, a1, 8 +; RV32XTHEADBB-NEXT: slli a3, a0, 8 +; RV32XTHEADBB-NEXT: add a1, a1, a2 +; RV32XTHEADBB-NEXT: add a0, a0, a3 +; RV32XTHEADBB-NEXT: slli a2, a1, 16 +; RV32XTHEADBB-NEXT: slli a3, a0, 16 +; RV32XTHEADBB-NEXT: add a1, a1, a2 +; RV32XTHEADBB-NEXT: add a0, a0, a3 +; RV32XTHEADBB-NEXT: srli a1, a1, 24 +; RV32XTHEADBB-NEXT: srli a0, a0, 24 +; RV32XTHEADBB-NEXT: add a0, a0, a1 +; RV32XTHEADBB-NEXT: li a1, 0 ; RV32XTHEADBB-NEXT: ret ; ; RV64XTHEADBB-LABEL: test_ctpop_i64: ; RV64XTHEADBB: # %bb.0: -; RV64XTHEADBB-NEXT: addi sp, sp, -16 -; RV64XTHEADBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64XTHEADBB-NEXT: call __popcountdi2 -; RV64XTHEADBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64XTHEADBB-NEXT: addi sp, sp, 16 +; RV64XTHEADBB-NEXT: lui a1, 349525 +; RV64XTHEADBB-NEXT: lui a2, 209715 +; RV64XTHEADBB-NEXT: addiw a1, a1, 1365 +; RV64XTHEADBB-NEXT: addiw a2, a2, 819 +; RV64XTHEADBB-NEXT: slli a3, a1, 32 +; RV64XTHEADBB-NEXT: add a1, a1, a3 +; RV64XTHEADBB-NEXT: slli a3, a2, 32 +; RV64XTHEADBB-NEXT: add a2, a2, a3 +; RV64XTHEADBB-NEXT: srli a3, a0, 1 +; RV64XTHEADBB-NEXT: and a1, a3, a1 +; RV64XTHEADBB-NEXT: lui a3, 61681 +; RV64XTHEADBB-NEXT: addiw a3, a3, -241 +; RV64XTHEADBB-NEXT: sub a0, a0, a1 +; RV64XTHEADBB-NEXT: and a1, a0, a2 +; RV64XTHEADBB-NEXT: srli a0, a0, 2 +; RV64XTHEADBB-NEXT: and a0, a0, a2 +; RV64XTHEADBB-NEXT: slli a2, a3, 32 +; RV64XTHEADBB-NEXT: add a0, a1, a0 +; RV64XTHEADBB-NEXT: srli a1, a0, 4 +; RV64XTHEADBB-NEXT: add a0, a0, a1 +; RV64XTHEADBB-NEXT: add a2, a3, a2 +; RV64XTHEADBB-NEXT: and a0, a0, a2 +; RV64XTHEADBB-NEXT: slli a1, a0, 8 +; RV64XTHEADBB-NEXT: add a0, a0, a1 +; RV64XTHEADBB-NEXT: slli a1, a0, 16 +; RV64XTHEADBB-NEXT: add a0, a0, a1 +; RV64XTHEADBB-NEXT: slli a1, a0, 32 +; RV64XTHEADBB-NEXT: add a0, a0, a1 +; RV64XTHEADBB-NEXT: srli a0, a0, 56 ; RV64XTHEADBB-NEXT: ret %1 = call i64 @llvm.ctpop.i64(i64 %a) ret i64 %1 diff --git a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll index d57c4d653b2ae..03a6a6b1c4b7d 100644 --- a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll +++ b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll @@ -602,11 +602,14 @@ define signext i32 @ctlz(i64 %b) nounwind { ; ; RV32I-LABEL: ctlz: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: lui a3, 209715 +; RV32I-NEXT: lui a5, 61681 +; RV32I-NEXT: addi a4, a2, 1365 +; RV32I-NEXT: addi a3, a3, 819 +; RV32I-NEXT: addi a2, a5, -241 +; RV32I-NEXT: bnez a1, .LBB7_2 +; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 2 @@ -618,10 +621,27 @@ define signext i32 @ctlz(i64 %b) nounwind { ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: not a0, a0 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: srli a0, s1, 1 -; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: addi a0, a0, 32 +; RV32I-NEXT: andi a0, a0, 63 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB7_2: +; RV32I-NEXT: srli a0, a1, 1 +; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 4 @@ -631,39 +651,69 @@ define signext i32 @ctlz(i64 %b) nounwind { ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: not a0, a0 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: bnez s1, .LBB7_2 -; RV32I-NEXT: # %bb.1: # %entry -; RV32I-NEXT: addi a0, s0, 32 -; RV32I-NEXT: .LBB7_2: # %entry +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: andi a0, a0, 63 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; ; RV64I-LABEL: ctlz: ; RV64I: # %bb.0: # %entry -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: srli a1, a0, 1 +; RV64I-NEXT: lui a2, 349525 +; RV64I-NEXT: lui a3, 209715 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 2 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 8 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 16 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 32 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addiw a2, a3, 819 +; RV64I-NEXT: srli a3, a0, 2 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: slli a3, a1, 32 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: slli a3, a2, 32 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: srli a3, a0, 4 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 8 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 16 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 32 +; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: not a0, a0 -; RV64I-NEXT: call __popcountdi2 -; RV64I-NEXT: andi a0, a0, 63 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: srli a3, a0, 1 +; RV64I-NEXT: and a1, a3, a1 +; RV64I-NEXT: lui a3, 61681 +; RV64I-NEXT: addiw a3, a3, -241 +; RV64I-NEXT: sub a0, a0, a1 +; RV64I-NEXT: and a1, a0, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a2, a3, 32 +; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: srli a1, a0, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a3, a2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a1, a0, 8 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 16 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 32 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a0, a0, 2 +; RV64I-NEXT: srli a0, a0, 58 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/pr56457.ll b/llvm/test/CodeGen/RISCV/pr56457.ll index 19cc8b3af208f..cf518b31a190b 100644 --- a/llvm/test/CodeGen/RISCV/pr56457.ll +++ b/llvm/test/CodeGen/RISCV/pr56457.ll @@ -9,25 +9,46 @@ define i15 @foo(i15 %x) nounwind { ; CHECK-NEXT: slli a1, a0, 49 ; CHECK-NEXT: beqz a1, .LBB0_2 ; CHECK-NEXT: # %bb.1: # %cond.false -; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: srli a1, a1, 50 +; CHECK-NEXT: lui a2, 1 +; CHECK-NEXT: lui a3, 209715 +; CHECK-NEXT: lui a4, 61681 ; CHECK-NEXT: or a0, a0, a1 -; CHECK-NEXT: slli a1, a0, 49 -; CHECK-NEXT: srli a1, a1, 51 -; CHECK-NEXT: or a0, a0, a1 -; CHECK-NEXT: slli a1, a0, 49 -; CHECK-NEXT: srli a1, a1, 53 -; CHECK-NEXT: or a0, a0, a1 -; CHECK-NEXT: slli a1, a0, 49 -; CHECK-NEXT: srli a1, a1, 57 -; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: addiw a1, a2, 1365 +; CHECK-NEXT: addiw a2, a3, 819 +; CHECK-NEXT: addiw a3, a4, -241 +; CHECK-NEXT: slli a4, a2, 32 +; CHECK-NEXT: add a2, a2, a4 +; CHECK-NEXT: slli a4, a3, 32 +; CHECK-NEXT: add a3, a3, a4 +; CHECK-NEXT: slli a4, a0, 49 +; CHECK-NEXT: srli a4, a4, 51 +; CHECK-NEXT: or a0, a0, a4 +; CHECK-NEXT: slli a4, a0, 49 +; CHECK-NEXT: srli a4, a4, 53 +; CHECK-NEXT: or a0, a0, a4 +; CHECK-NEXT: slli a4, a0, 49 +; CHECK-NEXT: srli a4, a4, 57 +; CHECK-NEXT: or a0, a0, a4 ; CHECK-NEXT: not a0, a0 +; CHECK-NEXT: srli a4, a0, 1 +; CHECK-NEXT: and a1, a4, a1 ; CHECK-NEXT: slli a0, a0, 49 ; CHECK-NEXT: srli a0, a0, 49 -; CHECK-NEXT: call __popcountdi2 -; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: sub a0, a0, a1 +; CHECK-NEXT: and a1, a0, a2 +; CHECK-NEXT: srli a0, a0, 2 +; CHECK-NEXT: and a0, a0, a2 +; CHECK-NEXT: add a0, a1, a0 +; CHECK-NEXT: srli a1, a0, 4 +; CHECK-NEXT: add a0, a0, a1 +; CHECK-NEXT: lui a1, 4112 +; CHECK-NEXT: addiw a1, a1, 257 +; CHECK-NEXT: and a0, a0, a3 +; CHECK-NEXT: slli a2, a1, 32 +; CHECK-NEXT: add a1, a1, a2 +; CHECK-NEXT: mul a0, a0, a1 +; CHECK-NEXT: srli a0, a0, 56 ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: li a0, 15 diff --git a/llvm/test/CodeGen/RISCV/pr95271.ll b/llvm/test/CodeGen/RISCV/pr95271.ll index 46e9a196d6c59..aa941cb803627 100644 --- a/llvm/test/CodeGen/RISCV/pr95271.ll +++ b/llvm/test/CodeGen/RISCV/pr95271.ll @@ -6,8 +6,29 @@ define i32 @PR95271(ptr %p) { ; RV32I-LABEL: PR95271: ; RV32I: # %bb.0: ; RV32I-NEXT: lw a0, 0(a0) +; RV32I-NEXT: lui a1, 349525 +; RV32I-NEXT: addi a1, a1, 1365 ; RV32I-NEXT: addi a0, a0, 1 -; RV32I-NEXT: tail __popcountsi2 +; RV32I-NEXT: srli a2, a0, 1 +; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: lui a2, 209715 +; RV32I-NEXT: addi a2, a2, 819 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: lui a2, 61681 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: addi a1, a2, -241 +; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: ret ; ; RV64I-LABEL: PR95271: ; RV64I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll index e783421e18769..04a2f67c4942b 100644 --- a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll @@ -11,22 +11,38 @@ define i32 @ctlz_i32(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: beqz a0, .LBB0_2 ; RV32I-NEXT: # %bb.1: # %cond.false -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: srli a1, a0, 2 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: srli a1, a0, 4 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: srli a1, a0, 8 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: srli a1, a0, 16 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: addi a1, a2, 1365 +; RV32I-NEXT: srli a2, a0, 2 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 4 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 8 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 16 +; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: not a0, a0 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: srli a2, a0, 1 +; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: lui a2, 209715 +; RV32I-NEXT: addi a2, a2, 819 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: lui a2, 61681 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: addi a1, a2, -241 +; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: li a0, 32 @@ -45,11 +61,14 @@ declare i64 @llvm.ctlz.i64(i64, i1) define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-LABEL: ctlz_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: lui a3, 209715 +; RV32I-NEXT: lui a5, 61681 +; RV32I-NEXT: addi a4, a2, 1365 +; RV32I-NEXT: addi a3, a3, 819 +; RV32I-NEXT: addi a2, a5, -241 +; RV32I-NEXT: bnez a1, .LBB1_2 +; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 2 @@ -61,10 +80,27 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: not a0, a0 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: srli a0, s1, 1 -; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: addi a0, a0, 32 +; RV32I-NEXT: li a1, 0 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB1_2: +; RV32I-NEXT: srli a0, a1, 1 +; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 4 @@ -74,16 +110,22 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: not a0, a0 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: bnez s1, .LBB1_2 -; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: addi a0, s0, 32 -; RV32I-NEXT: .LBB1_2: +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; ; RV32XTHEADBB-LABEL: ctlz_i64: diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll index acfdff82d5a52..98c86da41afa1 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll @@ -11,22 +11,38 @@ define i32 @ctlz_i32(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: beqz a0, .LBB0_2 ; RV32I-NEXT: # %bb.1: # %cond.false -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: srli a1, a0, 2 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: srli a1, a0, 4 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: srli a1, a0, 8 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: srli a1, a0, 16 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: addi a1, a2, 1365 +; RV32I-NEXT: srli a2, a0, 2 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 4 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 8 +; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: srli a2, a0, 16 +; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: not a0, a0 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: srli a2, a0, 1 +; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: lui a2, 209715 +; RV32I-NEXT: addi a2, a2, 819 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: lui a2, 61681 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: addi a1, a2, -241 +; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: li a0, 32 @@ -45,11 +61,14 @@ declare i64 @llvm.ctlz.i64(i64, i1) define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-LABEL: ctlz_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: lui a3, 209715 +; RV32I-NEXT: lui a5, 61681 +; RV32I-NEXT: addi a4, a2, 1365 +; RV32I-NEXT: addi a3, a3, 819 +; RV32I-NEXT: addi a2, a5, -241 +; RV32I-NEXT: bnez a1, .LBB1_2 +; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 2 @@ -61,10 +80,27 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: not a0, a0 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: srli a0, s1, 1 -; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: addi a0, a0, 32 +; RV32I-NEXT: li a1, 0 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB1_2: +; RV32I-NEXT: srli a0, a1, 1 +; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 4 @@ -74,16 +110,22 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: not a0, a0 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: bnez s1, .LBB1_2 -; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: addi a0, s0, 32 -; RV32I-NEXT: .LBB1_2: +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a3 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: li a1, 0 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: ctlz_i64: @@ -211,7 +253,28 @@ declare i32 @llvm.ctpop.i32(i32) define i32 @ctpop_i32(i32 %a) nounwind { ; RV32I-LABEL: ctpop_i32: ; RV32I: # %bb.0: -; RV32I-NEXT: tail __popcountsi2 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: lui a2, 209715 +; RV32I-NEXT: addi a2, a2, 819 +; RV32I-NEXT: sub a0, a0, a1 +; RV32I-NEXT: and a1, a0, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: lui a2, 61681 +; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: srli a1, a0, 4 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: addi a1, a2, -241 +; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: slli a1, a0, 16 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: ctpop_i32: ; RV32ZBB: # %bb.0: @@ -302,21 +365,42 @@ declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) define <2 x i32> @ctpop_v2i32(<2 x i32> %a) nounwind { ; RV32I-LABEL: ctpop_v2i32: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: mv s0, a1 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __popcountsi2 -; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: srli a2, a0, 1 +; RV32I-NEXT: lui a3, 349525 +; RV32I-NEXT: lui a4, 209715 +; RV32I-NEXT: srli a5, a1, 1 +; RV32I-NEXT: addi a3, a3, 1365 +; RV32I-NEXT: and a2, a2, a3 +; RV32I-NEXT: and a3, a5, a3 +; RV32I-NEXT: lui a5, 61681 +; RV32I-NEXT: addi a4, a4, 819 +; RV32I-NEXT: addi a5, a5, -241 +; RV32I-NEXT: sub a0, a0, a2 +; RV32I-NEXT: sub a1, a1, a3 +; RV32I-NEXT: and a2, a0, a4 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a3, a1, a4 +; RV32I-NEXT: srli a1, a1, 2 +; RV32I-NEXT: and a0, a0, a4 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: add a1, a3, a1 +; RV32I-NEXT: srli a2, a0, 4 +; RV32I-NEXT: srli a3, a1, 4 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: add a1, a1, a3 +; RV32I-NEXT: and a0, a0, a5 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: slli a2, a0, 8 +; RV32I-NEXT: slli a3, a1, 8 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: add a1, a1, a3 +; RV32I-NEXT: slli a2, a0, 16 +; RV32I-NEXT: slli a3, a1, 16 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: add a1, a1, a3 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: srli a1, a1, 24 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: ctpop_v2i32: @@ -433,12 +517,44 @@ declare i64 @llvm.ctpop.i64(i64) define i64 @ctpop_i64(i64 %a) nounwind { ; RV32I-LABEL: ctpop_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: call __popcountdi2 -; RV32I-NEXT: srai a1, a0, 31 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: srli a2, a1, 1 +; RV32I-NEXT: lui a3, 349525 +; RV32I-NEXT: lui a4, 209715 +; RV32I-NEXT: srli a5, a0, 1 +; RV32I-NEXT: addi a3, a3, 1365 +; RV32I-NEXT: and a2, a2, a3 +; RV32I-NEXT: and a3, a5, a3 +; RV32I-NEXT: lui a5, 61681 +; RV32I-NEXT: addi a4, a4, 819 +; RV32I-NEXT: addi a5, a5, -241 +; RV32I-NEXT: sub a1, a1, a2 +; RV32I-NEXT: sub a0, a0, a3 +; RV32I-NEXT: and a2, a1, a4 +; RV32I-NEXT: srli a1, a1, 2 +; RV32I-NEXT: and a3, a0, a4 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: and a0, a0, a4 +; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: add a0, a3, a0 +; RV32I-NEXT: srli a2, a1, 4 +; RV32I-NEXT: srli a3, a0, 4 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: add a0, a0, a3 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: and a0, a0, a5 +; RV32I-NEXT: slli a2, a1, 8 +; RV32I-NEXT: slli a3, a0, 8 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: add a0, a0, a3 +; RV32I-NEXT: slli a2, a1, 16 +; RV32I-NEXT: slli a3, a0, 16 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: add a0, a0, a3 +; RV32I-NEXT: srli a1, a1, 24 +; RV32I-NEXT: srli a0, a0, 24 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: ctpop_i64: @@ -566,38 +682,82 @@ declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind { ; RV32I-LABEL: ctpop_v2i64: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -32 -; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a2, 0(a1) -; RV32I-NEXT: lw a3, 4(a1) -; RV32I-NEXT: lw s0, 8(a1) -; RV32I-NEXT: lw s1, 12(a1) -; RV32I-NEXT: mv s2, a0 -; RV32I-NEXT: mv a0, a2 -; RV32I-NEXT: mv a1, a3 -; RV32I-NEXT: call __popcountdi2 -; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: srai s4, a0, 31 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: call __popcountdi2 -; RV32I-NEXT: srai a1, a0, 31 -; RV32I-NEXT: sw s3, 0(s2) -; RV32I-NEXT: sw s4, 4(s2) -; RV32I-NEXT: sw a0, 8(s2) -; RV32I-NEXT: sw a1, 12(s2) -; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 32 +; RV32I-NEXT: lw a3, 0(a1) +; RV32I-NEXT: lw a4, 4(a1) +; RV32I-NEXT: lw a2, 8(a1) +; RV32I-NEXT: lw a1, 12(a1) +; RV32I-NEXT: lui a5, 349525 +; RV32I-NEXT: addi a5, a5, 1365 +; RV32I-NEXT: srli a6, a4, 1 +; RV32I-NEXT: srli a7, a3, 1 +; RV32I-NEXT: srli t0, a1, 1 +; RV32I-NEXT: srli t1, a2, 1 +; RV32I-NEXT: and a6, a6, a5 +; RV32I-NEXT: and a7, a7, a5 +; RV32I-NEXT: and t0, t0, a5 +; RV32I-NEXT: and a5, t1, a5 +; RV32I-NEXT: lui t1, 209715 +; RV32I-NEXT: addi t1, t1, 819 +; RV32I-NEXT: sub a4, a4, a6 +; RV32I-NEXT: sub a3, a3, a7 +; RV32I-NEXT: sub a1, a1, t0 +; RV32I-NEXT: sub a2, a2, a5 +; RV32I-NEXT: and a5, a4, t1 +; RV32I-NEXT: srli a4, a4, 2 +; RV32I-NEXT: and a6, a3, t1 +; RV32I-NEXT: srli a3, a3, 2 +; RV32I-NEXT: and a7, a1, t1 +; RV32I-NEXT: srli a1, a1, 2 +; RV32I-NEXT: and t0, a2, t1 +; RV32I-NEXT: srli a2, a2, 2 +; RV32I-NEXT: and a4, a4, t1 +; RV32I-NEXT: and a3, a3, t1 +; RV32I-NEXT: and a1, a1, t1 +; RV32I-NEXT: and a2, a2, t1 +; RV32I-NEXT: add a4, a5, a4 +; RV32I-NEXT: lui a5, 61681 +; RV32I-NEXT: addi a5, a5, -241 +; RV32I-NEXT: add a3, a6, a3 +; RV32I-NEXT: add a1, a7, a1 +; RV32I-NEXT: add a2, t0, a2 +; RV32I-NEXT: srli a6, a4, 4 +; RV32I-NEXT: srli a7, a3, 4 +; RV32I-NEXT: srli t0, a1, 4 +; RV32I-NEXT: add a4, a4, a6 +; RV32I-NEXT: srli a6, a2, 4 +; RV32I-NEXT: add a3, a3, a7 +; RV32I-NEXT: add a1, a1, t0 +; RV32I-NEXT: add a2, a2, a6 +; RV32I-NEXT: and a4, a4, a5 +; RV32I-NEXT: and a3, a3, a5 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: and a2, a2, a5 +; RV32I-NEXT: slli a5, a4, 8 +; RV32I-NEXT: slli a6, a3, 8 +; RV32I-NEXT: slli a7, a1, 8 +; RV32I-NEXT: slli t0, a2, 8 +; RV32I-NEXT: add a4, a4, a5 +; RV32I-NEXT: add a3, a3, a6 +; RV32I-NEXT: add a1, a1, a7 +; RV32I-NEXT: add a2, a2, t0 +; RV32I-NEXT: slli a5, a4, 16 +; RV32I-NEXT: slli a6, a3, 16 +; RV32I-NEXT: slli a7, a1, 16 +; RV32I-NEXT: slli t0, a2, 16 +; RV32I-NEXT: add a4, a4, a5 +; RV32I-NEXT: add a3, a3, a6 +; RV32I-NEXT: add a1, a1, a7 +; RV32I-NEXT: add a2, a2, t0 +; RV32I-NEXT: srli a4, a4, 24 +; RV32I-NEXT: srli a3, a3, 24 +; RV32I-NEXT: srli a1, a1, 24 +; RV32I-NEXT: srli a2, a2, 24 +; RV32I-NEXT: add a3, a3, a4 +; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: sw a3, 0(a0) +; RV32I-NEXT: sw zero, 4(a0) +; RV32I-NEXT: sw a1, 8(a0) +; RV32I-NEXT: sw zero, 12(a0) ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: ctpop_v2i64: diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll index a11bc09954062..d9f7d36127293 100644 --- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll @@ -295,24 +295,48 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: beqz a0, .LBB5_2 ; RV64I-NEXT: # %bb.1: # %cond.false -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: srli a1, a0, 1 +; RV64I-NEXT: lui a2, 349525 +; RV64I-NEXT: lui a3, 209715 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 2 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 8 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 16 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 32 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addiw a2, a3, 819 +; RV64I-NEXT: srli a3, a0, 2 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: slli a3, a1, 32 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: slli a3, a2, 32 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: srli a3, a0, 4 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 8 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 16 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 32 +; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: not a0, a0 -; RV64I-NEXT: call __popcountdi2 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: srli a3, a0, 1 +; RV64I-NEXT: and a1, a3, a1 +; RV64I-NEXT: lui a3, 61681 +; RV64I-NEXT: addiw a3, a3, -241 +; RV64I-NEXT: sub a0, a0, a1 +; RV64I-NEXT: and a1, a0, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a2, a3, 32 +; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: srli a1, a0, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a3, a2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a1, a0, 8 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 16 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 32 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB5_2: ; RV64I-NEXT: li a0, 64 diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll index bb7078461c244..17eb0817d548a 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll @@ -285,24 +285,48 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: beqz a0, .LBB5_2 ; RV64I-NEXT: # %bb.1: # %cond.false -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: srli a1, a0, 1 +; RV64I-NEXT: lui a2, 349525 +; RV64I-NEXT: lui a3, 209715 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 2 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 8 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 16 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srli a1, a0, 32 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addiw a2, a3, 819 +; RV64I-NEXT: srli a3, a0, 2 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: slli a3, a1, 32 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: slli a3, a2, 32 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: srli a3, a0, 4 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 8 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 16 +; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: srli a3, a0, 32 +; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: not a0, a0 -; RV64I-NEXT: call __popcountdi2 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: srli a3, a0, 1 +; RV64I-NEXT: and a1, a3, a1 +; RV64I-NEXT: lui a3, 61681 +; RV64I-NEXT: addiw a3, a3, -241 +; RV64I-NEXT: sub a0, a0, a1 +; RV64I-NEXT: and a1, a0, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a2, a3, 32 +; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: srli a1, a0, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a3, a2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a1, a0, 8 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 16 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 32 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB5_2: ; RV64I-NEXT: li a0, 64 @@ -804,11 +828,35 @@ declare i64 @llvm.ctpop.i64(i64) define i64 @ctpop_i64(i64 %a) nounwind { ; RV64I-LABEL: ctpop_i64: ; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: call __popcountdi2 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: lui a1, 349525 +; RV64I-NEXT: lui a2, 209715 +; RV64I-NEXT: addiw a1, a1, 1365 +; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: slli a3, a1, 32 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: slli a3, a2, 32 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: srli a3, a0, 1 +; RV64I-NEXT: and a1, a3, a1 +; RV64I-NEXT: lui a3, 61681 +; RV64I-NEXT: addiw a3, a3, -241 +; RV64I-NEXT: sub a0, a0, a1 +; RV64I-NEXT: and a1, a0, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a2, a3, 32 +; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: srli a1, a0, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a3, a2 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: slli a1, a0, 8 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 16 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a1, a0, 32 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: ctpop_i64: @@ -900,21 +948,52 @@ declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind { ; RV64I-LABEL: ctpop_v2i64: ; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -32 -; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: mv s0, a1 -; RV64I-NEXT: call __popcountdi2 -; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: mv a0, s0 -; RV64I-NEXT: call __popcountdi2 -; RV64I-NEXT: mv a1, a0 -; RV64I-NEXT: mv a0, s1 -; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 32 +; RV64I-NEXT: srli a2, a0, 1 +; RV64I-NEXT: lui a3, 349525 +; RV64I-NEXT: lui a4, 209715 +; RV64I-NEXT: lui a5, 61681 +; RV64I-NEXT: addiw a3, a3, 1365 +; RV64I-NEXT: addiw a4, a4, 819 +; RV64I-NEXT: addiw a5, a5, -241 +; RV64I-NEXT: slli a6, a3, 32 +; RV64I-NEXT: add a3, a3, a6 +; RV64I-NEXT: slli a6, a4, 32 +; RV64I-NEXT: add a4, a4, a6 +; RV64I-NEXT: slli a6, a5, 32 +; RV64I-NEXT: add a5, a5, a6 +; RV64I-NEXT: srli a6, a1, 1 +; RV64I-NEXT: and a2, a2, a3 +; RV64I-NEXT: and a3, a6, a3 +; RV64I-NEXT: sub a0, a0, a2 +; RV64I-NEXT: sub a1, a1, a3 +; RV64I-NEXT: and a2, a0, a4 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a3, a1, a4 +; RV64I-NEXT: srli a1, a1, 2 +; RV64I-NEXT: and a0, a0, a4 +; RV64I-NEXT: and a1, a1, a4 +; RV64I-NEXT: add a0, a2, a0 +; RV64I-NEXT: add a1, a3, a1 +; RV64I-NEXT: srli a2, a0, 4 +; RV64I-NEXT: srli a3, a1, 4 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: and a0, a0, a5 +; RV64I-NEXT: and a1, a1, a5 +; RV64I-NEXT: slli a2, a0, 8 +; RV64I-NEXT: slli a3, a1, 8 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: slli a2, a0, 16 +; RV64I-NEXT: slli a3, a1, 16 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: slli a2, a0, 32 +; RV64I-NEXT: slli a3, a1, 32 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a1, a1, a3 +; RV64I-NEXT: srli a0, a0, 56 +; RV64I-NEXT: srli a1, a1, 56 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: ctpop_v2i64: diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll index 4494d9b8b5691..49494608eee4d 100644 --- a/llvm/test/CodeGen/RISCV/sextw-removal.ll +++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll @@ -316,18 +316,52 @@ declare float @baz(i32 signext %i3) define void @test7(i32 signext %arg, i32 signext %arg1) nounwind { ; RV64I-LABEL: test7: ; RV64I: # %bb.0: # %bb -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: addi sp, sp, -48 +; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sraw a0, a0, a1 +; RV64I-NEXT: lui a1, 349525 +; RV64I-NEXT: lui a2, 209715 +; RV64I-NEXT: lui a3, 61681 +; RV64I-NEXT: lui a4, 4112 +; RV64I-NEXT: addiw s0, a1, 1365 +; RV64I-NEXT: addiw s1, a2, 819 +; RV64I-NEXT: addiw s2, a3, -241 +; RV64I-NEXT: addiw s3, a4, 257 +; RV64I-NEXT: slli a1, s0, 32 +; RV64I-NEXT: add s0, s0, a1 +; RV64I-NEXT: slli a1, s1, 32 +; RV64I-NEXT: add s1, s1, a1 +; RV64I-NEXT: slli a1, s2, 32 +; RV64I-NEXT: add s2, s2, a1 +; RV64I-NEXT: slli a1, s3, 32 +; RV64I-NEXT: add s3, s3, a1 ; RV64I-NEXT: .LBB6_1: # %bb2 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 -; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: call foo -; RV64I-NEXT: call __popcountdi2 +; RV64I-NEXT: srli a1, a0, 1 +; RV64I-NEXT: and a1, a1, s0 +; RV64I-NEXT: sub a0, a0, a1 +; RV64I-NEXT: and a1, a0, s1 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, s1 +; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: srli a1, a0, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: and a0, a0, s2 +; RV64I-NEXT: mul a0, a0, s3 +; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: bnez a0, .LBB6_1 ; RV64I-NEXT: # %bb.2: # %bb7 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: test7: diff --git a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll index 9f89b2c495659..341163c6f9bd0 100644 --- a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll @@ -6,20 +6,56 @@ define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){ ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr} -; CHECK-NEXT: .vsave {d8, d9} -; CHECK-NEXT: vpush {d8, d9} -; CHECK-NEXT: vmov q4, q0 -; CHECK-NEXT: vmov r0, r1, d9 -; CHECK-NEXT: bl __popcountdi2 -; CHECK-NEXT: mov r4, r0 -; CHECK-NEXT: vmov r0, r1, d8 -; CHECK-NEXT: asrs r5, r4, #31 -; CHECK-NEXT: bl __popcountdi2 -; CHECK-NEXT: asrs r1, r0, #31 -; CHECK-NEXT: vmov q0[2], q0[0], r0, r4 -; CHECK-NEXT: vmov q0[3], q0[1], r1, r5 -; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: vmov r1, r2, d1 +; CHECK-NEXT: mov.w lr, #1431655765 +; CHECK-NEXT: vmov r3, r4, d0 +; CHECK-NEXT: mov.w r12, #858993459 +; CHECK-NEXT: vldr s1, .LCPI0_0 +; CHECK-NEXT: vmov.f32 s3, s1 +; CHECK-NEXT: and.w r0, lr, r2, lsr #1 +; CHECK-NEXT: subs r0, r2, r0 +; CHECK-NEXT: and.w r2, r12, r0, lsr #2 +; CHECK-NEXT: bic r0, r0, #-858993460 +; CHECK-NEXT: add r0, r2 +; CHECK-NEXT: and.w r2, lr, r1, lsr #1 +; CHECK-NEXT: subs r1, r1, r2 +; CHECK-NEXT: add.w r0, r0, r0, lsr #4 +; CHECK-NEXT: and.w r2, r12, r1, lsr #2 +; CHECK-NEXT: bic r1, r1, #-858993460 +; CHECK-NEXT: add r1, r2 +; CHECK-NEXT: and.w r2, lr, r3, lsr #1 +; CHECK-NEXT: subs r2, r3, r2 +; CHECK-NEXT: bic r5, r0, #-252645136 +; CHECK-NEXT: add.w r1, r1, r1, lsr #4 +; CHECK-NEXT: mov.w r0, #16843009 +; CHECK-NEXT: and.w r3, r12, r2, lsr #2 +; CHECK-NEXT: bic r2, r2, #-858993460 +; CHECK-NEXT: add r2, r3 +; CHECK-NEXT: and.w r3, lr, r4, lsr #1 +; CHECK-NEXT: subs r3, r4, r3 +; CHECK-NEXT: bic r1, r1, #-252645136 +; CHECK-NEXT: add.w r2, r2, r2, lsr #4 +; CHECK-NEXT: muls r5, r0, r5 +; CHECK-NEXT: and.w r4, r12, r3, lsr #2 +; CHECK-NEXT: bic r3, r3, #-858993460 +; CHECK-NEXT: bic r2, r2, #-252645136 +; CHECK-NEXT: add r3, r4 +; CHECK-NEXT: muls r1, r0, r1 +; CHECK-NEXT: add.w r3, r3, r3, lsr #4 +; CHECK-NEXT: muls r2, r0, r2 +; CHECK-NEXT: bic r3, r3, #-252645136 +; CHECK-NEXT: muls r0, r3, r0 +; CHECK-NEXT: lsrs r1, r1, #24 +; CHECK-NEXT: add.w r1, r1, r5, lsr #24 +; CHECK-NEXT: lsrs r2, r2, #24 +; CHECK-NEXT: vmov s2, r1 +; CHECK-NEXT: add.w r0, r2, r0, lsr #24 +; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: pop {r4, r5, r7, pc} +; CHECK-NEXT: .p2align 2 +; CHECK-NEXT: @ %bb.1: +; CHECK-NEXT: .LCPI0_0: +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src) ret <2 x i64> %0