Skip to content

[AutoUpgrade][AMDGPU] Adjust AS7 and AS9 address width to 48 bits #137418

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 2 commits into from
Closed

[AutoUpgrade][AMDGPU] Adjust AS7 and AS9 address width to 48 bits #137418

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
bafdd8b
[𝘀𝗽𝗿] initial version
arichardson Apr 25, 2025
dbb3295
add other address spaces as well
arichardson May 1, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 3 additions & 4 deletions clang/lib/Basic/Targets/AMDGPU.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -33,10 +33,9 @@ static const char *const DataLayoutStringR600 =

static const char *const DataLayoutStringAMDGCN =
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
"-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:"
"32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
"-ni:7:8:9";
"-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16"
"-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
"-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9";

const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
llvm::AMDGPUAS::FLAT_ADDRESS, // Default
Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGen/target-data.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -176,12 +176,12 @@

// RUN: %clang_cc1 -triple amdgcn-unknown -target-cpu hawaii -o - -emit-llvm %s \
// RUN: | FileCheck %s -check-prefix=R600SI
// R600SI: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
// R600SI: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"

// Test default -target-cpu
// RUN: %clang_cc1 -triple amdgcn-unknown -o - -emit-llvm %s \
// RUN: | FileCheck %s -check-prefix=R600SIDefault
// R600SIDefault: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
// R600SIDefault: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"

// RUN: %clang_cc1 -triple arm64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=AARCH64
Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 %s -O0 -triple amdgcn -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 %s -O0 -triple amdgcn---opencl -emit-llvm -o - | FileCheck %s

// CHECK: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
// CHECK: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
void foo(void) {}
6 changes: 3 additions & 3 deletions lld/test/ELF/lto/amdgcn-oses.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@

;--- amdhsa.ll
target triple = "amdgcn-amd-amdhsa"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"

!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
Expand All @@ -36,15 +36,15 @@ define void @_start() {

;--- amdpal.ll
target triple = "amdgcn-amd-amdpal"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"

define amdgpu_cs void @_start() {
ret void
}

;--- mesa3d.ll
target triple = "amdgcn-amd-mesa3d"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"

define void @_start() {
ret void
Expand Down
2 changes: 1 addition & 1 deletion lld/test/ELF/lto/amdgcn.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
; Make sure the amdgcn triple is handled

target triple = "amdgcn-amd-amdhsa"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"

define void @_start() {
ret void
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/IR/AutoUpgrade.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5768,11 +5768,11 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
// Add sizing for address spaces 7 and 8 (fat raw buffers and buffer
// resources) An empty data layout has already been upgraded to G1 by now.
if (!DL.contains("-p7") && !DL.starts_with("p7"))
Res.append("-p7:160:256:256:32");
Res.append("-p7:160:256:256:32:48");
if (!DL.contains("-p8") && !DL.starts_with("p8"))
Res.append("-p8:128:128");
Res.append("-p8:128:128:128:32:48");
if (!DL.contains("-p9") && !DL.starts_with("p9"))
Res.append("-p9:192:256:256:32");
Res.append("-p9:192:256:256:32:48");

return Res;
}
Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -686,7 +686,9 @@ static StringRef computeDataLayout(const Triple &TT) {
// space 8) which cannot be non-trivilally accessed by LLVM memory operations
// like getelementptr.
return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
"-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-"
"-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16-"
"v24:"
"32-"
"v32:32-v48:64-v96:"
"128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-"
"G1-ni:7:8:9";
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Analysis/StackSafetyAnalysis/extend-ptr.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
; CHECK-NEXT: x[]: full-set
; CHECK-NEXT: allocas uses:

target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"

define void @a(ptr addrspace(5) %x) {
entry:
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,14 +1,13 @@
; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - < %s 2>&1 | FileCheck -check-prefix=GISEL-ERR %s

; GISEL-ERR: LLVM ERROR: unable to legalize instruction: %{{[0-9]+}}:_(p8) = G_PTR_ADD %{{[0-9]+}}:_, %{{[0-9]+}}:_(s128)
; GISEL-ERR: LLVM ERROR: unable to legalize instruction: %{{[0-9]+}}:_(p8) = G_PTR_ADD %{{[0-9]+}}:_, %{{[0-9]+}}:_(s8)


define float @gep_on_rsrc(ptr addrspace(8) %rsrc) {
body:
%next = getelementptr float, ptr addrspace(8) %rsrc, i128 1
%next = getelementptr float, ptr addrspace(8) %rsrc, i8 1
%res = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %next, i32 0, i32 0, i32 0)
ret float %res
}

declare float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8), i32, i32, i32 immarg)

32 changes: 16 additions & 16 deletions llvm/test/CodeGen/AMDGPU/ptrmask.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -145,8 +145,8 @@ define amdgpu_ps ptr addrspace(7) @s_ptrmask_buffer_fat_ptr_i32_neg8(ptr addrspa
ret ptr addrspace(7) %masked
}

define ptr addrspace(8) @v_ptrmask_buffer_resource_variable_i128(ptr addrspace(8) %ptr, i128 %mask) {
; GCN-LABEL: v_ptrmask_buffer_resource_variable_i128:
define ptr addrspace(8) @v_ptrmask_buffer_resource_variable_i8(ptr addrspace(8) %ptr, i8 %mask) {
; GCN-LABEL: v_ptrmask_buffer_resource_variable_i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_and_b32_e32 v1, v1, v5
Expand All @@ -155,69 +155,69 @@ define ptr addrspace(8) @v_ptrmask_buffer_resource_variable_i128(ptr addrspace(8
; GCN-NEXT: v_and_b32_e32 v2, v2, v6
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10PLUS-LABEL: v_ptrmask_buffer_resource_variable_i128:
; GFX10PLUS-LABEL: v_ptrmask_buffer_resource_variable_i8:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_and_b32_e32 v0, v0, v4
; GFX10PLUS-NEXT: v_and_b32_e32 v1, v1, v5
; GFX10PLUS-NEXT: v_and_b32_e32 v2, v2, v6
; GFX10PLUS-NEXT: v_and_b32_e32 v3, v3, v7
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%masked = call ptr addrspace(8) @llvm.ptrmask.p8.i128(ptr addrspace(8) %ptr, i128 %mask)
%masked = call ptr addrspace(8) @llvm.ptrmask.p8.i8(ptr addrspace(8) %ptr, i8 %mask)
ret ptr addrspace(8) %masked
}

define ptr addrspace(8) @v_ptrmask_buffer_resource_variable_i128_neg8(ptr addrspace(8) %ptr) {
; GCN-LABEL: v_ptrmask_buffer_resource_variable_i128_neg8:
define ptr addrspace(8) @v_ptrmask_buffer_resource_variable_i8_neg8(ptr addrspace(8) %ptr) {
; GCN-LABEL: v_ptrmask_buffer_resource_variable_i8_neg8:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_and_b32_e32 v0, -8, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10PLUS-LABEL: v_ptrmask_buffer_resource_variable_i128_neg8:
; GFX10PLUS-LABEL: v_ptrmask_buffer_resource_variable_i8_neg8:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_and_b32_e32 v0, -8, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%masked = call ptr addrspace(8) @llvm.ptrmask.p8.i128(ptr addrspace(8) %ptr, i128 -8)
%masked = call ptr addrspace(8) @llvm.ptrmask.p8.i8(ptr addrspace(8) %ptr, i8 -8)
ret ptr addrspace(8) %masked
}

define amdgpu_ps ptr addrspace(8) @s_ptrmask_buffer_resource_variable_i128(ptr addrspace(8) inreg %ptr, i128 inreg %mask) {
; GCN-LABEL: s_ptrmask_buffer_resource_variable_i128:
define amdgpu_ps ptr addrspace(8) @s_ptrmask_buffer_resource_variable_i8(ptr addrspace(8) inreg %ptr, i8 inreg %mask) {
; GCN-LABEL: s_ptrmask_buffer_resource_variable_i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9]
; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[6:7]
; GCN-NEXT: s_mov_b32 s2, s4
; GCN-NEXT: s_mov_b32 s3, s5
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_ptrmask_buffer_resource_variable_i128:
; GFX10PLUS-LABEL: s_ptrmask_buffer_resource_variable_i8:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[6:7]
; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[4:5], s[8:9]
; GFX10PLUS-NEXT: ; return to shader part epilog
%masked = call ptr addrspace(8) @llvm.ptrmask.p8.i128(ptr addrspace(8) %ptr, i128 %mask)
%masked = call ptr addrspace(8) @llvm.ptrmask.p8.i8(ptr addrspace(8) %ptr, i8 %mask)
ret ptr addrspace(8) %masked
}

define amdgpu_ps ptr addrspace(8) @s_ptrmask_buffer_resource_variable_i128_neg8(ptr addrspace(8) inreg %ptr) {
; GCN-LABEL: s_ptrmask_buffer_resource_variable_i128_neg8:
define amdgpu_ps ptr addrspace(8) @s_ptrmask_buffer_resource_variable_i8_neg8(ptr addrspace(8) inreg %ptr) {
; GCN-LABEL: s_ptrmask_buffer_resource_variable_i8_neg8:
; GCN: ; %bb.0:
; GCN-NEXT: s_mov_b32 s1, s3
; GCN-NEXT: s_and_b32 s0, s2, -8
; GCN-NEXT: s_mov_b32 s2, s4
; GCN-NEXT: s_mov_b32 s3, s5
; GCN-NEXT: ; return to shader part epilog
;
; GFX10PLUS-LABEL: s_ptrmask_buffer_resource_variable_i128_neg8:
; GFX10PLUS-LABEL: s_ptrmask_buffer_resource_variable_i8_neg8:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_mov_b32 s1, s3
; GFX10PLUS-NEXT: s_and_b32 s0, s2, -8
; GFX10PLUS-NEXT: s_mov_b32 s2, s4
; GFX10PLUS-NEXT: s_mov_b32 s3, s5
; GFX10PLUS-NEXT: ; return to shader part epilog
%masked = call ptr addrspace(8) @llvm.ptrmask.p8.i128(ptr addrspace(8) %ptr, i128 -8)
%masked = call ptr addrspace(8) @llvm.ptrmask.p8.i8(ptr addrspace(8) %ptr, i8 -8)
ret ptr addrspace(8) %masked
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/AlignmentFromAssumptions/amdgpu-crash.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; Test that we don't crash.
; RUN: opt < %s -passes=alignment-from-assumptions -S

target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7:8"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:8:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7:8"

%"core::str::CharIndices.29.66.90.114.138.149.165.173.181.197.205.213.229.387.398" = type { [0 x i64], i64, [0 x i64], { ptr, ptr }, [0 x i64] }
%"unwind::libunwind::_Unwind_Exception.9.51.75.99.123.147.163.171.179.195.203.211.227.385.396" = type { [0 x i64], i64, [0 x i64], ptr, [0 x i64], [6 x i64], [0 x i64] }
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
; CHECK: store i32 1, ptr addrspace(3) @IsSPMDMode
; CHECK-NOT: store i32 0, ptr addrspace(3) @IsSPMDMode
;
target datalayout = "A5-G1-ni:7:8:9-p7:160:256:256:32-p8:128:128-p9:192:256:256:32"
target datalayout = "A5-G1-ni:7:8:9-p7:160:256:256:32:48-p8:128:128-p9:192:256:256:32:48"
target triple = "amdgcn-amd-amdhsa"

%struct.ident_t = type { i32, i32, i32, i32, ptr }
Expand Down
39 changes: 18 additions & 21 deletions llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -41,12 +41,12 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) {
// Check that AMDGPU targets add -G1 if it's not present.
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "r600"), "e-p:32:32-G1");
// and that ANDGCN adds p7 and p8 as well.
EXPECT_EQ(
UpgradeDataLayoutString("e-p:64:64", "amdgcn"),
"e-p:64:64-G1-ni:7:8:9-p7:160:256:256:32-p8:128:128-p9:192:256:256:32");
EXPECT_EQ(
UpgradeDataLayoutString("e-p:64:64-G1", "amdgcn"),
"e-p:64:64-G1-ni:7:8:9-p7:160:256:256:32-p8:128:128-p9:192:256:256:32");
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64", "amdgcn"),
"e-p:64:64-G1-ni:7:8:9-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:"
"256:32");
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G1", "amdgcn"),
"e-p:64:64-G1-ni:7:8:9-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:"
"256:32");
// but that r600 does not.
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32-G1", "r600"), "e-p:32:32-G1");

Expand All @@ -60,8 +60,8 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) {
"amdgcn"),
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-"
"v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:"
"1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-p7:160:256:256:32-p8:128:128-"
"p9:192:256:256:32");
"1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-p7:160:256:256:32:48-p8:128:"
"128-p9:192:256:256:32:48");

// Check that RISCV64 upgrades -n64 to -n32:64.
EXPECT_EQ(UpgradeDataLayoutString("e-m:e-p:64:64-i64:64-i128:128-n64-S128",
Expand Down Expand Up @@ -144,23 +144,20 @@ TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {
// Check that AMDGPU targets don't add -G1 if there is already a -G flag.
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32-G2", "r600"), "e-p:32:32-G2");
EXPECT_EQ(UpgradeDataLayoutString("G2", "r600"), "G2");
EXPECT_EQ(
UpgradeDataLayoutString("e-p:64:64-G2", "amdgcn"),
"e-p:64:64-G2-ni:7:8:9-p7:160:256:256:32-p8:128:128-p9:192:256:256:32");
EXPECT_EQ(
UpgradeDataLayoutString("G2-e-p:64:64", "amdgcn"),
"G2-e-p:64:64-ni:7:8:9-p7:160:256:256:32-p8:128:128-p9:192:256:256:32");
EXPECT_EQ(
UpgradeDataLayoutString("e-p:64:64-G0", "amdgcn"),
"e-p:64:64-G0-ni:7:8:9-p7:160:256:256:32-p8:128:128-p9:192:256:256:32");
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G2", "amdgcn"),
"e-p:64:64-G2-ni:7:8:9-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48");
EXPECT_EQ(UpgradeDataLayoutString("G2-e-p:64:64", "amdgcn"),
"G2-e-p:64:64-ni:7:8:9-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48");
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G0", "amdgcn"),
"e-p:64:64-G0-ni:7:8:9-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48");

// Check that AMDGCN targets don't add already declared address space 7.
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-p7:64:64", "amdgcn"),
"e-p:64:64-p7:64:64-G1-ni:7:8:9-p8:128:128-p9:192:256:256:32");
"e-p:64:64-p7:64:64-G1-ni:7:8:9-p8:128:128:128:8:48-p9:192:256:256:32:48");
EXPECT_EQ(UpgradeDataLayoutString("p7:64:64-G2-e-p:64:64", "amdgcn"),
"p7:64:64-G2-e-p:64:64-ni:7:8:9-p8:128:128-p9:192:256:256:32");
"p7:64:64-G2-e-p:64:64-ni:7:8:9-p8:128:128:128:8:48-p9:192:256:256:32:48");
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-p7:64:64-G1", "amdgcn"),
"e-p:64:64-p7:64:64-G1-ni:7:8:9-p8:128:128-p9:192:256:256:32");
"e-p:64:64-p7:64:64-G1-ni:7:8:9-p8:128:128:128:8:48-p9:192:256:256:32:48");

// Check that SPIR & SPIRV targets don't add -G1 if there is already a -G
// flag.
Expand Down Expand Up @@ -192,7 +189,7 @@ TEST(DataLayoutUpgradeTest, EmptyDataLayout) {
// Check that AMDGPU targets add G1 if it's not present.
EXPECT_EQ(UpgradeDataLayoutString("", "r600"), "G1");
EXPECT_EQ(UpgradeDataLayoutString("", "amdgcn"),
"G1-ni:7:8:9-p7:160:256:256:32-p8:128:128-p9:192:256:256:32");
"G1-ni:7:8:9-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48");

// Check that SPIR & SPIRV targets add G1 if it's not present.
EXPECT_EQ(UpgradeDataLayoutString("", "spir"), "G1");
Expand Down
6 changes: 3 additions & 3 deletions mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -94,9 +94,9 @@ static Value getLaneId(ConversionPatternRewriter &rewriter, Location loc,
}
static constexpr StringLiteral amdgcnDataLayout =
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
"-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:"
"32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:"
"64-S32-A5-G1-ni:7:8:9";
"-p7:160:256:256:32:48-p8:128:128:128:8:48-p9:192:256:256:32:48-i64:64-v16:16"
"-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
"-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9";

namespace {
struct GPULaneIdOpToROCDL : ConvertOpToLLVMPattern<gpu::LaneIdOp> {
Expand Down
2 changes: 1 addition & 1 deletion mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
// RUN: mlir-opt %s -convert-gpu-to-rocdl='index-bitwidth=32' -split-input-file | FileCheck --check-prefix=CHECK32 %s

// CHECK-LABEL: @test_module
// CHECK-SAME: llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
// CHECK-SAME: llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32:48-p8:128:128-p9:192:256:256:32:48-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"

gpu.module @test_module {
// CHECK-LABEL: func @gpu_index_ops()
Expand Down
Loading
Loading