diff --git a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel index 6ac7889b026d3..4435cd0622378 100644 --- a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel @@ -43,7 +43,7 @@ cc_binary( gentbl_cc_library( name = "diagnostic_defs_gen", - tbl_outs = [out for c in [ + tbl_outs = dict([out for c in [ "AST", "Analysis", "Comment", @@ -59,47 +59,47 @@ gentbl_cc_library( "Serialization", ] for out in [ ( + "include/clang/Basic/Diagnostic%sKinds.inc" % c, [ "-gen-clang-diags-defs", "-clang-component=%s" % c, ], - "include/clang/Basic/Diagnostic%sKinds.inc" % c, ), ( + "include/clang/Basic/Diagnostic%sEnums.inc" % c, [ "-gen-clang-diags-enums", "-clang-component=%s" % c, ], - "include/clang/Basic/Diagnostic%sEnums.inc" % c, ), ( + "include/clang/Basic/Diagnostic%sCompatIDs.inc" % c, [ "-gen-clang-diags-compat-ids", "-clang-component=%s" % c, ], - "include/clang/Basic/Diagnostic%sCompatIDs.inc" % c, ), ( + "include/clang/Basic/Diagnostic%sInterface.inc" % c, [ "-gen-clang-diags-iface", "-clang-component=%s" % c, ], - "include/clang/Basic/Diagnostic%sInterface.inc" % c, ), ]] + [ ( - ["-gen-clang-diag-groups"], "include/clang/Basic/DiagnosticGroups.inc", + ["-gen-clang-diag-groups"], ), ( - ["-gen-clang-diags-index-name"], "include/clang/Basic/DiagnosticIndexName.inc", + ["-gen-clang-diags-index-name"], ), ( - ["-gen-clang-diags-compat-ids"], "include/clang/Basic/DiagnosticAllCompatIDs.inc", + ["-gen-clang-diags-compat-ids"], ), - ], + ]), tblgen = ":clang-tblgen", td_file = "include/clang/Basic/Diagnostic.td", deps = [":BasicTdFiles"], diff --git a/utils/bazel/llvm-project-overlay/lld/BUILD.bazel b/utils/bazel/llvm-project-overlay/lld/BUILD.bazel index 94bcf68896615..2c9f3e56e3113 100644 --- a/utils/bazel/llvm-project-overlay/lld/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/lld/BUILD.bazel @@ -8,7 +8,7 @@ load( ) load("//llvm:binary_alias.bzl", "binary_alias") load("//llvm:driver.bzl", "llvm_driver_cc_binary") -load("//llvm:tblgen.bzl", "gentbl") +load("//mlir:tblgen.bzl", "gentbl_cc_library") package( default_visibility = ["//visibility:public"], @@ -59,19 +59,14 @@ cc_library( ], ) -gentbl( +gentbl_cc_library( name = "elf_options_inc_gen", # See https://github.com/bazelbuild/bazel/issues/13803 strip_include_prefix = "ELF", - tbl_outs = [( - "-gen-opt-parser-defs", - "ELF/Options.inc", - )], + tbl_outs = {"ELF/Options.inc": ["-gen-opt-parser-defs"]}, tblgen = "//llvm:llvm-tblgen", td_file = "ELF/Options.td", - td_srcs = [ - "//llvm:include/llvm/Option/OptParser.td", - ], + deps = ["//llvm:OptParserTdFiles"], ) cc_library( @@ -116,19 +111,14 @@ cc_library( ], ) -gentbl( +gentbl_cc_library( name = "coff_options_inc_gen", # See https://github.com/bazelbuild/bazel/issues/13803 strip_include_prefix = "COFF", - tbl_outs = [( - "-gen-opt-parser-defs", - "COFF/Options.inc", - )], + tbl_outs = {"COFF/Options.inc": ["-gen-opt-parser-defs"]}, tblgen = "//llvm:llvm-tblgen", td_file = "COFF/Options.td", - td_srcs = [ - "//llvm:include/llvm/Option/OptParser.td", - ], + deps = ["//llvm:OptParserTdFiles"], ) cc_library( @@ -172,17 +162,12 @@ cc_library( ], ) -gentbl( +gentbl_cc_library( name = "mingw_options_inc_gen", - tbl_outs = [( - "-gen-opt-parser-defs", - "MinGW/Options.inc", - )], + tbl_outs = {"MinGW/Options.inc": ["-gen-opt-parser-defs"]}, tblgen = "//llvm:llvm-tblgen", td_file = "MinGW/Options.td", - td_srcs = [ - "//llvm:include/llvm/Option/OptParser.td", - ], + deps = ["//llvm:OptParserTdFiles"], ) cc_library( @@ -200,19 +185,14 @@ cc_library( ], ) -gentbl( +gentbl_cc_library( name = "macho_options_inc_gen", # See https://github.com/bazelbuild/bazel/issues/13803 strip_include_prefix = "MachO", - tbl_outs = [( - "-gen-opt-parser-defs", - "MachO/Options.inc", - )], + tbl_outs = {"MachO/Options.inc": ["-gen-opt-parser-defs"]}, tblgen = "//llvm:llvm-tblgen", td_file = "MachO/Options.td", - td_srcs = [ - "//llvm:include/llvm/Option/OptParser.td", - ], + deps = ["//llvm:OptParserTdFiles"], ) cc_library( @@ -246,19 +226,14 @@ cc_library( ], ) -gentbl( +gentbl_cc_library( name = "wasm_options_inc_gen", # See https://github.com/bazelbuild/bazel/issues/13803 strip_include_prefix = "wasm", - tbl_outs = [( - "-gen-opt-parser-defs", - "wasm/Options.inc", - )], + tbl_outs = {"wasm/Options.inc": ["-gen-opt-parser-defs"]}, tblgen = "//llvm:llvm-tblgen", td_file = "wasm/Options.td", - td_srcs = [ - "//llvm:include/llvm/Option/OptParser.td", - ], + deps = ["//llvm:OptParserTdFiles"], ) cc_library( diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel index 978f9e6b17222..00d44b2a49fbe 100644 --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -1645,12 +1645,7 @@ td_library( gentbl_filegroup( name = "omp_gen", - tbl_outs = [ - ( - ["--gen-directive-decl"], - "include/llvm/Frontend/OpenMP/OMP.h.inc", - ), - ], + tbl_outs = {"include/llvm/Frontend/OpenMP/OMP.h.inc": ["--gen-directive-decl"]}, tblgen = ":llvm-min-tblgen", td_file = "include/llvm/Frontend/OpenMP/OMP.td", deps = [":OmpTdFiles"], @@ -1658,12 +1653,7 @@ gentbl_filegroup( gentbl_filegroup( name = "omp_gen_impl", - tbl_outs = [ - ( - ["--gen-directive-impl"], - "include/llvm/Frontend/OpenMP/OMP.inc", - ), - ], + tbl_outs = {"include/llvm/Frontend/OpenMP/OMP.inc": ["--gen-directive-impl"]}, tblgen = ":llvm-min-tblgen", td_file = "include/llvm/Frontend/OpenMP/OMP.td", deps = [":OmpTdFiles"], @@ -1726,12 +1716,7 @@ td_library( gentbl_filegroup( name = "acc_gen", - tbl_outs = [ - ( - ["--gen-directive-decl"], - "include/llvm/Frontend/OpenACC/ACC.h.inc", - ), - ], + tbl_outs = {"include/llvm/Frontend/OpenACC/ACC.h.inc": ["--gen-directive-decl"]}, tblgen = ":llvm-min-tblgen", td_file = "include/llvm/Frontend/OpenACC/ACC.td", deps = [":AccTdFiles"], @@ -1739,12 +1724,7 @@ gentbl_filegroup( gentbl_filegroup( name = "acc_gen_impl", - tbl_outs = [ - ( - ["--gen-directive-impl"], - "include/llvm/Frontend/OpenACC/ACC.inc", - ), - ], + tbl_outs = {"include/llvm/Frontend/OpenACC/ACC.inc": ["--gen-directive-impl"]}, tblgen = ":llvm-min-tblgen", td_file = "include/llvm/Frontend/OpenACC/ACC.td", deps = [":AccTdFiles"], @@ -2064,219 +2044,84 @@ llvm_target_lib_list = [lib for lib in [ { "name": "AArch64", "short_name": "AArch64", - "tbl_outs": [ - ( - ["-gen-register-bank"], - "lib/Target/AArch64/AArch64GenRegisterBank.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/AArch64/AArch64GenRegisterInfo.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/AArch64/AArch64GenInstrInfo.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/AArch64/AArch64GenMCCodeEmitter.inc", - ), - ( - ["-gen-pseudo-lowering"], - "lib/Target/AArch64/AArch64GenMCPseudoLowering.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/AArch64/AArch64GenAsmWriter.inc", - ), - ( - [ - "-gen-asm-writer", - "-asmwriternum=1", - ], - "lib/Target/AArch64/AArch64GenAsmWriter1.inc", - ), - ( - ["-gen-asm-matcher"], - "lib/Target/AArch64/AArch64GenAsmMatcher.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/AArch64/AArch64GenDAGISel.inc", - ), - ( - ["-gen-fast-isel"], - "lib/Target/AArch64/AArch64GenFastISel.inc", - ), - ( - ["-gen-global-isel"], - "lib/Target/AArch64/AArch64GenGlobalISel.inc", - ), - ( - [ - "-gen-global-isel-combiner", - "-combiners=AArch64O0PreLegalizerCombiner", - ], - "lib/Target/AArch64/AArch64GenO0PreLegalizeGICombiner.inc", - ), - ( - [ - "-gen-global-isel-combiner", - "-combiners=AArch64PreLegalizerCombiner", - ], - "lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc", - ), - ( - [ - "-gen-global-isel-combiner", - "-combiners=AArch64PostLegalizerCombiner", - ], - "lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc", - ), - ( - [ - "-gen-global-isel-combiner", - "-combiners=AArch64PostLegalizerLowering", - ], - "lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/AArch64/AArch64GenCallingConv.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/AArch64/AArch64GenSubtargetInfo.inc", - ), - ( - ["-gen-disassembler", "--large-decoder-table"], - "lib/Target/AArch64/AArch64GenDisassemblerTables.inc", - ), - ( - ["-gen-searchable-tables"], - "lib/Target/AArch64/AArch64GenSystemOperands.inc", - ), - ( - ["-gen-exegesis"], - "lib/Target/AArch64/AArch64GenExegesis.inc", - ), - ], + "tbl_outs": { + "lib/Target/AArch64/AArch64GenRegisterBank.inc": ["-gen-register-bank"], + "lib/Target/AArch64/AArch64GenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/AArch64/AArch64GenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/AArch64/AArch64GenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/AArch64/AArch64GenMCPseudoLowering.inc": ["-gen-pseudo-lowering"], + "lib/Target/AArch64/AArch64GenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/AArch64/AArch64GenAsmWriter1.inc": [ + "-gen-asm-writer", + "-asmwriternum=1", + ], + "lib/Target/AArch64/AArch64GenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/AArch64/AArch64GenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/AArch64/AArch64GenFastISel.inc": ["-gen-fast-isel"], + "lib/Target/AArch64/AArch64GenGlobalISel.inc": ["-gen-global-isel"], + "lib/Target/AArch64/AArch64GenO0PreLegalizeGICombiner.inc": [ + "-gen-global-isel-combiner", + "-combiners=AArch64O0PreLegalizerCombiner", + ], + "lib/Target/AArch64/AArch64GenPreLegalizeGICombiner.inc": [ + "-gen-global-isel-combiner", + "-combiners=AArch64PreLegalizerCombiner", + ], + "lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc": [ + "-gen-global-isel-combiner", + "-combiners=AArch64PostLegalizerCombiner", + ], + "lib/Target/AArch64/AArch64GenPostLegalizeGILowering.inc": [ + "-gen-global-isel-combiner", + "-combiners=AArch64PostLegalizerLowering", + ], + "lib/Target/AArch64/AArch64GenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/AArch64/AArch64GenSubtargetInfo.inc": ["-gen-subtarget"], + "lib/Target/AArch64/AArch64GenDisassemblerTables.inc": [ + "-gen-disassembler", + "--large-decoder-table", + ], + "lib/Target/AArch64/AArch64GenSystemOperands.inc": ["-gen-searchable-tables"], + "lib/Target/AArch64/AArch64GenExegesis.inc": ["-gen-exegesis"], + }, }, { "name": "ARM", "short_name": "ARM", - "tbl_outs": [ - ( - ["-gen-register-bank"], - "lib/Target/ARM/ARMGenRegisterBank.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/ARM/ARMGenRegisterInfo.inc", - ), - ( - ["-gen-searchable-tables"], - "lib/Target/ARM/ARMGenSystemRegister.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/ARM/ARMGenInstrInfo.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/ARM/ARMGenMCCodeEmitter.inc", - ), - ( - ["-gen-pseudo-lowering"], - "lib/Target/ARM/ARMGenMCPseudoLowering.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/ARM/ARMGenAsmWriter.inc", - ), - ( - ["-gen-asm-matcher"], - "lib/Target/ARM/ARMGenAsmMatcher.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/ARM/ARMGenDAGISel.inc", - ), - ( - ["-gen-fast-isel"], - "lib/Target/ARM/ARMGenFastISel.inc", - ), - ( - ["-gen-global-isel"], - "lib/Target/ARM/ARMGenGlobalISel.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/ARM/ARMGenCallingConv.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/ARM/ARMGenSubtargetInfo.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/ARM/ARMGenDisassemblerTables.inc", - ), - ], + "tbl_outs": { + "lib/Target/ARM/ARMGenRegisterBank.inc": ["-gen-register-bank"], + "lib/Target/ARM/ARMGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/ARM/ARMGenSystemRegister.inc": ["-gen-searchable-tables"], + "lib/Target/ARM/ARMGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/ARM/ARMGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/ARM/ARMGenMCPseudoLowering.inc": ["-gen-pseudo-lowering"], + "lib/Target/ARM/ARMGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/ARM/ARMGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/ARM/ARMGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/ARM/ARMGenFastISel.inc": ["-gen-fast-isel"], + "lib/Target/ARM/ARMGenGlobalISel.inc": ["-gen-global-isel"], + "lib/Target/ARM/ARMGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/ARM/ARMGenSubtargetInfo.inc": ["-gen-subtarget"], + "lib/Target/ARM/ARMGenDisassemblerTables.inc": ["-gen-disassembler"], + }, }, { "name": "AMDGPU", "short_name": "AMDGPU", - "tbl_outs": [ - ( - ["-gen-register-bank"], - "lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/AMDGPU/AMDGPUGenMCCodeEmitter.inc", - ), - ( - ["-gen-pseudo-lowering"], - "lib/Target/AMDGPU/AMDGPUGenMCPseudoLowering.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/AMDGPU/AMDGPUGenAsmWriter.inc", - ), - ( - ["-gen-asm-matcher"], - "lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/AMDGPU/AMDGPUGenDAGISel.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/AMDGPU/AMDGPUGenCallingConv.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/AMDGPU/AMDGPUGenDisassemblerTables.inc", - ), - ( - ["-gen-searchable-tables"], - "lib/Target/AMDGPU/AMDGPUGenSearchableTables.inc", - ), - ], + "tbl_outs": { + "lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc": ["-gen-register-bank"], + "lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/AMDGPU/AMDGPUGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/AMDGPU/AMDGPUGenMCPseudoLowering.inc": ["-gen-pseudo-lowering"], + "lib/Target/AMDGPU/AMDGPUGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/AMDGPU/AMDGPUGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/AMDGPU/AMDGPUGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc": ["-gen-subtarget"], + "lib/Target/AMDGPU/AMDGPUGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/AMDGPU/AMDGPUGenSearchableTables.inc": ["-gen-searchable-tables"], + }, "tbl_deps": [ ":InstCombineTableGen", ":amdgpu_isel_target_gen", @@ -2286,481 +2131,169 @@ llvm_target_lib_list = [lib for lib in [ { "name": "AVR", "short_name": "AVR", - "tbl_outs": [ - ( - ["-gen-asm-matcher"], - "lib/Target/AVR/AVRGenAsmMatcher.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/AVR/AVRGenAsmWriter.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/AVR/AVRGenCallingConv.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/AVR/AVRGenDAGISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/AVR/AVRGenDisassemblerTables.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/AVR/AVRGenMCCodeEmitter.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/AVR/AVRGenInstrInfo.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/AVR/AVRGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/AVR/AVRGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/AVR/AVRGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/AVR/AVRGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/AVR/AVRGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/AVR/AVRGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/AVR/AVRGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/AVR/AVRGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/AVR/AVRGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/AVR/AVRGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/AVR/AVRGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "BPF", "short_name": "BPF", - "tbl_outs": [ - ( - ["-gen-register-bank"], - "lib/Target/BPF/BPFGenRegisterBank.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/BPF/BPFGenAsmWriter.inc", - ), - ( - ["-gen-asm-matcher"], - "lib/Target/BPF/BPFGenAsmMatcher.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/BPF/BPFGenCallingConv.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/BPF/BPFGenDAGISel.inc", - ), - ( - ["-gen-global-isel"], - "lib/Target/BPF/BPFGenGlobalISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/BPF/BPFGenDisassemblerTables.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/BPF/BPFGenMCCodeEmitter.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/BPF/BPFGenInstrInfo.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/BPF/BPFGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/BPF/BPFGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/BPF/BPFGenRegisterBank.inc": ["-gen-register-bank"], + "lib/Target/BPF/BPFGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/BPF/BPFGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/BPF/BPFGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/BPF/BPFGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/BPF/BPFGenGlobalISel.inc": ["-gen-global-isel"], + "lib/Target/BPF/BPFGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/BPF/BPFGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/BPF/BPFGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/BPF/BPFGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/BPF/BPFGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "Hexagon", "short_name": "Hexagon", - "tbl_outs": [ - ( - ["-gen-asm-matcher"], - "lib/Target/Hexagon/HexagonGenAsmMatcher.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/Hexagon/HexagonGenAsmWriter.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/Hexagon/HexagonGenCallingConv.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/Hexagon/HexagonGenDAGISel.inc", - ), - ( - ["-gen-dfa-packetizer"], - "lib/Target/Hexagon/HexagonGenDFAPacketizer.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/Hexagon/HexagonGenDisassemblerTables.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/Hexagon/HexagonGenInstrInfo.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/Hexagon/HexagonGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/Hexagon/HexagonGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/Hexagon/HexagonGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/Hexagon/HexagonGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/Hexagon/HexagonGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/Hexagon/HexagonGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/Hexagon/HexagonGenDFAPacketizer.inc": ["-gen-dfa-packetizer"], + "lib/Target/Hexagon/HexagonGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/Hexagon/HexagonGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/Hexagon/HexagonGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/Hexagon/HexagonGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "Lanai", "short_name": "Lanai", - "tbl_outs": [ - ( - ["-gen-asm-matcher"], - "lib/Target/Lanai/LanaiGenAsmMatcher.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/Lanai/LanaiGenAsmWriter.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/Lanai/LanaiGenCallingConv.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/Lanai/LanaiGenDAGISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/Lanai/LanaiGenDisassemblerTables.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/Lanai/LanaiGenMCCodeEmitter.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/Lanai/LanaiGenInstrInfo.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/Lanai/LanaiGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/Lanai/LanaiGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/Lanai/LanaiGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/Lanai/LanaiGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/Lanai/LanaiGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/Lanai/LanaiGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/Lanai/LanaiGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/Lanai/LanaiGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/Lanai/LanaiGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/Lanai/LanaiGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/Lanai/LanaiGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "LoongArch", "short_name": "LoongArch", - "tbl_outs": [ - ( - ["-gen-asm-matcher"], - "lib/Target/LoongArch/LoongArchGenAsmMatcher.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/LoongArch/LoongArchGenAsmWriter.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/LoongArch/LoongArchGenDAGISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/LoongArch/LoongArchGenDisassemblerTables.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/LoongArch/LoongArchGenInstrInfo.inc", - ), - ( - ["-gen-pseudo-lowering"], - "lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/LoongArch/LoongArchGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/LoongArch/LoongArchGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/LoongArch/LoongArchGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/LoongArch/LoongArchGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/LoongArch/LoongArchGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/LoongArch/LoongArchGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/LoongArch/LoongArchGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc": ["-gen-pseudo-lowering"], + "lib/Target/LoongArch/LoongArchGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/LoongArch/LoongArchGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "Mips", "short_name": "Mips", - "tbl_outs": [ - ( - ["-gen-asm-matcher"], - "lib/Target/Mips/MipsGenAsmMatcher.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/Mips/MipsGenAsmWriter.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/Mips/MipsGenCallingConv.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/Mips/MipsGenDAGISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/Mips/MipsGenDisassemblerTables.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/Mips/MipsGenMCCodeEmitter.inc", - ), - ( - ["-gen-exegesis"], - "lib/Target/Mips/MipsGenExegesis.inc", - ), - ( - ["-gen-fast-isel"], - "lib/Target/Mips/MipsGenFastISel.inc", - ), - ( - ["-gen-global-isel"], - "lib/Target/Mips/MipsGenGlobalISel.inc", - ), - ( - [ - "-gen-global-isel-combiner", - "-combiners=MipsPostLegalizerCombiner", - ], - "lib/Target/Mips/MipsGenPostLegalizeGICombiner.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/Mips/MipsGenInstrInfo.inc", - ), - ( - ["-gen-pseudo-lowering"], - "lib/Target/Mips/MipsGenMCPseudoLowering.inc", - ), - ( - ["-gen-register-bank"], - "lib/Target/Mips/MipsGenRegisterBank.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/Mips/MipsGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/Mips/MipsGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/Mips/MipsGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/Mips/MipsGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/Mips/MipsGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/Mips/MipsGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/Mips/MipsGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/Mips/MipsGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/Mips/MipsGenExegesis.inc": ["-gen-exegesis"], + "lib/Target/Mips/MipsGenFastISel.inc": ["-gen-fast-isel"], + "lib/Target/Mips/MipsGenGlobalISel.inc": ["-gen-global-isel"], + "lib/Target/Mips/MipsGenPostLegalizeGICombiner.inc": [ + "-gen-global-isel-combiner", + "-combiners=MipsPostLegalizerCombiner", + ], + "lib/Target/Mips/MipsGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/Mips/MipsGenMCPseudoLowering.inc": ["-gen-pseudo-lowering"], + "lib/Target/Mips/MipsGenRegisterBank.inc": ["-gen-register-bank"], + "lib/Target/Mips/MipsGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/Mips/MipsGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "MSP430", "short_name": "MSP430", - "tbl_outs": [ - ( - ["-gen-asm-matcher"], - "lib/Target/MSP430/MSP430GenAsmMatcher.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/MSP430/MSP430GenAsmWriter.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/MSP430/MSP430GenCallingConv.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/MSP430/MSP430GenDAGISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/MSP430/MSP430GenDisassemblerTables.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/MSP430/MSP430GenMCCodeEmitter.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/MSP430/MSP430GenInstrInfo.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/MSP430/MSP430GenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/MSP430/MSP430GenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/MSP430/MSP430GenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/MSP430/MSP430GenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/MSP430/MSP430GenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/MSP430/MSP430GenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/MSP430/MSP430GenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/MSP430/MSP430GenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/MSP430/MSP430GenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/MSP430/MSP430GenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/MSP430/MSP430GenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "NVPTX", "short_name": "NVPTX", - "tbl_outs": [ - ( - ["-gen-register-info"], - "lib/Target/NVPTX/NVPTXGenRegisterInfo.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/NVPTX/NVPTXGenInstrInfo.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/NVPTX/NVPTXGenAsmWriter.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/NVPTX/NVPTXGenDAGISel.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/NVPTX/NVPTXGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/NVPTX/NVPTXGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/NVPTX/NVPTXGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/NVPTX/NVPTXGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "PowerPC", "short_name": "PPC", - "tbl_outs": [ - ( - ["-gen-asm-writer"], - "lib/Target/PowerPC/PPCGenAsmWriter.inc", - ), - ( - ["-gen-asm-matcher"], - "lib/Target/PowerPC/PPCGenAsmMatcher.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/PowerPC/PPCGenMCCodeEmitter.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/PowerPC/PPCGenRegisterInfo.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/PowerPC/PPCGenInstrInfo.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/PowerPC/PPCGenDAGISel.inc", - ), - ( - ["-gen-fast-isel"], - "lib/Target/PowerPC/PPCGenFastISel.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/PowerPC/PPCGenCallingConv.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/PowerPC/PPCGenSubtargetInfo.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/PowerPC/PPCGenDisassemblerTables.inc", - ), - ( - ["-gen-register-bank"], - "lib/Target/PowerPC/PPCGenRegisterBank.inc", - ), - ( - ["-gen-global-isel"], - "lib/Target/PowerPC/PPCGenGlobalISel.inc", - ), - ( - ["-gen-exegesis"], - "lib/Target/PowerPC/PPCGenExegesis.inc", - ), - ], + "tbl_outs": { + "lib/Target/PowerPC/PPCGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/PowerPC/PPCGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/PowerPC/PPCGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/PowerPC/PPCGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/PowerPC/PPCGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/PowerPC/PPCGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/PowerPC/PPCGenFastISel.inc": ["-gen-fast-isel"], + "lib/Target/PowerPC/PPCGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/PowerPC/PPCGenSubtargetInfo.inc": ["-gen-subtarget"], + "lib/Target/PowerPC/PPCGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/PowerPC/PPCGenRegisterBank.inc": ["-gen-register-bank"], + "lib/Target/PowerPC/PPCGenGlobalISel.inc": ["-gen-global-isel"], + "lib/Target/PowerPC/PPCGenExegesis.inc": ["-gen-exegesis"], + }, }, { "name": "RISCV", "short_name": "RISCV", - "tbl_outs": [ - ( - ["-gen-asm-matcher"], - "lib/Target/RISCV/RISCVGenAsmMatcher.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/RISCV/RISCVGenAsmWriter.inc", - ), - ( - ["-gen-compress-inst-emitter"], - "lib/Target/RISCV/RISCVGenCompressInstEmitter.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/RISCV/RISCVGenDAGISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/RISCV/RISCVGenDisassemblerTables.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/RISCV/RISCVGenInstrInfo.inc", - ), - ( - ["-gen-macro-fusion-pred"], - "lib/Target/RISCV/RISCVGenMacroFusion.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/RISCV/RISCVGenMCCodeEmitter.inc", - ), - ( - ["-gen-pseudo-lowering"], - "lib/Target/RISCV/RISCVGenMCPseudoLowering.inc", - ), - ( - ["-gen-register-bank"], - "lib/Target/RISCV/RISCVGenRegisterBank.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/RISCV/RISCVGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/RISCV/RISCVGenSubtargetInfo.inc", - ), - ( - ["-gen-searchable-tables"], - "lib/Target/RISCV/RISCVGenSearchableTables.inc", - ), - ( - ["-gen-exegesis"], - "lib/Target/RISCV/RISCVGenExegesis.inc", - ), - ], + "tbl_outs": { + "lib/Target/RISCV/RISCVGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/RISCV/RISCVGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/RISCV/RISCVGenCompressInstEmitter.inc": ["-gen-compress-inst-emitter"], + "lib/Target/RISCV/RISCVGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/RISCV/RISCVGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/RISCV/RISCVGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/RISCV/RISCVGenMacroFusion.inc": ["-gen-macro-fusion-pred"], + "lib/Target/RISCV/RISCVGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/RISCV/RISCVGenMCPseudoLowering.inc": ["-gen-pseudo-lowering"], + "lib/Target/RISCV/RISCVGenRegisterBank.inc": ["-gen-register-bank"], + "lib/Target/RISCV/RISCVGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/RISCV/RISCVGenSubtargetInfo.inc": ["-gen-subtarget"], + "lib/Target/RISCV/RISCVGenSearchableTables.inc": ["-gen-searchable-tables"], + "lib/Target/RISCV/RISCVGenExegesis.inc": ["-gen-exegesis"], + }, "tbl_deps": [ ":riscv_isel_target_gen", ], @@ -2768,339 +2301,129 @@ llvm_target_lib_list = [lib for lib in [ { "name": "Sparc", "short_name": "Sparc", - "tbl_outs": [ - ( - ["-gen-asm-writer"], - "lib/Target/Sparc/SparcGenAsmWriter.inc", - ), - ( - ["-gen-asm-matcher"], - "lib/Target/Sparc/SparcGenAsmMatcher.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/Sparc/SparcGenMCCodeEmitter.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/Sparc/SparcGenRegisterInfo.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/Sparc/SparcGenInstrInfo.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/Sparc/SparcGenDAGISel.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/Sparc/SparcGenCallingConv.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/Sparc/SparcGenSubtargetInfo.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/Sparc/SparcGenDisassemblerTables.inc", - ), - ( - ["-gen-searchable-tables"], - "lib/Target/Sparc/SparcGenSearchableTables.inc", - ), - ], + "tbl_outs": { + "lib/Target/Sparc/SparcGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/Sparc/SparcGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/Sparc/SparcGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/Sparc/SparcGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/Sparc/SparcGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/Sparc/SparcGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/Sparc/SparcGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/Sparc/SparcGenSubtargetInfo.inc": ["-gen-subtarget"], + "lib/Target/Sparc/SparcGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/Sparc/SparcGenSearchableTables.inc": ["-gen-searchable-tables"], + }, }, { "name": "SPIRV", "short_name": "SPIRV", - "tbl_outs": [ - ( - ["-gen-asm-writer"], - "lib/Target/SPIRV/SPIRVGenAsmWriter.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/SPIRV/SPIRVGenMCCodeEmitter.inc", - ), - ( - ["-gen-global-isel"], - "lib/Target/SPIRV/SPIRVGenGlobalISel.inc", - ), - ( - [ - "-gen-global-isel-combiner", - "-combiners=SPIRVPreLegalizerCombiner", - ], - "lib/Target/SPIRV/SPIRVGenPreLegalizeGICombiner.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/SPIRV/SPIRVGenInstrInfo.inc", - ), - ( - ["-gen-register-bank"], - "lib/Target/SPIRV/SPIRVGenRegisterBank.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/SPIRV/SPIRVGenRegisterInfo.inc", - ), - ( - ["-gen-searchable-tables"], - "lib/Target/SPIRV/SPIRVGenTables.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/SPIRV/SPIRVGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/SPIRV/SPIRVGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/SPIRV/SPIRVGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/SPIRV/SPIRVGenGlobalISel.inc": ["-gen-global-isel"], + "lib/Target/SPIRV/SPIRVGenPreLegalizeGICombiner.inc": [ + "-gen-global-isel-combiner", + "-combiners=SPIRVPreLegalizerCombiner", + ], + "lib/Target/SPIRV/SPIRVGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/SPIRV/SPIRVGenRegisterBank.inc": ["-gen-register-bank"], + "lib/Target/SPIRV/SPIRVGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/SPIRV/SPIRVGenTables.inc": ["-gen-searchable-tables"], + "lib/Target/SPIRV/SPIRVGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "SystemZ", "short_name": "SystemZ", - "tbl_outs": [ - ( - ["-gen-asm-matcher"], - "lib/Target/SystemZ/SystemZGenAsmMatcher.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/SystemZ/SystemZGenGNUAsmWriter.inc", - ), - ( - [ - "-gen-asm-writer", - "-asmwriternum=1", - ], - "lib/Target/SystemZ/SystemZGenHLASMAsmWriter.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/SystemZ/SystemZGenCallingConv.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/SystemZ/SystemZGenDAGISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/SystemZ/SystemZGenDisassemblerTables.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/SystemZ/SystemZGenMCCodeEmitter.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/SystemZ/SystemZGenInstrInfo.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/SystemZ/SystemZGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/SystemZ/SystemZGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/SystemZ/SystemZGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/SystemZ/SystemZGenGNUAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/SystemZ/SystemZGenHLASMAsmWriter.inc": [ + "-gen-asm-writer", + "-asmwriternum=1", + ], + "lib/Target/SystemZ/SystemZGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/SystemZ/SystemZGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/SystemZ/SystemZGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/SystemZ/SystemZGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/SystemZ/SystemZGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/SystemZ/SystemZGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/SystemZ/SystemZGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "VE", "short_name": "VE", - "tbl_outs": [ - ( - ["-gen-asm-matcher"], - "lib/Target/VE/VEGenAsmMatcher.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/VE/VEGenAsmWriter.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/VE/VEGenCallingConv.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/VE/VEGenDAGISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/VE/VEGenDisassemblerTables.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/VE/VEGenMCCodeEmitter.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/VE/VEGenInstrInfo.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/VE/VEGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/VE/VEGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/VE/VEGenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/VE/VEGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/VE/VEGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/VE/VEGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/VE/VEGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/VE/VEGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/VE/VEGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/VE/VEGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/VE/VEGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, { "name": "WebAssembly", "short_name": "WebAssembly", - "tbl_outs": [ - ( - ["-gen-disassembler"], - "lib/Target/WebAssembly/WebAssemblyGenDisassemblerTables.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/WebAssembly/WebAssemblyGenAsmWriter.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc", - ), - ( - ["-gen-fast-isel"], - "lib/Target/WebAssembly/WebAssemblyGenFastISel.inc", - ), - ( - ["-gen-emitter"], - "lib/Target/WebAssembly/WebAssemblyGenMCCodeEmitter.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc", - ), - ( - ["-gen-asm-matcher"], - "lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc", - ), - ], + "tbl_outs": { + "lib/Target/WebAssembly/WebAssemblyGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/WebAssembly/WebAssemblyGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/WebAssembly/WebAssemblyGenFastISel.inc": ["-gen-fast-isel"], + "lib/Target/WebAssembly/WebAssemblyGenMCCodeEmitter.inc": ["-gen-emitter"], + "lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc": ["-gen-subtarget"], + "lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc": ["-gen-asm-matcher"], + }, }, { "name": "X86", "short_name": "X86", - "tbl_outs": [ - ( - ["-gen-register-bank"], - "lib/Target/X86/X86GenRegisterBank.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/X86/X86GenRegisterInfo.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/X86/X86GenDisassemblerTables.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/X86/X86GenInstrInfo.inc", - ), - ( - ["-gen-asm-writer"], - "lib/Target/X86/X86GenAsmWriter.inc", - ), - ( - [ - "-gen-asm-writer", - "-asmwriternum=1", - ], - "lib/Target/X86/X86GenAsmWriter1.inc", - ), - ( - ["-gen-asm-matcher"], - "lib/Target/X86/X86GenAsmMatcher.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/X86/X86GenDAGISel.inc", - ), - ( - ["-gen-fast-isel"], - "lib/Target/X86/X86GenFastISel.inc", - ), - ( - ["-gen-global-isel"], - "lib/Target/X86/X86GenGlobalISel.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/X86/X86GenCallingConv.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/X86/X86GenSubtargetInfo.inc", - ), - ( - [ - "-gen-x86-fold-tables", - "-asmwriternum=1", - ], - "lib/Target/X86/X86GenFoldTables.inc", - ), - ( - ["-gen-x86-instr-mapping"], - "lib/Target/X86/X86GenInstrMapping.inc", - ), - ( - ["-gen-exegesis"], - "lib/Target/X86/X86GenExegesis.inc", - ), - ( - [ - "-gen-x86-mnemonic-tables", - "-asmwriternum=1", - ], - "lib/Target/X86/X86GenMnemonicTables.inc", - ), - ], + "tbl_outs": { + "lib/Target/X86/X86GenRegisterBank.inc": ["-gen-register-bank"], + "lib/Target/X86/X86GenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/X86/X86GenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/X86/X86GenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/X86/X86GenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/X86/X86GenAsmWriter1.inc": [ + "-gen-asm-writer", + "-asmwriternum=1", + ], + "lib/Target/X86/X86GenAsmMatcher.inc": ["-gen-asm-matcher"], + "lib/Target/X86/X86GenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/X86/X86GenFastISel.inc": ["-gen-fast-isel"], + "lib/Target/X86/X86GenGlobalISel.inc": ["-gen-global-isel"], + "lib/Target/X86/X86GenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/X86/X86GenSubtargetInfo.inc": ["-gen-subtarget"], + "lib/Target/X86/X86GenFoldTables.inc": [ + "-gen-x86-fold-tables", + "-asmwriternum=1", + ], + "lib/Target/X86/X86GenInstrMapping.inc": ["-gen-x86-instr-mapping"], + "lib/Target/X86/X86GenExegesis.inc": ["-gen-exegesis"], + "lib/Target/X86/X86GenMnemonicTables.inc": [ + "-gen-x86-mnemonic-tables", + "-asmwriternum=1", + ], + }, }, { "name": "XCore", "short_name": "XCore", - "tbl_outs": [ - ( - ["-gen-asm-writer"], - "lib/Target/XCore/XCoreGenAsmWriter.inc", - ), - ( - ["-gen-callingconv"], - "lib/Target/XCore/XCoreGenCallingConv.inc", - ), - ( - ["-gen-dag-isel"], - "lib/Target/XCore/XCoreGenDAGISel.inc", - ), - ( - ["-gen-disassembler"], - "lib/Target/XCore/XCoreGenDisassemblerTables.inc", - ), - ( - ["-gen-instr-info"], - "lib/Target/XCore/XCoreGenInstrInfo.inc", - ), - ( - ["-gen-register-info"], - "lib/Target/XCore/XCoreGenRegisterInfo.inc", - ), - ( - ["-gen-subtarget"], - "lib/Target/XCore/XCoreGenSubtargetInfo.inc", - ), - ], + "tbl_outs": { + "lib/Target/XCore/XCoreGenAsmWriter.inc": ["-gen-asm-writer"], + "lib/Target/XCore/XCoreGenCallingConv.inc": ["-gen-callingconv"], + "lib/Target/XCore/XCoreGenDAGISel.inc": ["-gen-dag-isel"], + "lib/Target/XCore/XCoreGenDisassemblerTables.inc": ["-gen-disassembler"], + "lib/Target/XCore/XCoreGenInstrInfo.inc": ["-gen-instr-info"], + "lib/Target/XCore/XCoreGenRegisterInfo.inc": ["-gen-register-info"], + "lib/Target/XCore/XCoreGenSubtargetInfo.inc": ["-gen-subtarget"], + }, }, ] if lib["name"] in llvm_targets] @@ -3186,16 +2509,13 @@ gentbl_cc_library( [gentbl_cc_library( name = target["name"] + "CommonTableGen", strip_include_prefix = "lib/Target/" + target["name"], - tbl_outs = [( - # MSVC isn't happy with long string literals, while other compilers - # which support them get significant compile time improvements with - # them enabled. Ideally this flag would only be enabled on Windows via - # a select() on `@platforms//os:windows,`, but that would - # require refactoring gentbl from a macro into a rule. - # TODO(#92): Refactor gentbl to support this use - args + ["--long-string-literals=0"], - out, - ) for (args, out) in target["tbl_outs"]], + # MSVC isn't happy with long string literals, while other compilers + # which support them get significant compile time improvements with + # them enabled. Ideally this flag would only be enabled on Windows via + # a select() on `@platforms//os:windows,`, but that would + # require refactoring gentbl from a macro into a rule. + # TODO(#92): Refactor gentbl to support this use + tbl_outs = target["tbl_outs"], tblgen = ":llvm-tblgen", td_file = "lib/Target/" + target["name"] + "/" + target["short_name"] + ".td", td_srcs = glob( diff --git a/utils/bazel/llvm-project-overlay/llvm/tblgen.bzl b/utils/bazel/llvm-project-overlay/llvm/tblgen.bzl deleted file mode 100644 index d43390918e390..0000000000000 --- a/utils/bazel/llvm-project-overlay/llvm/tblgen.bzl +++ /dev/null @@ -1,81 +0,0 @@ -# This file is licensed under the Apache License v2.0 with LLVM Exceptions. -# See https://llvm.org/LICENSE.txt for license information. -# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception - -"""This file contains BUILD extensions for generating source code from LLVM's -table definition files using the TableGen tool. - -See http://llvm.org/cmds/tblgen.html for more information on the TableGen -tool. -TODO(chandlerc): Currently this expresses include-based dependencies as -"sources", and has no transitive understanding due to these files not being -correctly understood by the build system. -""" - -def gentbl( - name, - tblgen, - td_file, - td_srcs, - tbl_outs, - library = True, - tblgen_args = "", - **kwargs): - """gentbl() generates tabular code from a table definition file. - - Args: - name: The name of the build rule for use in dependencies. - tblgen: The binary used to produce the output. - td_file: The primary table definitions file. - td_srcs: A list of table definition files included transitively. - tbl_outs: A list of tuples (opts, out), where each opts is a string of - options passed to tblgen, and the out is the corresponding output file - produced. - library: Whether to bundle the generated files into a library. - tblgen_args: Extra arguments string to pass to the tblgen binary. - **kwargs: Keyword arguments to pass to subsidiary cc_library() rule. - """ - llvm_project_execroot_path = Label("//llvm:tblgen.bzl").workspace_root - - if td_file not in td_srcs: - td_srcs += [td_file] - for (opts, out) in tbl_outs: - rule_suffix = "_".join(opts.replace("-", "_").replace("=", "_").split(" ")) - native.genrule( - name = "%s_%s_genrule" % (name, rule_suffix), - srcs = td_srcs, - outs = [out], - tools = [tblgen], - message = "Generating code from table: %s" % td_file, - cmd = (("$(location %s) -I %s/llvm/include " + - "-I %s/clang/include " + - "-I $$(dirname $(location %s)) " + - "%s $(location %s) %s -o $@") % ( - tblgen, - llvm_project_execroot_path, - llvm_project_execroot_path, - td_file, - opts, - td_file, - tblgen_args, - )), - ) - - # For now, all generated files can be assumed to comprise public interfaces. - # If this is not true, you should specify library = False - # and list the generated '.inc' files in "srcs". - if library: - native.cc_library( - name = name, - # FIXME: This should be `textual_hdrs` instead of `hdrs`, but - # unfortunately that doesn't work with `strip_include_prefix`: - # https://github.com/bazelbuild/bazel/issues/12424 - # - # Once that issue is fixed and released, we can switch this to - # `textual_hdrs` and remove the feature disabling the various Bazel - # features (both current and under-development) that motivated the - # distinction between these two. - hdrs = [f for (_, f) in tbl_outs], - features = ["-parse_headers", "-header_modules"], - **kwargs - ) diff --git a/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel index 3904da8c90c30..c2ddf03ef28df 100644 --- a/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel @@ -114,15 +114,10 @@ td_library( gentbl_filegroup( name = "AffineOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=affine", - ], - "mlir/dialects/_affine_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_affine_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=affine", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/AffineOps.td", deps = [ @@ -156,15 +151,10 @@ td_library( gentbl_filegroup( name = "BuiltinOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=builtin", - ], - "mlir/dialects/_builtin_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_builtin_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=builtin", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/BuiltinOps.td", deps = [ @@ -196,22 +186,16 @@ td_library( gentbl_filegroup( name = "AMDGPUOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=amdgpu", - ], - "mlir/dialects/_amdgpu_enum_gen.py", - ), - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=amdgpu", - ], - "mlir/dialects/_amdgpu_ops_gen.py", - ), - ], + tbl_outs = { + "mlir/dialects/_amdgpu_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=amdgpu", + ], + "mlir/dialects/_amdgpu_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=amdgpu", + ], + }, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/AMDGPUOps.td", deps = [ @@ -245,22 +229,16 @@ td_library( gentbl_filegroup( name = "LinalgOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=linalg", - ], - "mlir/dialects/_linalg_enum_gen.py", - ), - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=linalg", - ], - "mlir/dialects/_linalg_ops_gen.py", - ), - ], + tbl_outs = { + "mlir/dialects/_linalg_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=linalg", + ], + "mlir/dialects/_linalg_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=linalg", + ], + }, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/LinalgOps.td", deps = [ @@ -306,22 +284,16 @@ filegroup( gentbl_filegroup( name = "LLVMOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=llvm", - ], - "mlir/dialects/_llvm_enum_gen.py", - ), - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=llvm", - ], - "mlir/dialects/_llvm_ops_gen.py", - ), - ], + tbl_outs = { + "mlir/dialects/_llvm_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=llvm", + ], + "mlir/dialects/_llvm_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=llvm", + ], + }, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/LLVMOps.td", deps = [ @@ -344,15 +316,10 @@ filegroup( gentbl_filegroup( name = "AsyncOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=async", - ], - "mlir/dialects/_async_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_async_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=async", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/AsyncOps.td", deps = [ @@ -384,22 +351,16 @@ filegroup( gentbl_filegroup( name = "ArithOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=arith", - ], - "mlir/dialects/_arith_enum_gen.py", - ), - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=arith", - ], - "mlir/dialects/_arith_ops_gen.py", - ), - ], + tbl_outs = { + "mlir/dialects/_arith_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=arith", + ], + "mlir/dialects/_arith_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=arith", + ], + }, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/ArithOps.td", deps = [ @@ -434,15 +395,10 @@ td_library( gentbl_filegroup( name = "BufferizationEnumPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=bufferization", - ], - "mlir/dialects/_bufferization_enum_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_bufferization_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=bufferization", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/BufferizationEnums.td", deps = [ @@ -452,15 +408,10 @@ gentbl_filegroup( gentbl_filegroup( name = "BufferizationOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=bufferization", - ], - "mlir/dialects/_bufferization_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_bufferization_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=bufferization", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/BufferizationOps.td", deps = [ @@ -483,15 +434,10 @@ filegroup( gentbl_filegroup( name = "ComplexOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=complex", - ], - "mlir/dialects/_complex_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_complex_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=complex", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/ComplexOps.td", deps = [ @@ -514,15 +460,10 @@ filegroup( gentbl_filegroup( name = "ControlFlowOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=cf", - ], - "mlir/dialects/_cf_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_cf_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=cf", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/ControlFlowOps.td", deps = [ @@ -545,15 +486,10 @@ filegroup( gentbl_filegroup( name = "EmitCPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=emitc", - ], - "mlir/dialects/_emitc_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_emitc_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=emitc", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/EmitC.td", deps = [ @@ -575,22 +511,16 @@ filegroup( gentbl_filegroup( name = "IndexOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=index", - ], - "mlir/dialects/_index_enum_gen.py", - ), - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=index", - ], - "mlir/dialects/_index_ops_gen.py", - ), - ], + tbl_outs = { + "mlir/dialects/_index_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=index", + ], + "mlir/dialects/_index_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=index", + ], + }, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/IndexOps.td", deps = [ @@ -613,15 +543,10 @@ filegroup( gentbl_filegroup( name = "MathOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=math", - ], - "mlir/dialects/_math_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_math_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=math", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/MathOps.td", deps = [ @@ -644,15 +569,10 @@ filegroup( gentbl_filegroup( name = "MemRefOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=memref", - ], - "mlir/dialects/_memref_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_memref_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=memref", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/MemRefOps.td", deps = [ @@ -675,15 +595,10 @@ filegroup( gentbl_filegroup( name = "MLProgramOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=ml_program", - ], - "mlir/dialects/_ml_program_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_ml_program_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=ml_program", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/MLProgramOps.td", deps = [ @@ -706,15 +621,10 @@ filegroup( gentbl_filegroup( name = "OpenMPOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=omp", - ], - "mlir/dialects/_omp_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_omp_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=omp", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/OpenMPOps.td", deps = [ @@ -737,15 +647,10 @@ filegroup( gentbl_filegroup( name = "PDLPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=pdl", - ], - "mlir/dialects/_pdl_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_pdl_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=pdl", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/PDLOps.td", deps = [ @@ -775,15 +680,10 @@ filegroup( gentbl_filegroup( name = "PythonTestPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=python_test", - ], - "mlir/dialects/_python_test_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_python_test_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=python_test", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "//mlir/test/python:python_test_ops.td", deps = [ @@ -834,22 +734,16 @@ td_library( gentbl_filegroup( name = "GPUOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=gpu", - ], - "mlir/dialects/_gpu_enum_gen.py", - ), - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=gpu", - ], - "mlir/dialects/_gpu_ops_gen.py", - ), - ], + tbl_outs = { + "mlir/dialects/_gpu_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=gpu", + ], + "mlir/dialects/_gpu_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=gpu", + ], + }, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/GPUOps.td", deps = [ @@ -891,22 +785,16 @@ td_library( gentbl_filegroup( name = "NVGPUOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=nvgpu", - ], - "mlir/dialects/_nvgpu_enum_gen.py", - ), - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=nvgpu", - ], - "mlir/dialects/_nvgpu_ops_gen.py", - ), - ], + tbl_outs = { + "mlir/dialects/_nvgpu_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=nvgpu", + ], + "mlir/dialects/_nvgpu_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=nvgpu", + ], + }, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/NVGPUOps.td", deps = [ @@ -938,22 +826,16 @@ td_library( gentbl_filegroup( name = "NVVMOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=nvvm", - ], - "mlir/dialects/_nvvm_enum_gen.py", - ), - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=nvvm", - ], - "mlir/dialects/_nvvm_ops_gen.py", - ), - ], + tbl_outs = { + "mlir/dialects/_nvvm_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=nvvm", + ], + "mlir/dialects/_nvvm_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=nvvm", + ], + }, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/NVVMOps.td", deps = [ @@ -985,15 +867,10 @@ td_library( gentbl_filegroup( name = "ROCDLOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=rocdl", - ], - "mlir/dialects/_rocdl_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_rocdl_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=rocdl", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/ROCDLOps.td", deps = [ @@ -1015,15 +892,10 @@ filegroup( gentbl_filegroup( name = "SCFPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=scf", - ], - "mlir/dialects/_scf_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_scf_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=scf", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/SCFOps.td", deps = [ @@ -1046,15 +918,10 @@ filegroup( gentbl_filegroup( name = "ShapeOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=shape", - ], - "mlir/dialects/_shape_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_shape_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=shape", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/ShapeOps.td", deps = [ @@ -1087,15 +954,10 @@ td_library( gentbl_filegroup( name = "FuncPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=func", - ], - "mlir/dialects/_func_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_func_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=func", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/FuncOps.td", deps = [ @@ -1128,22 +990,16 @@ td_library( gentbl_filegroup( name = "SMTOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=smt", - ], - "mlir/dialects/_smt_enum_gen.py", - ), - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=smt", - ], - "mlir/dialects/_smt_ops_gen.py", - ), - ], + tbl_outs = { + "mlir/dialects/_smt_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=smt", + ], + "mlir/dialects/_smt_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=smt", + ], + }, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/SMTOps.td", deps = [ @@ -1175,15 +1031,10 @@ td_library( gentbl_filegroup( name = "SparseTensorEnumPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=sparse_tensor", - ], - "mlir/dialects/_sparse_tensor_enum_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_sparse_tensor_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=sparse_tensor", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/SparseTensorAttrDefs.td", deps = [ @@ -1193,15 +1044,10 @@ gentbl_filegroup( gentbl_filegroup( name = "SparseTensorOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=sparse_tensor", - ], - "mlir/dialects/_sparse_tensor_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_sparse_tensor_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=sparse_tensor", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/SparseTensorOps.td", deps = [ @@ -1224,15 +1070,10 @@ filegroup( gentbl_filegroup( name = "SPIRVOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=spirv", - ], - "mlir/dialects/_spirv_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_spirv_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=spirv", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/SPIRVOps.td", deps = [ @@ -1265,15 +1106,10 @@ td_library( gentbl_filegroup( name = "TensorOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=tensor", - ], - "mlir/dialects/_tensor_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_tensor_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=tensor", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/TensorOps.td", deps = [ @@ -1295,15 +1131,10 @@ filegroup( gentbl_filegroup( name = "TosaOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=tosa", - ], - "mlir/dialects/_tosa_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_tosa_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=tosa", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/TosaOps.td", deps = [ @@ -1326,15 +1157,10 @@ filegroup( gentbl_filegroup( name = "TransformEnumPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=transform", - ], - "mlir/dialects/_transform_enum_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_transform_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/TransformAttrs.td", deps = [ @@ -1347,15 +1173,10 @@ gentbl_filegroup( gentbl_filegroup( name = "TransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - ], - "mlir/dialects/_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/TransformOps.td", deps = [ @@ -1368,16 +1189,11 @@ gentbl_filegroup( gentbl_filegroup( name = "BufferizationTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=bufferization_transform", - ], - "mlir/dialects/_bufferization_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_bufferization_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=bufferization_transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/BufferizationTransformOps.td", deps = [ @@ -1387,16 +1203,11 @@ gentbl_filegroup( gentbl_filegroup( name = "GPUTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=gpu_transform", - ], - "mlir/dialects/_gpu_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_gpu_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=gpu_transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/GPUTransformOps.td", deps = [ @@ -1410,15 +1221,10 @@ gentbl_filegroup( gentbl_filegroup( name = "StructureTransformEnumPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=transform", - ], - "mlir/dialects/_structured_transform_enum_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_structured_transform_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/LinalgStructuredTransformEnums.td", deps = [ @@ -1432,16 +1238,11 @@ gentbl_filegroup( gentbl_filegroup( name = "StructuredTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=structured_transform", - ], - "mlir/dialects/_structured_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_structured_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=structured_transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/LinalgStructuredTransformOps.td", deps = [ @@ -1455,16 +1256,11 @@ gentbl_filegroup( gentbl_filegroup( name = "LoopTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=loop_transform", - ], - "mlir/dialects/_loop_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_loop_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=loop_transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/SCFLoopTransformOps.td", deps = [ @@ -1478,16 +1274,11 @@ gentbl_filegroup( gentbl_filegroup( name = "MemRefTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=memref_transform", - ], - "mlir/dialects/_memref_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_memref_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=memref_transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/MemRefTransformOps.td", deps = [ @@ -1497,16 +1288,11 @@ gentbl_filegroup( gentbl_filegroup( name = "NVGPUTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=nvgpu_transform", - ], - "mlir/dialects/_nvgpu_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_nvgpu_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=nvgpu_transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/NVGPUTransformOps.td", deps = [ @@ -1516,16 +1302,11 @@ gentbl_filegroup( gentbl_filegroup( name = "PDLTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=transform_pdl_extension", - ], - "mlir/dialects/_transform_pdl_extension_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_transform_pdl_extension_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=transform_pdl_extension", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/TransformPDLExtensionOps.td", deps = [ @@ -1539,16 +1320,11 @@ gentbl_filegroup( gentbl_filegroup( name = "SparseTensorTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=sparse_tensor_transform", - ], - "mlir/dialects/_sparse_tensor_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_sparse_tensor_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=sparse_tensor_transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/SparseTensorTransformOps.td", deps = [ @@ -1558,16 +1334,11 @@ gentbl_filegroup( gentbl_filegroup( name = "TensorTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=tensor_transform", - ], - "mlir/dialects/_tensor_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_tensor_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=tensor_transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/TensorTransformOps.td", deps = [ @@ -1577,15 +1348,10 @@ gentbl_filegroup( gentbl_filegroup( name = "VectorTransformEnumPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=transform", - ], - "mlir/dialects/_vector_transform_enum_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_vector_transform_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/VectorTransformsBase.td", deps = [ @@ -1597,16 +1363,11 @@ gentbl_filegroup( gentbl_filegroup( name = "VectorTransformOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=transform", - "-dialect-extension=vector_transform", - ], - "mlir/dialects/_vector_transform_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_vector_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=vector_transform", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/VectorTransformOps.td", deps = [ @@ -1657,15 +1418,10 @@ filegroup( gentbl_filegroup( name = "VectorOpsPyGen", - tbl_outs = [ - ( - [ - "-gen-python-op-bindings", - "-bind-dialect=vector", - ], - "mlir/dialects/_vector_ops_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_vector_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=vector", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/VectorOps.td", deps = [ @@ -1677,15 +1433,10 @@ gentbl_filegroup( gentbl_filegroup( name = "VectorAttributesPyGen", - tbl_outs = [ - ( - [ - "-gen-python-enum-bindings", - "-bind-dialect=vector", - ], - "mlir/dialects/_vector_enum_gen.py", - ), - ], + tbl_outs = {"mlir/dialects/_vector_enum_gen.py": [ + "-gen-python-enum-bindings", + "-bind-dialect=vector", + ]}, tblgen = "//mlir:mlir-tblgen", td_file = "mlir/dialects/VectorAttributes.td", deps = [ diff --git a/utils/bazel/llvm-project-overlay/mlir/tblgen.bzl b/utils/bazel/llvm-project-overlay/mlir/tblgen.bzl index b0012848100be..16a7ecadeaffa 100644 --- a/utils/bazel/llvm-project-overlay/mlir/tblgen.bzl +++ b/utils/bazel/llvm-project-overlay/mlir/tblgen.bzl @@ -321,9 +321,9 @@ def gentbl_filegroup( name: The name of the generated filegroup rule for use in dependencies. tblgen: The binary used to produce the output. td_file: The primary table definitions file. - tbl_outs: A list of tuples ([opts], out), where each 'opts' is a list of - options passed to tblgen, each option being a string, and 'out' is the - corresponding output file produced. + tbl_outs: Either a dict {out: [opts]} or a list of tuples ([opts], out), + where each 'opts' is a list of options passed to tblgen, each option + being a string, and 'out' is the corresponding output file produced. td_srcs: See gentbl_rule.td_srcs includes: See gentbl_rule.includes deps: See gentbl_rule.deps @@ -333,6 +333,8 @@ def gentbl_filegroup( **kwargs: Extra keyword arguments to pass to all generated rules. """ + if type(tbl_outs) == type({}): + tbl_outs = [(v, k) for k, v in tbl_outs.items()] for (opts, out) in tbl_outs: first_opt = opts[0] if opts else "" rule_suffix = "_{}_{}".format( @@ -409,8 +411,6 @@ def gentbl_cc_library( **kwargs: Extra keyword arguments to pass to all generated rules. """ - if type(tbl_outs) == type({}): - tbl_outs = [(v, k) for k, v in tbl_outs.items()] filegroup_name = name + "_filegroup" gentbl_filegroup( name = filegroup_name, @@ -510,22 +510,16 @@ def gentbl_sharded_ops( name = cc_lib_name, strip_include_prefix = strip_include_prefix, includes = includes, - tbl_outs = [ - ( - [ - "-gen-op-defs", - "-op-shard-count=" + str(shard_count), - ], - src_out, - ), - ( - [ - "-gen-op-decls", - "-op-shard-count=" + str(shard_count), - ], - hdr_out, - ), - ], + tbl_outs = { + src_out: [ + "-gen-op-defs", + "-op-shard-count=" + str(shard_count), + ], + hdr_out: [ + "-gen-op-decls", + "-op-shard-count=" + str(shard_count), + ], + }, tblgen = tblgen, td_file = td_file, test = test,