From 25c647a4f52fca87c548d1e34f55ed876967557a Mon Sep 17 00:00:00 2001 From: Maryam Moghadas Date: Tue, 29 Apr 2025 15:48:35 +0000 Subject: [PATCH 1/3] [VPlan][LV] Fix invalid truncation in VPScalarIVStepsRecipe Replace CreateTrunc with CreateSExtOrTrunc in VPScalarIVStepsRecipe to safely handle type conversion. This prevents assertion failures from invalid truncation when StartIdx0 has a smaller integer type than IntStepTy. The assertion was introduced by commit 783a846. --- .../lib/Transforms/Vectorize/VPlanRecipes.cpp | 2 +- .../PowerPC/vplan-scalarivsext-crash.ll | 31 +++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index 75d056026025a..6ca43eec63dd4 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -2134,7 +2134,7 @@ void VPScalarIVStepsRecipe::execute(VPTransformState &State) { Builder.CreateMul(StartIdx0, ConstantInt::get(StartIdx0->getType(), getUnrollPart(*this))); } - StartIdx0 = Builder.CreateTrunc(StartIdx0, IntStepTy); + StartIdx0 = Builder.CreateSExtOrTrunc(StartIdx0, IntStepTy); } if (!FirstLaneOnly && State.VF.isScalable()) { diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll new file mode 100644 index 0000000000000..66b54a29b913c --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll @@ -0,0 +1,31 @@ +; RUN: opt -passes=loop-vectorize -S < %s > /dev/null +; REQUIRES: asserts + +target datalayout = "E-m:a-p:32:32-Fi32-i64:64-n32" +target triple = "powerpc-ibm-aix7.2.0.0" + +define void @__power_mod_NMOD_power_init(ptr %a, ptr %b, i32 %n) { +entry: + br label %loop_entry + +loop_exit: ; preds = %loop_header + br label %loop_entry + +loop_entry: ; preds = %loop_exit, %entry + %sum.0 = phi double [ 0.000000e+00, %entry ], [ %sum.1, %loop_exit ] + %x = load double, ptr %a, align 8 + br label %loop_header + +loop_header: ; preds = %loop_body, %loop_entry + %sum.1 = phi double [ %sum.0, %loop_entry ], [ %sum.next, %loop_body ] + %i = phi i32 [ 0, %loop_entry ], [ %i.next, %loop_body ] + %cond = icmp sgt i32 %i, %n + br i1 %cond, label %loop_exit, label %loop_body + +loop_body: ; preds = %loop_header + store double %sum.1, ptr %b, align 8 + %sum.next = fadd reassoc double %sum.1, %x + %i.next = add i32 %i, 1 + br label %loop_header +} + From c478c6fdca52452bbfb00ffc157864096c6707c1 Mon Sep 17 00:00:00 2001 From: Maryam Moghadas Date: Tue, 29 Apr 2025 17:12:55 +0000 Subject: [PATCH 2/3] Use -disable-output instead of redirecting to /dev/null in the test --- .../LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll index 66b54a29b913c..3bb9354f56ab4 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll @@ -1,4 +1,4 @@ -; RUN: opt -passes=loop-vectorize -S < %s > /dev/null +; RUN: opt -passes=loop-vectorize -disable-output -S < %s ; REQUIRES: asserts target datalayout = "E-m:a-p:32:32-Fi32-i64:64-n32" From e0851d8940c9115211b3791e21160c48f80922e2 Mon Sep 17 00:00:00 2001 From: Maryam Moghadas Date: Tue, 29 Apr 2025 19:16:50 +0000 Subject: [PATCH 3/3] Use a single loop and validate test output --- .../PowerPC/vplan-scalarivsext-crash.ll | 92 ++++++++++++++++--- 1 file changed, 77 insertions(+), 15 deletions(-) diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll index 3bb9354f56ab4..34b8deaa8de03 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-scalarivsext-crash.ll @@ -1,31 +1,93 @@ -; RUN: opt -passes=loop-vectorize -disable-output -S < %s -; REQUIRES: asserts +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -passes=loop-vectorize -S %s 2>&1 | FileCheck %s target datalayout = "E-m:a-p:32:32-Fi32-i64:64-n32" target triple = "powerpc-ibm-aix7.2.0.0" -define void @__power_mod_NMOD_power_init(ptr %a, ptr %b, i32 %n) { +define void @test_iv_trunc_crash(ptr %a, ptr %b, i32 %n) { +; CHECK-LABEL: define void @test_iv_trunc_crash( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[N:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: [[SUM_0:%.*]] = fadd reassoc double 0.000000e+00, 0.000000e+00 +; CHECK-NEXT: [[X:%.*]] = load double, ptr [[A]], align 8 +; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[TMP0]], 1 +; CHECK-NEXT: [[SMAX1:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP1]], i64 0) +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[SMAX1]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = add nuw i32 [[TMP2]], 1 +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP3]], 8 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] +; CHECK: [[VECTOR_SCEVCHECK]]: +; CHECK-NEXT: [[TMP4:%.*]] = sext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP4]], 1 +; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP5]], i64 0) +; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[SMAX]] to i32 +; CHECK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i64 [[SMAX]], 4294967295 +; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]] +; CHECK-NEXT: br i1 [[TMP9]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP3]], 8 +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[N_MOD_VF]], 0 +; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 8, i32 [[N_MOD_VF]] +; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP3]], [[TMP11]] +; CHECK-NEXT: [[DOTCAST:%.*]] = sitofp i32 [[N_VEC]] to double +; CHECK-NEXT: [[TMP12:%.*]] = fmul reassoc double [[X]], [[DOTCAST]] +; CHECK-NEXT: [[TMP13:%.*]] = fadd reassoc double [[SUM_0]], [[TMP12]] +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[DOTCAST2:%.*]] = sitofp i32 [[INDEX]] to double +; CHECK-NEXT: [[TMP14:%.*]] = fmul reassoc double [[X]], [[DOTCAST2]] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = fadd reassoc double [[SUM_0]], [[TMP14]] +; CHECK-NEXT: [[TMP15:%.*]] = fmul reassoc double 7.000000e+00, [[X]] +; CHECK-NEXT: [[TMP16:%.*]] = fadd reassoc double [[OFFSET_IDX]], [[TMP15]] +; CHECK-NEXT: store double [[TMP16]], ptr [[B]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8 +; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br label %[[SCALAR_PH]] +; CHECK: [[SCALAR_PH]]: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi double [ [[TMP13]], %[[MIDDLE_BLOCK]] ], [ [[SUM_0]], %[[ENTRY]] ], [ [[SUM_0]], %[[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL3:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] +; CHECK: [[LOOP_HEADER]]: +; CHECK-NEXT: [[SUM_1:%.*]] = phi double [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP_BODY:.*]] ] +; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL3]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[LOOP_BODY]] ] +; CHECK-NEXT: [[COND:%.*]] = icmp sgt i32 [[I]], [[N]] +; CHECK-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP_BODY]] +; CHECK: [[LOOP_BODY]]: +; CHECK-NEXT: store double [[SUM_1]], ptr [[B]], align 8 +; CHECK-NEXT: [[SUM_NEXT]] = fadd reassoc double [[SUM_1]], [[X]] +; CHECK-NEXT: [[I_NEXT]] = add i32 [[I]], 1 +; CHECK-NEXT: br label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; entry: - br label %loop_entry - -loop_exit: ; preds = %loop_header - br label %loop_entry - -loop_entry: ; preds = %loop_exit, %entry - %sum.0 = phi double [ 0.000000e+00, %entry ], [ %sum.1, %loop_exit ] + %sum.0 = fadd reassoc double 0.0, 0.0 %x = load double, ptr %a, align 8 br label %loop_header -loop_header: ; preds = %loop_body, %loop_entry - %sum.1 = phi double [ %sum.0, %loop_entry ], [ %sum.next, %loop_body ] - %i = phi i32 [ 0, %loop_entry ], [ %i.next, %loop_body ] +loop_header: ; preds = %loop_body, %entry + %sum.1 = phi double [ %sum.0, %entry ], [ %sum.next, %loop_body ] + %i = phi i32 [ 0, %entry ], [ %i.next, %loop_body ] %cond = icmp sgt i32 %i, %n - br i1 %cond, label %loop_exit, label %loop_body + br i1 %cond, label %exit, label %loop_body loop_body: ; preds = %loop_header store double %sum.1, ptr %b, align 8 %sum.next = fadd reassoc double %sum.1, %x %i.next = add i32 %i, 1 br label %loop_header -} +exit: + ret void +} +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]} +;.