From bd71a9d0e63829114422480a38fe8959ccf63c91 Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Tue, 29 Apr 2025 16:06:27 +0000 Subject: [PATCH 1/3] [MISched] Add statistics to quantify scheduling When diagnosing scheduler issues it can be useful to know how scheduling changes the order of instructions, particularly for large functions when it's not trivial to figure out from the debug output by looking at the scheduling unit (SU) IDs. This adds pre-RA and post-RA statistics to track 1) the number of instructions that remain in source order after scheduling and 2) the total number of instructions scheduled, to compare 1) against. --- llvm/include/llvm/CodeGen/MachineScheduler.h | 3 ++ llvm/lib/CodeGen/MachineScheduler.cpp | 33 ++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h index bc00d0b4ff852..1660fe6864a92 100644 --- a/llvm/include/llvm/CodeGen/MachineScheduler.h +++ b/llvm/include/llvm/CodeGen/MachineScheduler.h @@ -1196,6 +1196,9 @@ class GenericSchedulerBase : public MachineSchedStrategy { const MachineSchedContext *Context; const TargetSchedModel *SchedModel = nullptr; const TargetRegisterInfo *TRI = nullptr; + unsigned TopIdx = 0; + unsigned BotIdx = 0; + unsigned NumRegionInstrs = 0; MachineSchedPolicy RegionPolicy; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 31acfef45cfee..415b53cc19856 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -74,6 +74,14 @@ using namespace llvm; #define DEBUG_TYPE "machine-scheduler" +STATISTIC(NumInstrsInSourceOrderPreRA, + "Number of instructions in source order after pre-RA scheduling"); +STATISTIC(NumInstrsInSourceOrderPostRA, + "Number of instructions in source order after post-RA scheduling"); +STATISTIC(NumInstrsScheduledPreRA, + "Number of instructions scheduled by pre-RA scheduler"); +STATISTIC(NumInstrsScheduledPostRA, + "Number of instructions scheduled by post-RA scheduler"); STATISTIC(NumClustered, "Number of load/store pairs clustered"); namespace llvm { @@ -3505,6 +3513,9 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin, RegionPolicy.OnlyBottomUp = false; RegionPolicy.OnlyTopDown = false; } + + this->BotIdx = NumRegionInstrs - 1; + this->NumRegionInstrs = NumRegionInstrs; } void GenericScheduler::dumpPolicy() const { @@ -3981,6 +3992,17 @@ SUnit *GenericScheduler::pickNode(bool &IsTopNode) { LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr()); + + if (IsTopNode) { + if (SU->NodeNum == TopIdx++) + ++NumInstrsInSourceOrderPreRA; + } else { + if (SU->NodeNum == BotIdx--) + ++NumInstrsInSourceOrderPreRA; + } + + NumInstrsScheduledPreRA += 1; + return SU; } @@ -4323,6 +4345,17 @@ SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) { LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr()); + + if (IsTopNode) { + if (SU->NodeNum == TopIdx++) + ++NumInstrsInSourceOrderPostRA; + } else { + if (SU->NodeNum == BotIdx--) + ++NumInstrsInSourceOrderPostRA; + } + + NumInstrsScheduledPostRA += 1; + return SU; } From efd40cad5b307cf4f0ce28c85b8a68dbf07dfb13 Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Fri, 2 May 2025 08:16:00 +0000 Subject: [PATCH 2/3] address comments --- llvm/lib/CodeGen/MachineScheduler.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 415b53cc19856..49d44b71aee5c 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -3514,7 +3514,7 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin, RegionPolicy.OnlyTopDown = false; } - this->BotIdx = NumRegionInstrs - 1; + BotIdx = NumRegionInstrs - 1; this->NumRegionInstrs = NumRegionInstrs; } @@ -3997,6 +3997,7 @@ SUnit *GenericScheduler::pickNode(bool &IsTopNode) { if (SU->NodeNum == TopIdx++) ++NumInstrsInSourceOrderPreRA; } else { + assert(BotIdx < NumRegionInstrs && "out of bounds"); if (SU->NodeNum == BotIdx--) ++NumInstrsInSourceOrderPreRA; } @@ -4350,6 +4351,7 @@ SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) { if (SU->NodeNum == TopIdx++) ++NumInstrsInSourceOrderPostRA; } else { + assert(BotIdx < NumRegionInstrs && "out of bounds"); if (SU->NodeNum == BotIdx--) ++NumInstrsInSourceOrderPostRA; } From 55de55ec2fe835216db8f678acb6cfc698cea457 Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Tue, 6 May 2025 13:40:47 +0000 Subject: [PATCH 3/3] Add missing initialization to PostGenericScheduler Picked up by assert firing on precommit --- llvm/lib/CodeGen/MachineScheduler.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 49d44b71aee5c..b8a7eb6b4068b 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -4127,6 +4127,9 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin, RegionPolicy.OnlyBottomUp = false; RegionPolicy.OnlyTopDown = false; } + + BotIdx = NumRegionInstrs - 1; + this->NumRegionInstrs = NumRegionInstrs; } void PostGenericScheduler::registerRoots() {