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[MISched] Add statistics to quantify scheduling #138090

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Merged
merged 3 commits into from
May 7, 2025
Merged

[MISched] Add statistics to quantify scheduling #138090

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bd71a9d
[MISched] Add statistics to quantify scheduling
c-rhodes Apr 29, 2025
efd40ca
address comments
c-rhodes May 2, 2025
55de55e
Add missing initialization to PostGenericScheduler
c-rhodes May 6, 2025
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3 changes: 3 additions & 0 deletions llvm/include/llvm/CodeGen/MachineScheduler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1196,6 +1196,9 @@ class GenericSchedulerBase : public MachineSchedStrategy {
const MachineSchedContext *Context;
const TargetSchedModel *SchedModel = nullptr;
const TargetRegisterInfo *TRI = nullptr;
unsigned TopIdx = 0;
unsigned BotIdx = 0;
unsigned NumRegionInstrs = 0;

MachineSchedPolicy RegionPolicy;

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38 changes: 38 additions & 0 deletions llvm/lib/CodeGen/MachineScheduler.cpp
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Expand Up @@ -74,6 +74,14 @@ using namespace llvm;

#define DEBUG_TYPE "machine-scheduler"

STATISTIC(NumInstrsInSourceOrderPreRA,
"Number of instructions in source order after pre-RA scheduling");
STATISTIC(NumInstrsInSourceOrderPostRA,
"Number of instructions in source order after post-RA scheduling");
STATISTIC(NumInstrsScheduledPreRA,
"Number of instructions scheduled by pre-RA scheduler");
STATISTIC(NumInstrsScheduledPostRA,
"Number of instructions scheduled by post-RA scheduler");
STATISTIC(NumClustered, "Number of load/store pairs clustered");

namespace llvm {
Expand Down Expand Up @@ -3505,6 +3513,9 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = false;
RegionPolicy.OnlyTopDown = false;
}

BotIdx = NumRegionInstrs - 1;
this->NumRegionInstrs = NumRegionInstrs;
}

void GenericScheduler::dumpPolicy() const {
Expand Down Expand Up @@ -3981,6 +3992,18 @@ SUnit *GenericScheduler::pickNode(bool &IsTopNode) {

LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
<< *SU->getInstr());

if (IsTopNode) {
if (SU->NodeNum == TopIdx++)
++NumInstrsInSourceOrderPreRA;
} else {
assert(BotIdx < NumRegionInstrs && "out of bounds");
if (SU->NodeNum == BotIdx--)
++NumInstrsInSourceOrderPreRA;
}

NumInstrsScheduledPreRA += 1;

return SU;
}

Expand Down Expand Up @@ -4104,6 +4127,9 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.OnlyBottomUp = false;
RegionPolicy.OnlyTopDown = false;
}

BotIdx = NumRegionInstrs - 1;
this->NumRegionInstrs = NumRegionInstrs;
}

void PostGenericScheduler::registerRoots() {
Expand Down Expand Up @@ -4323,6 +4349,18 @@ SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {

LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
<< *SU->getInstr());

if (IsTopNode) {
if (SU->NodeNum == TopIdx++)
++NumInstrsInSourceOrderPostRA;
} else {
assert(BotIdx < NumRegionInstrs && "out of bounds");
if (SU->NodeNum == BotIdx--)
++NumInstrsInSourceOrderPostRA;
}

NumInstrsScheduledPostRA += 1;

return SU;
}

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