From e675805e927eebdb2324cc85b49b90d6441159f9 Mon Sep 17 00:00:00 2001 From: Carl Ritson Date: Thu, 1 May 2025 20:59:53 +0900 Subject: [PATCH] [MC][TableGen] Expand ImplicitOffset field of MCInstrDesc Increase width of ImplicitOffset to int from short to allow more table capacity. Reorder the elements to maintain natural alignment. --- llvm/include/llvm/MC/MCInstrDesc.h | 2 +- llvm/utils/TableGen/InstrInfoEmitter.cpp | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h index ef0b3c0a73992..5bb7f18bf2587 100644 --- a/llvm/include/llvm/MC/MCInstrDesc.h +++ b/llvm/include/llvm/MC/MCInstrDesc.h @@ -209,8 +209,8 @@ class MCInstrDesc { unsigned short SchedClass; // enum identifying instr sched class unsigned char NumImplicitUses; // Num of regs implicitly used unsigned char NumImplicitDefs; // Num of regs implicitly defined - unsigned short ImplicitOffset; // Offset to start of implicit op list unsigned short OpInfoOffset; // Offset to info about operands + unsigned int ImplicitOffset; // Offset to start of implicit op list uint64_t Flags; // Flags identifying machine instr class uint64_t TSFlags; // Target Specific Flag values diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index 377bfb593be5f..f240cab040caa 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -1106,12 +1106,14 @@ void InstrInfoEmitter::emitRecord( OS << Inst.ImplicitUses.size() << ",\t" << Inst.ImplicitDefs.size() << ",\t"; std::vector ImplicitOps = Inst.ImplicitUses; llvm::append_range(ImplicitOps, Inst.ImplicitDefs); - OS << Target.getName() << "ImpOpBase + " << EmittedLists[ImplicitOps] - << ",\t"; // Emit the operand info offset. OperandInfoTy OperandInfo = GetOperandInfo(Inst); - OS << OperandInfoMap.find(OperandInfo)->second << ",\t0"; + OS << OperandInfoMap.find(OperandInfo)->second << ",\t"; + + // Emit implicit operand base. + OS << Target.getName() << "ImpOpBase + " << EmittedLists[ImplicitOps] + << ",\t0"; // Emit all of the target independent flags... if (Inst.isPreISelOpcode)