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@koachan koachan commented May 3, 2025

From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification:

T3 SPARC core has a new 9 stage floating point pipeline and added Fused
Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to
UltraSPARC T2/T2+.

koachan added 2 commits May 3, 2025 20:50
Created using spr 1.3.5
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llvmbot commented May 3, 2025

@llvm/pr-subscribers-backend-sparc

Author: Koakuma (koachan)

Changes

From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification:
> T3 SPARC core has a new 9 stage floating point pipeline and added Fused
> Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to
> UltraSPARC T2/T2+.


Full diff: https://github.com/llvm/llvm-project/pull/138399.diff

1 Files Affected:

  • (modified) llvm/lib/Target/Sparc/Sparc.td (+1-1)
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 8b1122741b661..2083c0e763b82 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -156,7 +156,7 @@ def : Proc<"niagara",         [FeatureV9, FeatureV8Deprecated, FeatureVIS,
 def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc,
                                FeatureVIS, FeatureVIS2]>;
 def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-                               FeatureVIS, FeatureVIS2]>;
+                               FeatureVIS, FeatureVIS2, FeatureVIS3]>;
 def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
                                FeatureVIS, FeatureVIS2, FeatureVIS3]>;
 

@koachan koachan requested review from brad0, rorth and s-barannikov May 3, 2025 13:55
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LGTM

Created using spr 1.3.5
@koachan koachan changed the base branch from users/koachan/spr/main.sparc-mark-niagara3-as-vis3-capable to main May 4, 2025 02:39
@koachan koachan requested review from a team, Endilll, bcardosolopes, lanza and nikic as code owners May 4, 2025 02:39
@koachan koachan merged commit c34d2fb into main May 4, 2025
1 check was pending
@koachan koachan deleted the users/koachan/spr/sparc-mark-niagara3-as-vis3-capable branch May 4, 2025 02:39
IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025
From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification:
> T3 SPARC core has a new 9 stage floating point pipeline and added Fused
> Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to
> UltraSPARC T2/T2+.

Reviewers: rorth, s-barannikov, brad0

Reviewed By: s-barannikov

Pull Request: llvm#138399
llvm-sync bot pushed a commit to arm/arm-toolchain that referenced this pull request May 6, 2025
From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification:
> T3 SPARC core has a new 9 stage floating point pipeline and added Fused
> Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to
> UltraSPARC T2/T2+.

Reviewers: rorth, s-barannikov, brad0

Reviewed By: s-barannikov

Pull Request: llvm/llvm-project#138399
GeorgeARM pushed a commit to GeorgeARM/llvm-project that referenced this pull request May 7, 2025
From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification:
> T3 SPARC core has a new 9 stage floating point pipeline and added Fused
> Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to
> UltraSPARC T2/T2+.

Reviewers: rorth, s-barannikov, brad0

Reviewed By: s-barannikov

Pull Request: llvm#138399
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4 participants