[SPARC][IAS] Add definitions for UA 2005 instructions #138400

koachan · 2025-05-03T13:50:52Z

No description provided.

Created using spr 1.3.5

Created using spr 1.3.5 [skip ci]

llvmbot · 2025-05-03T13:51:26Z

@llvm/pr-subscribers-backend-sparc

@llvm/pr-subscribers-mc

Author: Koakuma (koachan)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/138400.diff

5 Files Affected:

(modified) llvm/lib/Target/Sparc/Sparc.td (+9-4)
(modified) llvm/lib/Target/Sparc/SparcInstrInfo.td (+5)
(added) llvm/lib/Target/Sparc/SparcInstrUAOSA.td (+21)
(added) llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt (+6)
(added) llvm/test/MC/Sparc/sparc-ua2005.s (+8)

diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 2083c0e763b82..0d66a03fd941d 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -49,6 +49,9 @@ def FeatureVIS2
 def FeatureVIS3
   : SubtargetFeature<"vis3", "IsVIS3", "true",
                      "Enable Visual Instruction Set extensions III">;
+def FeatureUA2005
+  : SubtargetFeature<"ua2005", "IsUA2005", "true",
+                     "Enable UltraSPARC Architecture 2005 extensions">;
 def FeatureLeon
   : SubtargetFeature<"leon", "IsLeon", "true",
                      "Enable LEON extensions">;
@@ -152,13 +155,15 @@ def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated, FeatureVIS,
                                FeatureVIS2],
                               [TuneSlowRDPC]>;
 def : Proc<"niagara",         [FeatureV9, FeatureV8Deprecated, FeatureVIS,
-                               FeatureVIS2]>;
+                               FeatureVIS2, FeatureUA2005]>;
 def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-                               FeatureVIS, FeatureVIS2]>;
+                               FeatureVIS, FeatureVIS2, FeatureUA2005]>;
 def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-                               FeatureVIS, FeatureVIS2, FeatureVIS3]>;
+                               FeatureVIS, FeatureVIS2, FeatureVIS3,
+                               FeatureUA2005]>;
 def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-                               FeatureVIS, FeatureVIS2, FeatureVIS3]>;
+                               FeatureVIS, FeatureVIS2, FeatureVIS3,
+                               FeatureUA2005]>;
 
 // LEON 2 FT generic
 def : Processor<"leon2", LEON2Itineraries,
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 0c890721da0f4..a220e0379213c 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -47,6 +47,10 @@ def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
              AssemblerPredicate<(all_of FeatureVIS3)>;
 
+// HasUA2005 - This is true when the target processor has UA 2005 extensions.
+def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
+                AssemblerPredicate<(all_of FeatureUA2005)>;
+
 // HasHardQuad - This is true when the target processor supports quad floating
 // point instructions.
 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
@@ -1968,4 +1972,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
 
 include "SparcInstr64Bit.td"
 include "SparcInstrVIS.td"
+include "SparcInstrUAOSA.td"
 include "SparcInstrAliases.td"
diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
new file mode 100644
index 0000000000000..d883e517db89d
--- /dev/null
+++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
@@ -0,0 +1,21 @@
+//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains instruction formats, definitions and patterns needed for
+// UA 2005 instructions on SPARC.
+//===----------------------------------------------------------------------===//
+
+// UltraSPARC Architecture 2005 Instructions
+let Predicates = [HasUA2005] in {
+let hasSideEffects = 1 in
+def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
+    let op = 2;
+    let Inst{29-19} = 0b00010110001;
+    let Inst{18-0} = 0;
+}
+} // Predicates = [HasUA2005]
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
new file mode 100644
index 0000000000000..dc3d196091c6b
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
@@ -0,0 +1,6 @@
+# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 | FileCheck %s
+
+## UA 2005 instructions.
+
+# CHECK: allclean
+0x85,0x88,0x00,0x00
diff --git a/llvm/test/MC/Sparc/sparc-ua2005.s b/llvm/test/MC/Sparc/sparc-ua2005.s
new file mode 100644
index 0000000000000..2214b91b335cd
--- /dev/null
+++ b/llvm/test/MC/Sparc/sparc-ua2005.s
@@ -0,0 +1,8 @@
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2005 --implicit-check-not=error:
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2005 -show-encoding | FileCheck %s --check-prefixes=UA2005
+
+!! UA 2005 instructions.
+
+! NO-UA2005: error: instruction requires a CPU feature not currently enabled
+! UA2005: allclean                   ! encoding: [0x85,0x88,0x00,0x00]
+allclean

s-barannikov

What about other instructions? (OTHERW, NORMALW, INVALWP)

s-barannikov · 2025-05-03T14:29:39Z

llvm/lib/Target/Sparc/SparcInstrUAOSA.td

@@ -0,0 +1,21 @@
+//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//


Copy&paste bug

s-barannikov · 2025-05-03T14:46:18Z

llvm/lib/Target/Sparc/SparcInstrUAOSA.td

+// UltraSPARC Architecture 2005 Instructions
+let Predicates = [HasUA2005] in {
+let hasSideEffects = 1 in
+def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {


Can it be put next to SAVED/RESTORED in SparcInstrInfo.td?

I prefer for these to be kept here in a separate file, especially since the other patches are adding more ISA extension instructions to this file.

Created using spr 1.3.5

koachan · 2025-05-04T01:57:34Z

What about other instructions? (OTHERW, NORMALW, INVALWP)

Added, thanks!

s-barannikov · 2025-05-04T11:35:53Z

llvm/lib/Target/Sparc/SparcInstrUAOSA.td

+// UltraSPARC Architecture 2005 Instructions
+let Predicates = [HasUA2005] in {
+let hasSideEffects = 1 in
+def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {


Sparc instructions have well-defined formats, you should rarely need to use InstSP as the base class, if ever.

0b00010110001 should be broken down into fcn=0b00010 (or decimal equivalent) and op3=0b110001. F3_1 looks the most appropriate base class of all existing classes, but it may also make sense to introduce a new class for this kind of instructions.

Yeah, it seems to be F3_1 but with anything past op3 set to zero.

s-barannikov · 2025-05-04T11:37:24Z

llvm/lib/Target/Sparc/Sparc.td

 def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-                               FeatureVIS, FeatureVIS2, FeatureVIS3]>;
+                               FeatureVIS, FeatureVIS2, FeatureVIS3,
+                               FeatureUA2005]>;


Can you point me to the documentation or other resources where I can make sure these processors support these instructions?

I usually refer to the supplement documents (T1 T2 T3 T4 are the most relevant, there also exist M5 and M7 ones if we do get around to implement optimization/ISA extension support for those processors).

Created using spr 1.3.5 [skip ci]

Created using spr 1.3.5

s-barannikov · 2025-05-11T16:19:40Z

llvm/lib/Target/Sparc/SparcInstrUAOSA.td

+    let rd = fcn;
+    let rs1 = 0;
+    let rs2 = 0;


The body is usually indented by 2 (the colon should still be indented by 4):

Suggested change

let rd = fcn;

let rs1 = 0;

let rs2 = 0;

let rd = fcn;

let rs1 = 0;

let rs2 = 0;

Created using spr 1.3.5

Reviewers: rorth, s-barannikov, brad0 Reviewed By: s-barannikov Pull Request: llvm/llvm-project#138400

koachan added 2 commits May 3, 2025 20:50

[𝘀𝗽𝗿] initial version

055fe7c

Created using spr 1.3.5

[𝘀𝗽𝗿] changes to main this commit is based on

79ab4d1

Created using spr 1.3.5 [skip ci]

llvmbot added backend:Sparc llvm:mc Machine (object) code labels May 3, 2025

koachan requested review from brad0, rorth and s-barannikov May 3, 2025 13:56

s-barannikov reviewed May 3, 2025

View reviewed changes

Add other instructions & fix typo

b2e8de5

Created using spr 1.3.5

s-barannikov reviewed May 4, 2025

View reviewed changes

koachan added 2 commits May 6, 2025 06:29

[𝘀𝗽𝗿] changes introduced through rebase

017dfac

Created using spr 1.3.5 [skip ci]

Avoid using InstSP directly

0261c9c

Created using spr 1.3.5

koachan requested a review from s-barannikov May 11, 2025 14:11

s-barannikov approved these changes May 11, 2025

View reviewed changes

Fix indentation

a2c49c5

Created using spr 1.3.5

koachan changed the base branch from users/koachan/spr/main.sparcias-add-definitions-for-ua-2005-instructions to main May 12, 2025 00:45

koachan merged commit 2e1809f into main May 12, 2025
6 of 11 checks passed

koachan deleted the users/koachan/spr/sparcias-add-definitions-for-ua-2005-instructions branch May 12, 2025 00:45

llvm-sync bot pushed a commit to arm/arm-toolchain that referenced this pull request May 12, 2025

Automerge: [SPARC][IAS] Add definitions for UA 2005 instructions

ee1f09a

Reviewers: rorth, s-barannikov, brad0 Reviewed By: s-barannikov Pull Request: llvm/llvm-project#138400

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		@@ -0,0 +1,21 @@
		//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//

[SPARC][IAS] Add definitions for UA 2005 instructions #138400

[SPARC][IAS] Add definitions for UA 2005 instructions #138400

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