From 79ab4d11c736bdb1cfcdb33f64a2a9b741ecc678 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sat, 3 May 2025 20:50:30 +0700 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?= =?UTF-8?q?anges=20to=20main=20this=20commit=20is=20based=20on?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.5 [skip ci] --- llvm/lib/Target/Sparc/Sparc.td | 2 +- llvm/lib/Target/Sparc/SparcInstr64Bit.td | 30 +++------------------- llvm/lib/Target/Sparc/SparcInstrInfo.td | 32 ++++++++++++------------ 3 files changed, 20 insertions(+), 44 deletions(-) diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index 8b1122741b661..2083c0e763b82 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -156,7 +156,7 @@ def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2]>; def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2]>; + FeatureVIS, FeatureVIS2, FeatureVIS3]>; def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, FeatureVIS, FeatureVIS2, FeatureVIS3]>; diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td index 372ab80a3bb71..5dc19144bebe9 100644 --- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -180,37 +180,13 @@ def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>; //===----------------------------------------------------------------------===// let Predicates = [Is64Bit] in { - -def MULXrr : F3_1<2, 0b001001, - (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), - "mulx $rs1, $rs2, $rd", - [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; -def MULXri : F3_2<2, 0b001001, - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), - "mulx $rs1, $simm13, $rd", - [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; +defm MULX : F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>; // Division can trap. let hasSideEffects = 1 in { -def SDIVXrr : F3_1<2, 0b101101, - (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), - "sdivx $rs1, $rs2, $rd", - [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; -def SDIVXri : F3_2<2, 0b101101, - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), - "sdivx $rs1, $simm13, $rd", - [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>; - -def UDIVXrr : F3_1<2, 0b001101, - (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), - "udivx $rs1, $rs2, $rd", - [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; -def UDIVXri : F3_2<2, 0b001101, - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), - "udivx $rs1, $simm13, $rd", - [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>; +defm SDIVX : F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>; +defm UDIVX : F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>; } // hasSideEffects = 1 - } // Predicates = [Is64Bit] diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 02f4b202e9645..0c890721da0f4 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -467,22 +467,6 @@ multiclass LoadA Op3Val, bits<6> LoadAOp3Val, defm A : LoadASI; } - -// The LDSTUB instruction is supported for asm only. -// It is unlikely that general-purpose code could make use of it. -// CAS is preferred for sparc v9. -def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr), - "ldstub [$addr], $rd", []>; -def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr), - "ldstub [$addr], $rd", []>; -def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd), - (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi), - "ldstuba [$addr] $asi, $rd", []>; -let Predicates = [HasV9], Uses = [ASR3] in -def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd), - (ins (MEMri $rs1, $simm13):$addr), - "ldstuba [$addr] %asi, $rd", []>; - // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. multiclass Store Op3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> { @@ -740,6 +724,22 @@ let rd = 1, mayStore = 1, Uses = [FSR] in { "stx %fsr, [$addr]", []>, Requires<[HasV9]>; } +// B.7. Atomic Load-Store Unsigned Byte Instructions +// (Atomic test-and-set) +// TODO look into the possibility to use this to implment `atomic_flag`. +// If it's possible, then LDSTUB is the preferred way to do it. +def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr), + "ldstub [$addr], $rd", []>; +def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr), + "ldstub [$addr], $rd", []>; +def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd), + (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi), + "ldstuba [$addr] $asi, $rd", []>; +let Predicates = [HasV9], Uses = [ASR3] in +def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd), + (ins (MEMri $rs1, $simm13):$addr), + "ldstuba [$addr] %asi, $rd", []>; + // Section B.8 - SWAP Register with Memory Instruction // (Atomic swap) let Constraints = "$val = $rd" in { From b2e8de55ea9e54239a017eb932f7107f29f465a4 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sun, 4 May 2025 08:57:07 +0700 Subject: [PATCH 2/3] Add other instructions & fix typo Created using spr 1.3.5 --- llvm/lib/Target/Sparc/SparcInstrUAOSA.td | 17 ++++++++++++++++- .../test/MC/Disassembler/Sparc/sparc-ua-osa.txt | 6 ++++++ llvm/test/MC/Sparc/sparc-ua2005.s | 9 +++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td index d883e517db89d..5ecc02ed10bfb 100644 --- a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td +++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td @@ -1,4 +1,4 @@ -//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===// +//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions ===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -18,4 +18,19 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> { let Inst{29-19} = 0b00010110001; let Inst{18-0} = 0; } +def INVALW : InstSP<(outs), (ins), "invalw", []> { + let op = 2; + let Inst{29-19} = 0b00101110001; + let Inst{18-0} = 0; +} +def NORMALW : InstSP<(outs), (ins), "normalw", []> { + let op = 2; + let Inst{29-19} = 0b00100110001; + let Inst{18-0} = 0; +} +def OTHERW : InstSP<(outs), (ins), "otherw", []> { + let op = 2; + let Inst{29-19} = 0b00011110001; + let Inst{18-0} = 0; +} } // Predicates = [HasUA2005] diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt index dc3d196091c6b..4a2de98e03fe3 100644 --- a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt +++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt @@ -4,3 +4,9 @@ # CHECK: allclean 0x85,0x88,0x00,0x00 +# CHECK: invalw +0x8b,0x88,0x00,0x00 +# CHECK: otherw +0x87,0x88,0x00,0x00 +# CHECK: normalw +0x89,0x88,0x00,0x00 diff --git a/llvm/test/MC/Sparc/sparc-ua2005.s b/llvm/test/MC/Sparc/sparc-ua2005.s index 2214b91b335cd..b07c99a20033b 100644 --- a/llvm/test/MC/Sparc/sparc-ua2005.s +++ b/llvm/test/MC/Sparc/sparc-ua2005.s @@ -6,3 +6,12 @@ ! NO-UA2005: error: instruction requires a CPU feature not currently enabled ! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00] allclean +! NO-UA2005: error: instruction requires a CPU feature not currently enabled +! UA2005: invalw ! encoding: [0x8b,0x88,0x00,0x00] +invalw +! NO-UA2005: error: instruction requires a CPU feature not currently enabled +! UA2005: otherw ! encoding: [0x87,0x88,0x00,0x00] +otherw +! NO-UA2005: error: instruction requires a CPU feature not currently enabled +! UA2005: normalw ! encoding: [0x89,0x88,0x00,0x00] +normalw From a2c49c5b9ecf2451a20d660cdc059c3301a8b816 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Mon, 12 May 2025 07:26:35 +0700 Subject: [PATCH 3/3] Fix indentation Created using spr 1.3.5 --- llvm/lib/Target/Sparc/SparcInstrUAOSA.td | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td index 8a833636301d0..b00995a960968 100644 --- a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td +++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td @@ -12,9 +12,9 @@ class UA2005RegWin fcn> : F3_1<2, 0b110001, (outs), (ins), asmstr, []> { - let rd = fcn; - let rs1 = 0; - let rs2 = 0; + let rd = fcn; + let rs1 = 0; + let rs2 = 0; } // UltraSPARC Architecture 2005 Instructions