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[SPARC][IAS] Add definitions for UA 2005 instructions #138400

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Merged
merged 6 commits into from
May 12, 2025
Merged

[SPARC][IAS] Add definitions for UA 2005 instructions #138400

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055fe7c
[𝘀𝗽𝗿] initial version
koachan May 3, 2025
79ab4d1
[𝘀𝗽𝗿] changes to main this commit is based on
koachan May 3, 2025
b2e8de5
Add other instructions & fix typo
koachan May 4, 2025
017dfac
[𝘀𝗽𝗿] changes introduced through rebase
koachan May 5, 2025
0261c9c
Avoid using InstSP directly
koachan May 5, 2025
a2c49c5
Fix indentation
koachan May 12, 2025
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13 changes: 9 additions & 4 deletions llvm/lib/Target/Sparc/Sparc.td
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Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,9 @@ def FeatureVIS2
def FeatureVIS3
: SubtargetFeature<"vis3", "IsVIS3", "true",
"Enable Visual Instruction Set extensions III">;
def FeatureUA2005
: SubtargetFeature<"ua2005", "IsUA2005", "true",
"Enable UltraSPARC Architecture 2005 extensions">;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
Expand Down Expand Up @@ -152,13 +155,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2],
[TuneSlowRDPC]>;
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2]>;
FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2]>;
FeatureVIS, FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3]>;
FeatureVIS, FeatureVIS2, FeatureVIS3,
FeatureUA2005]>;
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3]>;
FeatureVIS, FeatureVIS2, FeatureVIS3,
FeatureUA2005]>;
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@s-barannikov s-barannikov May 4, 2025

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Can you point me to the documentation or other resources where I can make sure these processors support these instructions?

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@koachan koachan May 4, 2025

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I usually refer to the supplement documents (T1 T2 T3 T4 are the most relevant, there also exist M5 and M7 ones if we do get around to implement optimization/ISA extension support for those processors).


// LEON 2 FT generic
def : Processor<"leon2", LEON2Itineraries,
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/Sparc/SparcInstrInfo.td
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Expand Up @@ -47,6 +47,10 @@ def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
AssemblerPredicate<(all_of FeatureVIS3)>;

// HasUA2005 - This is true when the target processor has UA 2005 extensions.
def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
AssemblerPredicate<(all_of FeatureUA2005)>;

// HasHardQuad - This is true when the target processor supports quad floating
// point instructions.
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
Expand Down Expand Up @@ -1968,4 +1972,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),

include "SparcInstr64Bit.td"
include "SparcInstrVIS.td"
include "SparcInstrUAOSA.td"
include "SparcInstrAliases.td"
28 changes: 28 additions & 0 deletions llvm/lib/Target/Sparc/SparcInstrUAOSA.td
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@@ -0,0 +1,28 @@
//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions ===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains instruction formats, definitions and patterns needed for
// UA 2005 instructions on SPARC.
//===----------------------------------------------------------------------===//

class UA2005RegWin<string asmstr, bits<5> fcn>
: F3_1<2, 0b110001, (outs), (ins), asmstr, []> {
let rd = fcn;
let rs1 = 0;
let rs2 = 0;
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@s-barannikov s-barannikov May 11, 2025

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The body is usually indented by 2 (the colon should still be indented by 4):

Suggested change
let rd = fcn;
let rs1 = 0;
let rs2 = 0;
let rd = fcn;
let rs1 = 0;
let rs2 = 0;

}

// UltraSPARC Architecture 2005 Instructions
let Predicates = [HasUA2005] in {
let hasSideEffects = 1 in {
def ALLCLEAN : UA2005RegWin<"allclean", 0b00010>;
def INVALW : UA2005RegWin<"invalw", 0b00101>;
def NORMALW : UA2005RegWin<"normalw", 0b00100>;
def OTHERW : UA2005RegWin<"otherw", 0b00011>;
}
} // Predicates = [HasUA2005]
12 changes: 12 additions & 0 deletions llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
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@@ -0,0 +1,12 @@
# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 | FileCheck %s

## UA 2005 instructions.

# CHECK: allclean
0x85,0x88,0x00,0x00
# CHECK: invalw
0x8b,0x88,0x00,0x00
# CHECK: otherw
0x87,0x88,0x00,0x00
# CHECK: normalw
0x89,0x88,0x00,0x00
17 changes: 17 additions & 0 deletions llvm/test/MC/Sparc/sparc-ua2005.s
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! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2005 --implicit-check-not=error:
! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2005 -show-encoding | FileCheck %s --check-prefixes=UA2005

!! UA 2005 instructions.

! NO-UA2005: error: instruction requires a CPU feature not currently enabled
! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00]
allclean
! NO-UA2005: error: instruction requires a CPU feature not currently enabled
! UA2005: invalw ! encoding: [0x8b,0x88,0x00,0x00]
invalw
! NO-UA2005: error: instruction requires a CPU feature not currently enabled
! UA2005: otherw ! encoding: [0x87,0x88,0x00,0x00]
otherw
! NO-UA2005: error: instruction requires a CPU feature not currently enabled
! UA2005: normalw ! encoding: [0x89,0x88,0x00,0x00]
normalw
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