From e6015270da12dbc8f870d172e3b55e9d07673c84 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sat, 3 May 2025 20:50:53 +0700 Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change?= =?UTF-8?q?s=20to=20main=20this=20commit=20is=20based=20on?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.5 [skip ci] --- llvm/lib/Target/Sparc/Sparc.td | 13 +++++-- llvm/lib/Target/Sparc/SparcInstr64Bit.td | 30 ++------------- llvm/lib/Target/Sparc/SparcInstrInfo.td | 37 +++++++++++-------- llvm/lib/Target/Sparc/SparcInstrUAOSA.td | 21 +++++++++++ .../MC/Disassembler/Sparc/sparc-ua-osa.txt | 6 +++ llvm/test/MC/Sparc/sparc-ua2005.s | 8 ++++ 6 files changed, 68 insertions(+), 47 deletions(-) create mode 100644 llvm/lib/Target/Sparc/SparcInstrUAOSA.td create mode 100644 llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt create mode 100644 llvm/test/MC/Sparc/sparc-ua2005.s diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index 8b1122741b661..0d66a03fd941d 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -49,6 +49,9 @@ def FeatureVIS2 def FeatureVIS3 : SubtargetFeature<"vis3", "IsVIS3", "true", "Enable Visual Instruction Set extensions III">; +def FeatureUA2005 + : SubtargetFeature<"ua2005", "IsUA2005", "true", + "Enable UltraSPARC Architecture 2005 extensions">; def FeatureLeon : SubtargetFeature<"leon", "IsLeon", "true", "Enable LEON extensions">; @@ -152,13 +155,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, FeatureVIS2], [TuneSlowRDPC]>; def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, - FeatureVIS2]>; + FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2]>; + FeatureVIS, FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005]>; def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2, FeatureVIS3]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005]>; // LEON 2 FT generic def : Processor<"leon2", LEON2Itineraries, diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td index 372ab80a3bb71..5dc19144bebe9 100644 --- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -180,37 +180,13 @@ def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>; //===----------------------------------------------------------------------===// let Predicates = [Is64Bit] in { - -def MULXrr : F3_1<2, 0b001001, - (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), - "mulx $rs1, $rs2, $rd", - [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; -def MULXri : F3_2<2, 0b001001, - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), - "mulx $rs1, $simm13, $rd", - [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; +defm MULX : F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>; // Division can trap. let hasSideEffects = 1 in { -def SDIVXrr : F3_1<2, 0b101101, - (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), - "sdivx $rs1, $rs2, $rd", - [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; -def SDIVXri : F3_2<2, 0b101101, - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), - "sdivx $rs1, $simm13, $rd", - [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>; - -def UDIVXrr : F3_1<2, 0b001101, - (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), - "udivx $rs1, $rs2, $rd", - [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; -def UDIVXri : F3_2<2, 0b001101, - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), - "udivx $rs1, $simm13, $rd", - [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>; +defm SDIVX : F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>; +defm UDIVX : F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>; } // hasSideEffects = 1 - } // Predicates = [Is64Bit] diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 02f4b202e9645..a220e0379213c 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -47,6 +47,10 @@ def HasVIS2 : Predicate<"Subtarget->isVIS2()">, def HasVIS3 : Predicate<"Subtarget->isVIS3()">, AssemblerPredicate<(all_of FeatureVIS3)>; +// HasUA2005 - This is true when the target processor has UA 2005 extensions. +def HasUA2005 : Predicate<"Subtarget->isUA2005()">, + AssemblerPredicate<(all_of FeatureUA2005)>; + // HasHardQuad - This is true when the target processor supports quad floating // point instructions. def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; @@ -467,22 +471,6 @@ multiclass LoadA Op3Val, bits<6> LoadAOp3Val, defm A : LoadASI; } - -// The LDSTUB instruction is supported for asm only. -// It is unlikely that general-purpose code could make use of it. -// CAS is preferred for sparc v9. -def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr), - "ldstub [$addr], $rd", []>; -def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr), - "ldstub [$addr], $rd", []>; -def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd), - (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi), - "ldstuba [$addr] $asi, $rd", []>; -let Predicates = [HasV9], Uses = [ASR3] in -def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd), - (ins (MEMri $rs1, $simm13):$addr), - "ldstuba [$addr] %asi, $rd", []>; - // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. multiclass Store Op3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> { @@ -740,6 +728,22 @@ let rd = 1, mayStore = 1, Uses = [FSR] in { "stx %fsr, [$addr]", []>, Requires<[HasV9]>; } +// B.7. Atomic Load-Store Unsigned Byte Instructions +// (Atomic test-and-set) +// TODO look into the possibility to use this to implment `atomic_flag`. +// If it's possible, then LDSTUB is the preferred way to do it. +def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr), + "ldstub [$addr], $rd", []>; +def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr), + "ldstub [$addr], $rd", []>; +def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd), + (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi), + "ldstuba [$addr] $asi, $rd", []>; +let Predicates = [HasV9], Uses = [ASR3] in +def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd), + (ins (MEMri $rs1, $simm13):$addr), + "ldstuba [$addr] %asi, $rd", []>; + // Section B.8 - SWAP Register with Memory Instruction // (Atomic swap) let Constraints = "$val = $rd" in { @@ -1968,4 +1972,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)), include "SparcInstr64Bit.td" include "SparcInstrVIS.td" +include "SparcInstrUAOSA.td" include "SparcInstrAliases.td" diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td new file mode 100644 index 0000000000000..d883e517db89d --- /dev/null +++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td @@ -0,0 +1,21 @@ +//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains instruction formats, definitions and patterns needed for +// UA 2005 instructions on SPARC. +//===----------------------------------------------------------------------===// + +// UltraSPARC Architecture 2005 Instructions +let Predicates = [HasUA2005] in { +let hasSideEffects = 1 in +def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> { + let op = 2; + let Inst{29-19} = 0b00010110001; + let Inst{18-0} = 0; +} +} // Predicates = [HasUA2005] diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt new file mode 100644 index 0000000000000..dc3d196091c6b --- /dev/null +++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 | FileCheck %s + +## UA 2005 instructions. + +# CHECK: allclean +0x85,0x88,0x00,0x00 diff --git a/llvm/test/MC/Sparc/sparc-ua2005.s b/llvm/test/MC/Sparc/sparc-ua2005.s new file mode 100644 index 0000000000000..2214b91b335cd --- /dev/null +++ b/llvm/test/MC/Sparc/sparc-ua2005.s @@ -0,0 +1,8 @@ +! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2005 --implicit-check-not=error: +! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2005 -show-encoding | FileCheck %s --check-prefixes=UA2005 + +!! UA 2005 instructions. + +! NO-UA2005: error: instruction requires a CPU feature not currently enabled +! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00] +allclean