From 8e75442d3bfadbc204965c9db15bea5b50ad0b0c Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sat, 3 May 2025 20:51:29 +0700 Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?= =?UTF-8?q?anges=20to=20main=20this=20commit=20is=20based=20on?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.5 [skip ci] --- .../Sparc/MCTargetDesc/SparcInstPrinter.cpp | 4 +- llvm/lib/Target/Sparc/Sparc.td | 16 +++++-- llvm/lib/Target/Sparc/SparcInstr64Bit.td | 30 ++----------- llvm/lib/Target/Sparc/SparcInstrAliases.td | 4 +- llvm/lib/Target/Sparc/SparcInstrFormats.td | 17 +++++++ llvm/lib/Target/Sparc/SparcInstrInfo.td | 45 +++++++++++-------- llvm/lib/Target/Sparc/SparcInstrUAOSA.td | 40 +++++++++++++++++ .../MC/Disassembler/Sparc/sparc-ua-osa.txt | 25 +++++++++++ llvm/test/MC/Sparc/sparc-ua2005.s | 8 ++++ llvm/test/MC/Sparc/sparc-ua2007.s | 30 +++++++++++++ 10 files changed, 166 insertions(+), 53 deletions(-) create mode 100644 llvm/lib/Target/Sparc/SparcInstrUAOSA.td create mode 100644 llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt create mode 100644 llvm/test/MC/Sparc/sparc-ua2005.s create mode 100644 llvm/test/MC/Sparc/sparc-ua2007.s diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp index f2a61c95fefb5..42f3b9d3c4ce9 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp @@ -192,8 +192,8 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum, // Make sure CC is a fp conditional flag. CC = (CC < SPCC::FCC_BEGIN) ? (CC + SPCC::FCC_BEGIN) : CC; break; - case SP::CBCOND: - case SP::CBCONDA: + case SP::CPBCOND: + case SP::CPBCONDA: // Make sure CC is a cp conditional flag. CC = (CC < SPCC::CPCC_BEGIN) ? (CC + SPCC::CPCC_BEGIN) : CC; break; diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index 8b1122741b661..93c3098bd89fe 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -49,6 +49,12 @@ def FeatureVIS2 def FeatureVIS3 : SubtargetFeature<"vis3", "IsVIS3", "true", "Enable Visual Instruction Set extensions III">; +def FeatureUA2005 + : SubtargetFeature<"ua2005", "IsUA2005", "true", + "Enable UltraSPARC Architecture 2005 extensions">; +def FeatureUA2007 + : SubtargetFeature<"ua2007", "IsUA2007", "true", + "Enable UltraSPARC Architecture 2007 extensions">; def FeatureLeon : SubtargetFeature<"leon", "IsLeon", "true", "Enable LEON extensions">; @@ -152,13 +158,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, FeatureVIS2], [TuneSlowRDPC]>; def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, - FeatureVIS2]>; + FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2]>; + FeatureVIS, FeatureVIS2, FeatureUA2005]>; def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005, FeatureUA2007]>; def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, - FeatureVIS, FeatureVIS2, FeatureVIS3]>; + FeatureVIS, FeatureVIS2, FeatureVIS3, + FeatureUA2005, FeatureUA2007]>; // LEON 2 FT generic def : Processor<"leon2", LEON2Itineraries, diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td index 372ab80a3bb71..5dc19144bebe9 100644 --- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -180,37 +180,13 @@ def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>; //===----------------------------------------------------------------------===// let Predicates = [Is64Bit] in { - -def MULXrr : F3_1<2, 0b001001, - (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), - "mulx $rs1, $rs2, $rd", - [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; -def MULXri : F3_2<2, 0b001001, - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), - "mulx $rs1, $simm13, $rd", - [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; +defm MULX : F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>; // Division can trap. let hasSideEffects = 1 in { -def SDIVXrr : F3_1<2, 0b101101, - (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), - "sdivx $rs1, $rs2, $rd", - [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; -def SDIVXri : F3_2<2, 0b101101, - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), - "sdivx $rs1, $simm13, $rd", - [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>; - -def UDIVXrr : F3_1<2, 0b001101, - (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), - "udivx $rs1, $rs2, $rd", - [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; -def UDIVXri : F3_2<2, 0b001101, - (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), - "udivx $rs1, $simm13, $rd", - [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>; +defm SDIVX : F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>; +defm UDIVX : F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>; } // hasSideEffects = 1 - } // Predicates = [Is64Bit] diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td index bc57ddbb5682f..590395c16965b 100644 --- a/llvm/lib/Target/Sparc/SparcInstrAliases.td +++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td @@ -286,11 +286,11 @@ multiclass cp_cond_alias { // cb $imm def : InstAlias; + (CPBCOND brtarget:$imm, condVal), 0>; // cb,a $imm def : InstAlias; + (CPBCONDA brtarget:$imm, condVal), 0>; } // Instruction aliases for register conditional branches and moves. diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td index 4ff902b190a3b..2998f53ef2dbc 100644 --- a/llvm/lib/Target/Sparc/SparcInstrFormats.td +++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td @@ -260,6 +260,23 @@ multiclass F3_S Op3Val, bit XVal, SDNode OpNode, itin>; } +// 4-operand instructions. +class F3_4 op3val, bits<4> op5val, dag outs, dag ins, + string asmstr, list pattern = [], InstrItinClass itin = NoItinerary> + : F3 { + bits<4> op5; + bits<5> rs3; + bits<5> rs2; + + let op = 2; + let op3 = op3val; + let op5 = op5val; + + let Inst{13-9} = rs3; + let Inst{8-5} = op5; + let Inst{4-0} = rs2; +} + class F4 op3, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin = NoItinerary> : InstSP { diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 02f4b202e9645..057eafd734e71 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -47,6 +47,14 @@ def HasVIS2 : Predicate<"Subtarget->isVIS2()">, def HasVIS3 : Predicate<"Subtarget->isVIS3()">, AssemblerPredicate<(all_of FeatureVIS3)>; +// HasUA2005 - This is true when the target processor has UA 2005 extensions. +def HasUA2005 : Predicate<"Subtarget->isUA2005()">, + AssemblerPredicate<(all_of FeatureUA2005)>; + +// HasUA2007 - This is true when the target processor has UA 2007 extensions. +def HasUA2007 : Predicate<"Subtarget->isUA2007()">, + AssemblerPredicate<(all_of FeatureUA2007)>; + // HasHardQuad - This is true when the target processor supports quad floating // point instructions. def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; @@ -467,22 +475,6 @@ multiclass LoadA Op3Val, bits<6> LoadAOp3Val, defm A : LoadASI; } - -// The LDSTUB instruction is supported for asm only. -// It is unlikely that general-purpose code could make use of it. -// CAS is preferred for sparc v9. -def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr), - "ldstub [$addr], $rd", []>; -def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr), - "ldstub [$addr], $rd", []>; -def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd), - (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi), - "ldstuba [$addr] $asi, $rd", []>; -let Predicates = [HasV9], Uses = [ASR3] in -def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd), - (ins (MEMri $rs1, $simm13):$addr), - "ldstuba [$addr] %asi, $rd", []>; - // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. multiclass Store Op3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> { @@ -740,6 +732,22 @@ let rd = 1, mayStore = 1, Uses = [FSR] in { "stx %fsr, [$addr]", []>, Requires<[HasV9]>; } +// B.7. Atomic Load-Store Unsigned Byte Instructions +// (Atomic test-and-set) +// TODO look into the possibility to use this to implment `atomic_flag`. +// If it's possible, then LDSTUB is the preferred way to do it. +def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr), + "ldstub [$addr], $rd", []>; +def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr), + "ldstub [$addr], $rd", []>; +def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd), + (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi), + "ldstuba [$addr] $asi, $rd", []>; +let Predicates = [HasV9], Uses = [ASR3] in +def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd), + (ins (MEMri $rs1, $simm13):$addr), + "ldstuba [$addr] %asi, $rd", []>; + // Section B.8 - SWAP Register with Memory Instruction // (Atomic swap) let Constraints = "$val = $rd" in { @@ -1020,10 +1028,10 @@ class CPBranchSPA pattern> } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 -def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond), +def CPBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond), "cb$cond $imm22", [(SPbrfcc bb:$imm22, imm:$cond)]>; -def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), +def CPBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), "cb$cond,a $imm22", []>; // Section B.24 - Call and Link Instruction, p. 125 @@ -1968,4 +1976,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)), include "SparcInstr64Bit.td" include "SparcInstrVIS.td" +include "SparcInstrUAOSA.td" include "SparcInstrAliases.td" diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td new file mode 100644 index 0000000000000..a1bfcc3dbb652 --- /dev/null +++ b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td @@ -0,0 +1,40 @@ +//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains instruction formats, definitions and patterns needed for +// UA 2005 and UA 2007 instructions on SPARC. +//===----------------------------------------------------------------------===// + +// Convenience template for 4-operand instructions +class FourOp op3val, bits<4> op5val, + RegisterClass RC> + : F3_4; + +// UltraSPARC Architecture 2005 Instructions +let Predicates = [HasUA2005] in { +let hasSideEffects = 1 in +def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> { + let op = 2; + let Inst{29-19} = 0b00010110001; + let Inst{18-0} = 0; +} +} // Predicates = [HasUA2005] + +// UltraSPARC Architecture 2007 Instructions +let Predicates = [HasUA2007] in { +def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>; +def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>; +def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>; +def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>; + +def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>; +def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>; +def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>; +def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>; +} // Predicates = [HasUA2007] diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt new file mode 100644 index 0000000000000..b6a48ab56c9d9 --- /dev/null +++ b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt @@ -0,0 +1,25 @@ +# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005,+ua2007 | FileCheck %s + +## UA 2005 instructions. + +# CHECK: allclean +0x85,0x88,0x00,0x00 + +## UA 2007 instructions. + +# CHECK: fmadds %f1, %f3, %f5, %f7 +0x8f,0xb8,0x4a,0x23 +# CHECK: fmaddd %f0, %f2, %f4, %f6 +0x8d,0xb8,0x08,0x42 +# CHECK: fmsubs %f1, %f3, %f5, %f7 +0x8f,0xb8,0x4a,0xa3 +# CHECK: fmsubd %f0, %f2, %f4, %f6 +0x8d,0xb8,0x08,0xc2 +# CHECK: fnmadds %f1, %f3, %f5, %f7 +0x8f,0xb8,0x4b,0xa3 +# CHECK: fnmaddd %f0, %f2, %f4, %f6 +0x8d,0xb8,0x09,0xc2 +# CHECK: fnmsubs %f1, %f3, %f5, %f7 +0x8f,0xb8,0x4b,0x23 +# CHECK: fnmsubd %f0, %f2, %f4, %f6 +0x8d,0xb8,0x09,0x42 diff --git a/llvm/test/MC/Sparc/sparc-ua2005.s b/llvm/test/MC/Sparc/sparc-ua2005.s new file mode 100644 index 0000000000000..2214b91b335cd --- /dev/null +++ b/llvm/test/MC/Sparc/sparc-ua2005.s @@ -0,0 +1,8 @@ +! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2005 --implicit-check-not=error: +! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2005 -show-encoding | FileCheck %s --check-prefixes=UA2005 + +!! UA 2005 instructions. + +! NO-UA2005: error: instruction requires a CPU feature not currently enabled +! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00] +allclean diff --git a/llvm/test/MC/Sparc/sparc-ua2007.s b/llvm/test/MC/Sparc/sparc-ua2007.s new file mode 100644 index 0000000000000..6b41f929a75da --- /dev/null +++ b/llvm/test/MC/Sparc/sparc-ua2007.s @@ -0,0 +1,30 @@ +! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2007 --implicit-check-not=error: +! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2007 -show-encoding | FileCheck %s --check-prefixes=UA2007 + +!! UA 2007 instructions. + +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fmadds %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4a,0x23] +fmadds %f1, %f3, %f5, %f7 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fmaddd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0x42] +fmaddd %f0, %f2, %f4, %f6 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fmsubs %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4a,0xa3] +fmsubs %f1, %f3, %f5, %f7 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fmsubd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0xc2] +fmsubd %f0, %f2, %f4, %f6 + +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fnmadds %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4b,0xa3] +fnmadds %f1, %f3, %f5, %f7 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fnmaddd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x09,0xc2] +fnmaddd %f0, %f2, %f4, %f6 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fnmsubs %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4b,0x23] +fnmsubs %f1, %f3, %f5, %f7 +! NO-UA2007: error: instruction requires a CPU feature not currently enabled +! UA2007: fnmsubd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x09,0x42] +fnmsubd %f0, %f2, %f4, %f6 From 5b59eb6176ee2790e7b31e99ae7f7769bf630b1a Mon Sep 17 00:00:00 2001 From: Koakuma Date: Thu, 29 May 2025 11:04:46 +0700 Subject: [PATCH 2/2] Apply feedback Created using spr 1.3.5 --- .../Sparc/MCTargetDesc/SparcAsmBackend.cpp | 6 + .../Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp | 9 +- llvm/lib/Target/Sparc/SparcInstrAliases.td | 18 +- llvm/lib/Target/Sparc/SparcInstrFormats.td | 4 +- llvm/test/MC/Sparc/Relocations/expr.s | 16 +- llvm/test/MC/Sparc/sparc64-branch-offset.s | 508 +++++++++--------- 6 files changed, 289 insertions(+), 272 deletions(-) diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index c74f24d95523e..743752ad2c107 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -51,6 +51,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { } case ELF::R_SPARC_WDISP10: { + // FIXME this really should be an error reporting check. + assert((Value & 0x3) == 0); + // 7.17 Compare and Branch // Inst{20-19} = d10hi; // Inst{12-5} = d10lo; @@ -70,6 +73,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { case Sparc::fixup_sparc_13: return Value & 0x1fff; + case ELF::R_SPARC_5: + return Value & 0x1f; + case ELF::R_SPARC_LOX10: return (Value & 0x3ff) | 0x1c00; diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp index b44d4361dacdb..2c8dbaa5aba60 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp @@ -164,7 +164,12 @@ unsigned SparcMCCodeEmitter::getSImm5OpValue(const MCInst &MI, unsigned OpNo, if (const MCConstantExpr *CE = dyn_cast(Expr)) return CE->getValue(); - llvm_unreachable("simm5 operands can only be used with constants!"); + if (const SparcMCExpr *SExpr = dyn_cast(Expr)) { + Fixups.push_back(MCFixup::create(0, Expr, SExpr->getFixupKind())); + return 0; + } + Fixups.push_back(MCFixup::create(0, Expr, ELF::R_SPARC_5)); + return 0; } unsigned @@ -247,7 +252,7 @@ unsigned SparcMCCodeEmitter::getCompareAndBranchTargetOpValue( const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) + if (MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); Fixups.push_back(MCFixup::create(0, MO.getExpr(), ELF::R_SPARC_WDISP10)); diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td index fa2c62101d30e..459fd193db0ed 100644 --- a/llvm/lib/Target/Sparc/SparcInstrAliases.td +++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td @@ -333,19 +333,19 @@ multiclass reg_cond_alias { // Instruction aliases for compare-and-branch. multiclass cwb_cond_alias { - def : InstAlias, Requires<[HasOSA2011]>; - def : InstAlias, Requires<[HasOSA2011]>; } multiclass cxb_cond_alias { - def : InstAlias, Requires<[HasOSA2011]>; - def : InstAlias, Requires<[HasOSA2011]>; } @@ -441,8 +441,7 @@ defm : cwb_cond_alias<"pos", 0b1110>; defm : cwb_cond_alias<"neg", 0b0110>; defm : cwb_cond_alias<"vc", 0b1111>; defm : cwb_cond_alias<"vs", 0b0111>; -let EmitPriority = 0 in -{ +let EmitPriority = 0 in { defm : cwb_cond_alias<"geu", 0b1101>; // same as cc defm : cwb_cond_alias<"lu", 0b0101>; // same as cs } @@ -461,8 +460,7 @@ defm : cxb_cond_alias<"pos", 0b1110>; defm : cxb_cond_alias<"neg", 0b0110>; defm : cxb_cond_alias<"vc", 0b1111>; defm : cxb_cond_alias<"vs", 0b0111>; -let EmitPriority = 0 in -{ +let EmitPriority = 0 in { defm : cxb_cond_alias<"geu", 0b1101>; // same as cc defm : cxb_cond_alias<"lu", 0b0101>; // same as cs } @@ -727,6 +725,6 @@ def : InstAlias<"sir", (SIR 0), 0>; // pause reg_or_imm -> wrasr %g0, reg_or_imm, %asr27 let Predicates = [HasOSA2011] in { -def : InstAlias<"pause $rs2", (WRASRrr ASR27, G0, IntRegs:$rs2), 1>; -def : InstAlias<"pause $simm13", (WRASRri ASR27, G0, simm13Op:$simm13), 1>; + def : InstAlias<"pause $rs2", (WRASRrr ASR27, G0, IntRegs:$rs2), 1>; + def : InstAlias<"pause $simm13", (WRASRri ASR27, G0, simm13Op:$simm13), 1>; } // Predicates = [HasOSA2011] diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td index fe10bb443348a..79c4cb2128a0f 100644 --- a/llvm/lib/Target/Sparc/SparcInstrFormats.td +++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td @@ -104,7 +104,7 @@ class F2_4 pattern = [], InstrItinClass itin = NoItinerary> - : InstSP { + : InstSP { bits<10> imm10; bits<5> rs1; bits<5> rs2; @@ -126,7 +126,7 @@ class F2_5 pattern = [], InstrItinClass itin = NoItinerary> - : InstSP { + : InstSP { bits<10> imm10; bits<5> rs1; bits<5> simm5; diff --git a/llvm/test/MC/Sparc/Relocations/expr.s b/llvm/test/MC/Sparc/Relocations/expr.s index fcde7d6a1d905..ec3a3ac699b6b 100644 --- a/llvm/test/MC/Sparc/Relocations/expr.s +++ b/llvm/test/MC/Sparc/Relocations/expr.s @@ -1,5 +1,5 @@ -! RUN: llvm-mc %s -triple=sparc | FileCheck %s -! RUN: llvm-mc %s -triple=sparc -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP +! RUN: llvm-mc %s -triple=sparc -mattr=+osa2011 | FileCheck %s +! RUN: llvm-mc %s -triple=sparc -mattr=+osa2011 -filetype=obj | llvm-objdump -r -d - | FileCheck %s --check-prefix=OBJDUMP ! CHECK: mov 1033, %o1 mov (0x400|9), %o1 @@ -12,7 +12,7 @@ symStart: b symStart + 4 ! CHECK: mov symEnd-symStart, %g1 - ! OBJDUMP: mov 0x18, %g1 + ! OBJDUMP: mov 0x20, %g1 mov symEnd - symStart, %g1 ! CHECK: sethi %hi(sym+10), %g2 @@ -30,10 +30,18 @@ symStart: ! CHECK: add %g1, 100+val, %g2 ! OBJDUMP: R_SPARC_13 val+0x64 add %g1, 100 + val, %g2 + + ! CHECK: cwbe %g0, val+2, symStart + ! OBJDUMP: R_SPARC_5 val+0x2 + cwbe %g0, val + 2, symStart + + ! CHECK: cxbe %g0, val+2, symStart + ! OBJDUMP: R_SPARC_5 val+0x2 + cxbe %g0, val + 2, symStart symEnd: ! "." is exactly like a temporary symbol equated to the current line. -! RUN: llvm-mc %s -triple=sparc | FileCheck %s --check-prefix=DOTEXPR +! RUN: llvm-mc %s -triple=sparc -mattr=+osa2011 | FileCheck %s --check-prefix=DOTEXPR ! DOTEXPR: .Ltmp0 ! DOTEXPR-NEXT: ba .Ltmp0+8 diff --git a/llvm/test/MC/Sparc/sparc64-branch-offset.s b/llvm/test/MC/Sparc/sparc64-branch-offset.s index 5341c349a14d4..c0be339bec728 100644 --- a/llvm/test/MC/Sparc/sparc64-branch-offset.s +++ b/llvm/test/MC/Sparc/sparc64-branch-offset.s @@ -1,267 +1,267 @@ ! RUN: llvm-mc -triple=sparcv9 -mattr=+osa2011 -filetype=obj %s | llvm-objdump --mattr=+osa2011 --no-print-imm-hex -d - | FileCheck %s --check-prefix=BIN - !! SPARCv9/SPARC64 BPr branches have different offset encoding from the others, - !! make sure that our offset bits don't trample on other fields. - !! This is particularly important with backwards branches. +!! SPARCv9/SPARC64 BPr branches have different offset encoding from the others, +!! make sure that our offset bits don't trample on other fields. +!! This is particularly important with backwards branches. - ! BIN: 0: 02 c8 40 01 brz %g1, 0x4 - ! BIN: 4: 04 c8 40 01 brlez %g1, 0x8 - ! BIN: 8: 06 c8 40 01 brlz %g1, 0xc - ! BIN: c: 0a c8 40 01 brnz %g1, 0x10 - ! BIN: 10: 0c c8 40 01 brgz %g1, 0x14 - ! BIN: 14: 0e c8 40 01 brgez %g1, 0x18 - brz %g1, .+4 - brlez %g1, .+4 - brlz %g1, .+4 - brnz %g1, .+4 - brgz %g1, .+4 - brgez %g1, .+4 +! BIN: 0: 02 c8 40 01 brz %g1, 0x4 +! BIN: 4: 04 c8 40 01 brlez %g1, 0x8 +! BIN: 8: 06 c8 40 01 brlz %g1, 0xc +! BIN: c: 0a c8 40 01 brnz %g1, 0x10 +! BIN: 10: 0c c8 40 01 brgz %g1, 0x14 +! BIN: 14: 0e c8 40 01 brgez %g1, 0x18 +brz %g1, .+4 +brlez %g1, .+4 +brlz %g1, .+4 +brnz %g1, .+4 +brgz %g1, .+4 +brgez %g1, .+4 - ! BIN: 18: 02 f8 7f ff brz %g1, 0x14 - ! BIN: 1c: 04 f8 7f ff brlez %g1, 0x18 - ! BIN: 20: 06 f8 7f ff brlz %g1, 0x1c - ! BIN: 24: 0a f8 7f ff brnz %g1, 0x20 - ! BIN: 28: 0c f8 7f ff brgz %g1, 0x24 - ! BIN: 2c: 0e f8 7f ff brgez %g1, 0x28 - brz %g1, .-4 - brlez %g1, .-4 - brlz %g1, .-4 - brnz %g1, .-4 - brgz %g1, .-4 - brgez %g1, .-4 +! BIN: 18: 02 f8 7f ff brz %g1, 0x14 +! BIN: 1c: 04 f8 7f ff brlez %g1, 0x18 +! BIN: 20: 06 f8 7f ff brlz %g1, 0x1c +! BIN: 24: 0a f8 7f ff brnz %g1, 0x20 +! BIN: 28: 0c f8 7f ff brgz %g1, 0x24 +! BIN: 2c: 0e f8 7f ff brgez %g1, 0x28 +brz %g1, .-4 +brlez %g1, .-4 +brlz %g1, .-4 +brnz %g1, .-4 +brgz %g1, .-4 +brgez %g1, .-4 - !! Similarly, OSA2011 CBCond branches have different offset encoding, - !! make sure that our offset bits don't trample on other fields. - !! This is particularly important with backwards branches. +!! Similarly, OSA2011 CBCond branches have different offset encoding, +!! make sure that our offset bits don't trample on other fields. +!! This is particularly important with backwards branches. - !BIN: 30: 32 c2 00 29 cwbne %o0, %o1, 0x34 - !BIN: 34: 12 c2 00 29 cwbe %o0, %o1, 0x38 - !BIN: 38: 34 c2 00 29 cwbg %o0, %o1, 0x3c - !BIN: 3c: 14 c2 00 29 cwble %o0, %o1, 0x40 - !BIN: 40: 36 c2 00 29 cwbge %o0, %o1, 0x44 - !BIN: 44: 16 c2 00 29 cwbl %o0, %o1, 0x48 - !BIN: 48: 38 c2 00 29 cwbgu %o0, %o1, 0x4c - !BIN: 4c: 18 c2 00 29 cwbleu %o0, %o1, 0x50 - !BIN: 50: 3a c2 00 29 cwbcc %o0, %o1, 0x54 - !BIN: 54: 1a c2 00 29 cwbcs %o0, %o1, 0x58 - !BIN: 58: 3c c2 00 29 cwbpos %o0, %o1, 0x5c - !BIN: 5c: 1c c2 00 29 cwbneg %o0, %o1, 0x60 - !BIN: 60: 3e c2 00 29 cwbvc %o0, %o1, 0x64 - !BIN: 64: 1e c2 00 29 cwbvs %o0, %o1, 0x68 - cwbne %o0, %o1, .+4 - cwbe %o0, %o1, .+4 - cwbg %o0, %o1, .+4 - cwble %o0, %o1, .+4 - cwbge %o0, %o1, .+4 - cwbl %o0, %o1, .+4 - cwbgu %o0, %o1, .+4 - cwbleu %o0, %o1, .+4 - cwbcc %o0, %o1, .+4 - cwbcs %o0, %o1, .+4 - cwbpos %o0, %o1, .+4 - cwbneg %o0, %o1, .+4 - cwbvc %o0, %o1, .+4 - cwbvs %o0, %o1, .+4 +!BIN: 30: 32 c2 00 29 cwbne %o0, %o1, 0x34 +!BIN: 34: 12 c2 00 29 cwbe %o0, %o1, 0x38 +!BIN: 38: 34 c2 00 29 cwbg %o0, %o1, 0x3c +!BIN: 3c: 14 c2 00 29 cwble %o0, %o1, 0x40 +!BIN: 40: 36 c2 00 29 cwbge %o0, %o1, 0x44 +!BIN: 44: 16 c2 00 29 cwbl %o0, %o1, 0x48 +!BIN: 48: 38 c2 00 29 cwbgu %o0, %o1, 0x4c +!BIN: 4c: 18 c2 00 29 cwbleu %o0, %o1, 0x50 +!BIN: 50: 3a c2 00 29 cwbcc %o0, %o1, 0x54 +!BIN: 54: 1a c2 00 29 cwbcs %o0, %o1, 0x58 +!BIN: 58: 3c c2 00 29 cwbpos %o0, %o1, 0x5c +!BIN: 5c: 1c c2 00 29 cwbneg %o0, %o1, 0x60 +!BIN: 60: 3e c2 00 29 cwbvc %o0, %o1, 0x64 +!BIN: 64: 1e c2 00 29 cwbvs %o0, %o1, 0x68 +cwbne %o0, %o1, .+4 +cwbe %o0, %o1, .+4 +cwbg %o0, %o1, .+4 +cwble %o0, %o1, .+4 +cwbge %o0, %o1, .+4 +cwbl %o0, %o1, .+4 +cwbgu %o0, %o1, .+4 +cwbleu %o0, %o1, .+4 +cwbcc %o0, %o1, .+4 +cwbcs %o0, %o1, .+4 +cwbpos %o0, %o1, .+4 +cwbneg %o0, %o1, .+4 +cwbvc %o0, %o1, .+4 +cwbvs %o0, %o1, .+4 - !BIN: 68: 32 da 1f e9 cwbne %o0, %o1, 0x64 - !BIN: 6c: 12 da 1f e9 cwbe %o0, %o1, 0x68 - !BIN: 70: 34 da 1f e9 cwbg %o0, %o1, 0x6c - !BIN: 74: 14 da 1f e9 cwble %o0, %o1, 0x70 - !BIN: 78: 36 da 1f e9 cwbge %o0, %o1, 0x74 - !BIN: 7c: 16 da 1f e9 cwbl %o0, %o1, 0x78 - !BIN: 80: 38 da 1f e9 cwbgu %o0, %o1, 0x7c - !BIN: 84: 18 da 1f e9 cwbleu %o0, %o1, 0x80 - !BIN: 88: 3a da 1f e9 cwbcc %o0, %o1, 0x84 - !BIN: 8c: 1a da 1f e9 cwbcs %o0, %o1, 0x88 - !BIN: 90: 3c da 1f e9 cwbpos %o0, %o1, 0x8c - !BIN: 94: 1c da 1f e9 cwbneg %o0, %o1, 0x90 - !BIN: 98: 3e da 1f e9 cwbvc %o0, %o1, 0x94 - !BIN: 9c: 1e da 1f e9 cwbvs %o0, %o1, 0x98 - cwbne %o0, %o1, .-4 - cwbe %o0, %o1, .-4 - cwbg %o0, %o1, .-4 - cwble %o0, %o1, .-4 - cwbge %o0, %o1, .-4 - cwbl %o0, %o1, .-4 - cwbgu %o0, %o1, .-4 - cwbleu %o0, %o1, .-4 - cwbcc %o0, %o1, .-4 - cwbcs %o0, %o1, .-4 - cwbpos %o0, %o1, .-4 - cwbneg %o0, %o1, .-4 - cwbvc %o0, %o1, .-4 - cwbvs %o0, %o1, .-4 +!BIN: 68: 32 da 1f e9 cwbne %o0, %o1, 0x64 +!BIN: 6c: 12 da 1f e9 cwbe %o0, %o1, 0x68 +!BIN: 70: 34 da 1f e9 cwbg %o0, %o1, 0x6c +!BIN: 74: 14 da 1f e9 cwble %o0, %o1, 0x70 +!BIN: 78: 36 da 1f e9 cwbge %o0, %o1, 0x74 +!BIN: 7c: 16 da 1f e9 cwbl %o0, %o1, 0x78 +!BIN: 80: 38 da 1f e9 cwbgu %o0, %o1, 0x7c +!BIN: 84: 18 da 1f e9 cwbleu %o0, %o1, 0x80 +!BIN: 88: 3a da 1f e9 cwbcc %o0, %o1, 0x84 +!BIN: 8c: 1a da 1f e9 cwbcs %o0, %o1, 0x88 +!BIN: 90: 3c da 1f e9 cwbpos %o0, %o1, 0x8c +!BIN: 94: 1c da 1f e9 cwbneg %o0, %o1, 0x90 +!BIN: 98: 3e da 1f e9 cwbvc %o0, %o1, 0x94 +!BIN: 9c: 1e da 1f e9 cwbvs %o0, %o1, 0x98 +cwbne %o0, %o1, .-4 +cwbe %o0, %o1, .-4 +cwbg %o0, %o1, .-4 +cwble %o0, %o1, .-4 +cwbge %o0, %o1, .-4 +cwbl %o0, %o1, .-4 +cwbgu %o0, %o1, .-4 +cwbleu %o0, %o1, .-4 +cwbcc %o0, %o1, .-4 +cwbcs %o0, %o1, .-4 +cwbpos %o0, %o1, .-4 +cwbneg %o0, %o1, .-4 +cwbvc %o0, %o1, .-4 +cwbvs %o0, %o1, .-4 - !BIN: a0: 32 c2 20 21 cwbne %o0, 1, 0xa4 - !BIN: a4: 12 c2 20 21 cwbe %o0, 1, 0xa8 - !BIN: a8: 34 c2 20 21 cwbg %o0, 1, 0xac - !BIN: ac: 14 c2 20 21 cwble %o0, 1, 0xb0 - !BIN: b0: 36 c2 20 21 cwbge %o0, 1, 0xb4 - !BIN: b4: 16 c2 20 21 cwbl %o0, 1, 0xb8 - !BIN: b8: 38 c2 20 21 cwbgu %o0, 1, 0xbc - !BIN: bc: 18 c2 20 21 cwbleu %o0, 1, 0xc0 - !BIN: c0: 3a c2 20 21 cwbcc %o0, 1, 0xc4 - !BIN: c4: 1a c2 20 21 cwbcs %o0, 1, 0xc8 - !BIN: c8: 3c c2 20 21 cwbpos %o0, 1, 0xcc - !BIN: cc: 1c c2 20 21 cwbneg %o0, 1, 0xd0 - !BIN: d0: 3e c2 20 21 cwbvc %o0, 1, 0xd4 - !BIN: d4: 1e c2 20 21 cwbvs %o0, 1, 0xd8 - cwbne %o0, 1, .+4 - cwbe %o0, 1, .+4 - cwbg %o0, 1, .+4 - cwble %o0, 1, .+4 - cwbge %o0, 1, .+4 - cwbl %o0, 1, .+4 - cwbgu %o0, 1, .+4 - cwbleu %o0, 1, .+4 - cwbcc %o0, 1, .+4 - cwbcs %o0, 1, .+4 - cwbpos %o0, 1, .+4 - cwbneg %o0, 1, .+4 - cwbvc %o0, 1, .+4 - cwbvs %o0, 1, .+4 +!BIN: a0: 32 c2 20 21 cwbne %o0, 1, 0xa4 +!BIN: a4: 12 c2 20 21 cwbe %o0, 1, 0xa8 +!BIN: a8: 34 c2 20 21 cwbg %o0, 1, 0xac +!BIN: ac: 14 c2 20 21 cwble %o0, 1, 0xb0 +!BIN: b0: 36 c2 20 21 cwbge %o0, 1, 0xb4 +!BIN: b4: 16 c2 20 21 cwbl %o0, 1, 0xb8 +!BIN: b8: 38 c2 20 21 cwbgu %o0, 1, 0xbc +!BIN: bc: 18 c2 20 21 cwbleu %o0, 1, 0xc0 +!BIN: c0: 3a c2 20 21 cwbcc %o0, 1, 0xc4 +!BIN: c4: 1a c2 20 21 cwbcs %o0, 1, 0xc8 +!BIN: c8: 3c c2 20 21 cwbpos %o0, 1, 0xcc +!BIN: cc: 1c c2 20 21 cwbneg %o0, 1, 0xd0 +!BIN: d0: 3e c2 20 21 cwbvc %o0, 1, 0xd4 +!BIN: d4: 1e c2 20 21 cwbvs %o0, 1, 0xd8 +cwbne %o0, 1, .+4 +cwbe %o0, 1, .+4 +cwbg %o0, 1, .+4 +cwble %o0, 1, .+4 +cwbge %o0, 1, .+4 +cwbl %o0, 1, .+4 +cwbgu %o0, 1, .+4 +cwbleu %o0, 1, .+4 +cwbcc %o0, 1, .+4 +cwbcs %o0, 1, .+4 +cwbpos %o0, 1, .+4 +cwbneg %o0, 1, .+4 +cwbvc %o0, 1, .+4 +cwbvs %o0, 1, .+4 - !BIN: d8: 32 da 3f e1 cwbne %o0, 1, 0xd4 - !BIN: dc: 12 da 3f e1 cwbe %o0, 1, 0xd8 - !BIN: e0: 34 da 3f e1 cwbg %o0, 1, 0xdc - !BIN: e4: 14 da 3f e1 cwble %o0, 1, 0xe0 - !BIN: e8: 36 da 3f e1 cwbge %o0, 1, 0xe4 - !BIN: ec: 16 da 3f e1 cwbl %o0, 1, 0xe8 - !BIN: f0: 38 da 3f e1 cwbgu %o0, 1, 0xec - !BIN: f4: 18 da 3f e1 cwbleu %o0, 1, 0xf0 - !BIN: f8: 3a da 3f e1 cwbcc %o0, 1, 0xf4 - !BIN: fc: 1a da 3f e1 cwbcs %o0, 1, 0xf8 - !BIN: 100: 3c da 3f e1 cwbpos %o0, 1, 0xfc - !BIN: 104: 1c da 3f e1 cwbneg %o0, 1, 0x100 - !BIN: 108: 3e da 3f e1 cwbvc %o0, 1, 0x104 - !BIN: 10c: 1e da 3f e1 cwbvs %o0, 1, 0x108 - cwbne %o0, 1, .-4 - cwbe %o0, 1, .-4 - cwbg %o0, 1, .-4 - cwble %o0, 1, .-4 - cwbge %o0, 1, .-4 - cwbl %o0, 1, .-4 - cwbgu %o0, 1, .-4 - cwbleu %o0, 1, .-4 - cwbcc %o0, 1, .-4 - cwbcs %o0, 1, .-4 - cwbpos %o0, 1, .-4 - cwbneg %o0, 1, .-4 - cwbvc %o0, 1, .-4 - cwbvs %o0, 1, .-4 +!BIN: d8: 32 da 3f e1 cwbne %o0, 1, 0xd4 +!BIN: dc: 12 da 3f e1 cwbe %o0, 1, 0xd8 +!BIN: e0: 34 da 3f e1 cwbg %o0, 1, 0xdc +!BIN: e4: 14 da 3f e1 cwble %o0, 1, 0xe0 +!BIN: e8: 36 da 3f e1 cwbge %o0, 1, 0xe4 +!BIN: ec: 16 da 3f e1 cwbl %o0, 1, 0xe8 +!BIN: f0: 38 da 3f e1 cwbgu %o0, 1, 0xec +!BIN: f4: 18 da 3f e1 cwbleu %o0, 1, 0xf0 +!BIN: f8: 3a da 3f e1 cwbcc %o0, 1, 0xf4 +!BIN: fc: 1a da 3f e1 cwbcs %o0, 1, 0xf8 +!BIN: 100: 3c da 3f e1 cwbpos %o0, 1, 0xfc +!BIN: 104: 1c da 3f e1 cwbneg %o0, 1, 0x100 +!BIN: 108: 3e da 3f e1 cwbvc %o0, 1, 0x104 +!BIN: 10c: 1e da 3f e1 cwbvs %o0, 1, 0x108 +cwbne %o0, 1, .-4 +cwbe %o0, 1, .-4 +cwbg %o0, 1, .-4 +cwble %o0, 1, .-4 +cwbge %o0, 1, .-4 +cwbl %o0, 1, .-4 +cwbgu %o0, 1, .-4 +cwbleu %o0, 1, .-4 +cwbcc %o0, 1, .-4 +cwbcs %o0, 1, .-4 +cwbpos %o0, 1, .-4 +cwbneg %o0, 1, .-4 +cwbvc %o0, 1, .-4 +cwbvs %o0, 1, .-4 - !BIN: 110: 32 e2 00 29 cxbne %o0, %o1, 0x114 - !BIN: 114: 12 e2 00 29 cxbe %o0, %o1, 0x118 - !BIN: 118: 34 e2 00 29 cxbg %o0, %o1, 0x11c - !BIN: 11c: 14 e2 00 29 cxble %o0, %o1, 0x120 - !BIN: 120: 36 e2 00 29 cxbge %o0, %o1, 0x124 - !BIN: 124: 16 e2 00 29 cxbl %o0, %o1, 0x128 - !BIN: 128: 38 e2 00 29 cxbgu %o0, %o1, 0x12c - !BIN: 12c: 18 e2 00 29 cxbleu %o0, %o1, 0x130 - !BIN: 130: 3a e2 00 29 cxbcc %o0, %o1, 0x134 - !BIN: 134: 1a e2 00 29 cxbcs %o0, %o1, 0x138 - !BIN: 138: 3c e2 00 29 cxbpos %o0, %o1, 0x13c - !BIN: 13c: 1c e2 00 29 cxbneg %o0, %o1, 0x140 - !BIN: 140: 3e e2 00 29 cxbvc %o0, %o1, 0x144 - !BIN: 144: 1e e2 00 29 cxbvs %o0, %o1, 0x148 - cxbne %o0, %o1, .+4 - cxbe %o0, %o1, .+4 - cxbg %o0, %o1, .+4 - cxble %o0, %o1, .+4 - cxbge %o0, %o1, .+4 - cxbl %o0, %o1, .+4 - cxbgu %o0, %o1, .+4 - cxbleu %o0, %o1, .+4 - cxbcc %o0, %o1, .+4 - cxbcs %o0, %o1, .+4 - cxbpos %o0, %o1, .+4 - cxbneg %o0, %o1, .+4 - cxbvc %o0, %o1, .+4 - cxbvs %o0, %o1, .+4 +!BIN: 110: 32 e2 00 29 cxbne %o0, %o1, 0x114 +!BIN: 114: 12 e2 00 29 cxbe %o0, %o1, 0x118 +!BIN: 118: 34 e2 00 29 cxbg %o0, %o1, 0x11c +!BIN: 11c: 14 e2 00 29 cxble %o0, %o1, 0x120 +!BIN: 120: 36 e2 00 29 cxbge %o0, %o1, 0x124 +!BIN: 124: 16 e2 00 29 cxbl %o0, %o1, 0x128 +!BIN: 128: 38 e2 00 29 cxbgu %o0, %o1, 0x12c +!BIN: 12c: 18 e2 00 29 cxbleu %o0, %o1, 0x130 +!BIN: 130: 3a e2 00 29 cxbcc %o0, %o1, 0x134 +!BIN: 134: 1a e2 00 29 cxbcs %o0, %o1, 0x138 +!BIN: 138: 3c e2 00 29 cxbpos %o0, %o1, 0x13c +!BIN: 13c: 1c e2 00 29 cxbneg %o0, %o1, 0x140 +!BIN: 140: 3e e2 00 29 cxbvc %o0, %o1, 0x144 +!BIN: 144: 1e e2 00 29 cxbvs %o0, %o1, 0x148 +cxbne %o0, %o1, .+4 +cxbe %o0, %o1, .+4 +cxbg %o0, %o1, .+4 +cxble %o0, %o1, .+4 +cxbge %o0, %o1, .+4 +cxbl %o0, %o1, .+4 +cxbgu %o0, %o1, .+4 +cxbleu %o0, %o1, .+4 +cxbcc %o0, %o1, .+4 +cxbcs %o0, %o1, .+4 +cxbpos %o0, %o1, .+4 +cxbneg %o0, %o1, .+4 +cxbvc %o0, %o1, .+4 +cxbvs %o0, %o1, .+4 - !BIN: 148: 32 fa 1f e9 cxbne %o0, %o1, 0x144 - !BIN: 14c: 12 fa 1f e9 cxbe %o0, %o1, 0x148 - !BIN: 150: 34 fa 1f e9 cxbg %o0, %o1, 0x14c - !BIN: 154: 14 fa 1f e9 cxble %o0, %o1, 0x150 - !BIN: 158: 36 fa 1f e9 cxbge %o0, %o1, 0x154 - !BIN: 15c: 16 fa 1f e9 cxbl %o0, %o1, 0x158 - !BIN: 160: 38 fa 1f e9 cxbgu %o0, %o1, 0x15c - !BIN: 164: 18 fa 1f e9 cxbleu %o0, %o1, 0x160 - !BIN: 168: 3a fa 1f e9 cxbcc %o0, %o1, 0x164 - !BIN: 16c: 1a fa 1f e9 cxbcs %o0, %o1, 0x168 - !BIN: 170: 3c fa 1f e9 cxbpos %o0, %o1, 0x16c - !BIN: 174: 1c fa 1f e9 cxbneg %o0, %o1, 0x170 - !BIN: 178: 3e fa 1f e9 cxbvc %o0, %o1, 0x174 - !BIN: 17c: 1e fa 1f e9 cxbvs %o0, %o1, 0x178 - cxbne %o0, %o1, .-4 - cxbe %o0, %o1, .-4 - cxbg %o0, %o1, .-4 - cxble %o0, %o1, .-4 - cxbge %o0, %o1, .-4 - cxbl %o0, %o1, .-4 - cxbgu %o0, %o1, .-4 - cxbleu %o0, %o1, .-4 - cxbcc %o0, %o1, .-4 - cxbcs %o0, %o1, .-4 - cxbpos %o0, %o1, .-4 - cxbneg %o0, %o1, .-4 - cxbvc %o0, %o1, .-4 - cxbvs %o0, %o1, .-4 +!BIN: 148: 32 fa 1f e9 cxbne %o0, %o1, 0x144 +!BIN: 14c: 12 fa 1f e9 cxbe %o0, %o1, 0x148 +!BIN: 150: 34 fa 1f e9 cxbg %o0, %o1, 0x14c +!BIN: 154: 14 fa 1f e9 cxble %o0, %o1, 0x150 +!BIN: 158: 36 fa 1f e9 cxbge %o0, %o1, 0x154 +!BIN: 15c: 16 fa 1f e9 cxbl %o0, %o1, 0x158 +!BIN: 160: 38 fa 1f e9 cxbgu %o0, %o1, 0x15c +!BIN: 164: 18 fa 1f e9 cxbleu %o0, %o1, 0x160 +!BIN: 168: 3a fa 1f e9 cxbcc %o0, %o1, 0x164 +!BIN: 16c: 1a fa 1f e9 cxbcs %o0, %o1, 0x168 +!BIN: 170: 3c fa 1f e9 cxbpos %o0, %o1, 0x16c +!BIN: 174: 1c fa 1f e9 cxbneg %o0, %o1, 0x170 +!BIN: 178: 3e fa 1f e9 cxbvc %o0, %o1, 0x174 +!BIN: 17c: 1e fa 1f e9 cxbvs %o0, %o1, 0x178 +cxbne %o0, %o1, .-4 +cxbe %o0, %o1, .-4 +cxbg %o0, %o1, .-4 +cxble %o0, %o1, .-4 +cxbge %o0, %o1, .-4 +cxbl %o0, %o1, .-4 +cxbgu %o0, %o1, .-4 +cxbleu %o0, %o1, .-4 +cxbcc %o0, %o1, .-4 +cxbcs %o0, %o1, .-4 +cxbpos %o0, %o1, .-4 +cxbneg %o0, %o1, .-4 +cxbvc %o0, %o1, .-4 +cxbvs %o0, %o1, .-4 - !BIN: 180: 32 e2 20 21 cxbne %o0, 1, 0x184 - !BIN: 184: 12 e2 20 21 cxbe %o0, 1, 0x188 - !BIN: 188: 34 e2 20 21 cxbg %o0, 1, 0x18c - !BIN: 18c: 14 e2 20 21 cxble %o0, 1, 0x190 - !BIN: 190: 36 e2 20 21 cxbge %o0, 1, 0x194 - !BIN: 194: 16 e2 20 21 cxbl %o0, 1, 0x198 - !BIN: 198: 38 e2 20 21 cxbgu %o0, 1, 0x19c - !BIN: 19c: 18 e2 20 21 cxbleu %o0, 1, 0x1a0 - !BIN: 1a0: 3a e2 20 21 cxbcc %o0, 1, 0x1a4 - !BIN: 1a4: 1a e2 20 21 cxbcs %o0, 1, 0x1a8 - !BIN: 1a8: 3c e2 20 21 cxbpos %o0, 1, 0x1ac - !BIN: 1ac: 1c e2 20 21 cxbneg %o0, 1, 0x1b0 - !BIN: 1b0: 3e e2 20 21 cxbvc %o0, 1, 0x1b4 - !BIN: 1b4: 1e e2 20 21 cxbvs %o0, 1, 0x1b8 - cxbne %o0, 1, .+4 - cxbe %o0, 1, .+4 - cxbg %o0, 1, .+4 - cxble %o0, 1, .+4 - cxbge %o0, 1, .+4 - cxbl %o0, 1, .+4 - cxbgu %o0, 1, .+4 - cxbleu %o0, 1, .+4 - cxbcc %o0, 1, .+4 - cxbcs %o0, 1, .+4 - cxbpos %o0, 1, .+4 - cxbneg %o0, 1, .+4 - cxbvc %o0, 1, .+4 - cxbvs %o0, 1, .+4 +!BIN: 180: 32 e2 20 21 cxbne %o0, 1, 0x184 +!BIN: 184: 12 e2 20 21 cxbe %o0, 1, 0x188 +!BIN: 188: 34 e2 20 21 cxbg %o0, 1, 0x18c +!BIN: 18c: 14 e2 20 21 cxble %o0, 1, 0x190 +!BIN: 190: 36 e2 20 21 cxbge %o0, 1, 0x194 +!BIN: 194: 16 e2 20 21 cxbl %o0, 1, 0x198 +!BIN: 198: 38 e2 20 21 cxbgu %o0, 1, 0x19c +!BIN: 19c: 18 e2 20 21 cxbleu %o0, 1, 0x1a0 +!BIN: 1a0: 3a e2 20 21 cxbcc %o0, 1, 0x1a4 +!BIN: 1a4: 1a e2 20 21 cxbcs %o0, 1, 0x1a8 +!BIN: 1a8: 3c e2 20 21 cxbpos %o0, 1, 0x1ac +!BIN: 1ac: 1c e2 20 21 cxbneg %o0, 1, 0x1b0 +!BIN: 1b0: 3e e2 20 21 cxbvc %o0, 1, 0x1b4 +!BIN: 1b4: 1e e2 20 21 cxbvs %o0, 1, 0x1b8 +cxbne %o0, 1, .+4 +cxbe %o0, 1, .+4 +cxbg %o0, 1, .+4 +cxble %o0, 1, .+4 +cxbge %o0, 1, .+4 +cxbl %o0, 1, .+4 +cxbgu %o0, 1, .+4 +cxbleu %o0, 1, .+4 +cxbcc %o0, 1, .+4 +cxbcs %o0, 1, .+4 +cxbpos %o0, 1, .+4 +cxbneg %o0, 1, .+4 +cxbvc %o0, 1, .+4 +cxbvs %o0, 1, .+4 - !BIN: 1b8: 32 fa 3f e1 cxbne %o0, 1, 0x1b4 - !BIN: 1bc: 12 fa 3f e1 cxbe %o0, 1, 0x1b8 - !BIN: 1c0: 34 fa 3f e1 cxbg %o0, 1, 0x1bc - !BIN: 1c4: 14 fa 3f e1 cxble %o0, 1, 0x1c0 - !BIN: 1c8: 36 fa 3f e1 cxbge %o0, 1, 0x1c4 - !BIN: 1cc: 16 fa 3f e1 cxbl %o0, 1, 0x1c8 - !BIN: 1d0: 38 fa 3f e1 cxbgu %o0, 1, 0x1cc - !BIN: 1d4: 18 fa 3f e1 cxbleu %o0, 1, 0x1d0 - !BIN: 1d8: 3a fa 3f e1 cxbcc %o0, 1, 0x1d4 - !BIN: 1dc: 1a fa 3f e1 cxbcs %o0, 1, 0x1d8 - !BIN: 1e0: 3c fa 3f e1 cxbpos %o0, 1, 0x1dc - !BIN: 1e4: 1c fa 3f e1 cxbneg %o0, 1, 0x1e0 - !BIN: 1e8: 3e fa 3f e1 cxbvc %o0, 1, 0x1e4 - !BIN: 1ec: 1e fa 3f e1 cxbvs %o0, 1, 0x1e8 - cxbne %o0, 1, .-4 - cxbe %o0, 1, .-4 - cxbg %o0, 1, .-4 - cxble %o0, 1, .-4 - cxbge %o0, 1, .-4 - cxbl %o0, 1, .-4 - cxbgu %o0, 1, .-4 - cxbleu %o0, 1, .-4 - cxbcc %o0, 1, .-4 - cxbcs %o0, 1, .-4 - cxbpos %o0, 1, .-4 - cxbneg %o0, 1, .-4 - cxbvc %o0, 1, .-4 - cxbvs %o0, 1, .-4 +!BIN: 1b8: 32 fa 3f e1 cxbne %o0, 1, 0x1b4 +!BIN: 1bc: 12 fa 3f e1 cxbe %o0, 1, 0x1b8 +!BIN: 1c0: 34 fa 3f e1 cxbg %o0, 1, 0x1bc +!BIN: 1c4: 14 fa 3f e1 cxble %o0, 1, 0x1c0 +!BIN: 1c8: 36 fa 3f e1 cxbge %o0, 1, 0x1c4 +!BIN: 1cc: 16 fa 3f e1 cxbl %o0, 1, 0x1c8 +!BIN: 1d0: 38 fa 3f e1 cxbgu %o0, 1, 0x1cc +!BIN: 1d4: 18 fa 3f e1 cxbleu %o0, 1, 0x1d0 +!BIN: 1d8: 3a fa 3f e1 cxbcc %o0, 1, 0x1d4 +!BIN: 1dc: 1a fa 3f e1 cxbcs %o0, 1, 0x1d8 +!BIN: 1e0: 3c fa 3f e1 cxbpos %o0, 1, 0x1dc +!BIN: 1e4: 1c fa 3f e1 cxbneg %o0, 1, 0x1e0 +!BIN: 1e8: 3e fa 3f e1 cxbvc %o0, 1, 0x1e4 +!BIN: 1ec: 1e fa 3f e1 cxbvs %o0, 1, 0x1e8 +cxbne %o0, 1, .-4 +cxbe %o0, 1, .-4 +cxbg %o0, 1, .-4 +cxble %o0, 1, .-4 +cxbge %o0, 1, .-4 +cxbl %o0, 1, .-4 +cxbgu %o0, 1, .-4 +cxbleu %o0, 1, .-4 +cxbcc %o0, 1, .-4 +cxbcs %o0, 1, .-4 +cxbpos %o0, 1, .-4 +cxbneg %o0, 1, .-4 +cxbvc %o0, 1, .-4 +cxbvs %o0, 1, .-4