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[PowerPC] catch v2i64 shift left by 1 is add case #138772

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Merged
merged 2 commits into from
May 13, 2025
Merged

[PowerPC] catch v2i64 shift left by 1 is add case #138772

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0955560
catch v2i64 shift by 1
RolandF77 May 6, 2025
62f06a4
address comment
RolandF77 May 12, 2025
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35 changes: 35 additions & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18456,10 +18456,45 @@ static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N,
return SDValue();
}

SDValue PPCTargetLowering::combineVectorSHL(SDNode *N,
DAGCombinerInfo &DCI) const {
assert(N->getValueType(0).isVector() && "Vector type expected.");
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@amy-kwan amy-kwan May 12, 2025

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Minor nit, but we can probably pull out N->getValueType(0) and N->getOperand(0) in this function since we use them few times.


SDValue N1 = N->getOperand(1);
if (!Subtarget.hasP8Altivec() || N1.getOpcode() != ISD::BUILD_VECTOR ||
!isOperationLegal(ISD::ADD, N->getValueType(0)))
return SDValue();

// For 64-bit there is no splat immediate so we want to catch shift by 1 here
// before the BUILD_VECTOR is replaced by a load.
EVT EltTy = N->getValueType(0).getScalarType();
if (EltTy != MVT::i64)
return SDValue();

BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(N1);
APInt APSplatBits, APSplatUndef;
unsigned SplatBitSize;
bool HasAnyUndefs;
bool BVNIsConstantSplat =
BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
HasAnyUndefs, 0, !Subtarget.isLittleEndian());
if (!BVNIsConstantSplat || SplatBitSize != EltTy.getSizeInBits())
return SDValue();
uint64_t SplatBits = APSplatBits.getZExtValue();
if (SplatBits != 1)
return SDValue();

return DCI.DAG.getNode(ISD::ADD, SDLoc(N), N->getValueType(0),
N->getOperand(0), N->getOperand(0));
}

SDValue PPCTargetLowering::combineSHL(SDNode *N, DAGCombinerInfo &DCI) const {
if (auto Value = stripModuloOnShift(*this, N, DCI.DAG))
return Value;

if (N->getValueType(0).isVector())
return combineVectorSHL(N, DCI);

SDValue N0 = N->getOperand(0);
ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1));
if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() ||
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1 change: 1 addition & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.h
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Expand Up @@ -1441,6 +1441,7 @@ namespace llvm {
SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineVectorSHL(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
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5 changes: 1 addition & 4 deletions llvm/test/CodeGen/PowerPC/optimize-vector.ll
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Expand Up @@ -36,10 +36,7 @@ entry:
define dso_local <2 x i64> @x2d(<2 x i64> noundef %x) {
; CHECK-LABEL: x2d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-NEXT: lxvd2x v3, 0, r3
; CHECK-NEXT: vsld v2, v2, v3
; CHECK-NEXT: vaddudm v2, v2, v2
; CHECK-NEXT: blr
entry:
%add = shl <2 x i64> %x, <i64 1, i64 1>
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23 changes: 10 additions & 13 deletions llvm/test/CodeGen/PowerPC/pr47891.ll
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Expand Up @@ -7,26 +7,17 @@
define dso_local void @poly2_lshift1(ptr nocapture %p) local_unnamed_addr #0 {
; CHECK-LABEL: poly2_lshift1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r6, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: li r4, 72
; CHECK-NEXT: addis r6, r2, .LCPI0_1@toc@ha
; CHECK-NEXT: ld r5, 64(r3)
; CHECK-NEXT: lxvd2x vs0, r3, r4
; CHECK-NEXT: addi r6, r6, .LCPI0_1@toc@l
; CHECK-NEXT: lxvd2x v4, 0, r6
; CHECK-NEXT: addis r6, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: addi r6, r6, .LCPI0_0@toc@l
; CHECK-NEXT: xxswapd v2, vs0
; CHECK-NEXT: mtfprd f0, r5
; CHECK-NEXT: xxpermdi v3, v2, vs0, 2
; CHECK-NEXT: vsld v2, v2, v4
; CHECK-NEXT: lxvd2x vs0, r3, r4
; CHECK-NEXT: lxvd2x v4, 0, r6
; CHECK-NEXT: ld r6, 0(r3)
; CHECK-NEXT: sldi r7, r6, 1
; CHECK-NEXT: rotldi r6, r6, 1
; CHECK-NEXT: std r7, 0(r3)
; CHECK-NEXT: ld r7, 8(r3)
; CHECK-NEXT: vsrd v3, v3, v4
; CHECK-NEXT: xxlor vs0, v2, v3
; CHECK-NEXT: rldimi r6, r7, 1, 0
; CHECK-NEXT: rotldi r7, r7, 1
; CHECK-NEXT: std r6, 8(r3)
Expand All @@ -44,6 +35,8 @@ define dso_local void @poly2_lshift1(ptr nocapture %p) local_unnamed_addr #0 {
; CHECK-NEXT: std r7, 32(r3)
; CHECK-NEXT: ld r7, 40(r3)
; CHECK-NEXT: rldimi r6, r7, 1, 0
; CHECK-NEXT: xxswapd v2, vs0
; CHECK-NEXT: mtfprd f0, r5
; CHECK-NEXT: rotldi r7, r7, 1
; CHECK-NEXT: std r6, 40(r3)
; CHECK-NEXT: ld r6, 48(r3)
Expand All @@ -54,10 +47,14 @@ define dso_local void @poly2_lshift1(ptr nocapture %p) local_unnamed_addr #0 {
; CHECK-NEXT: rldimi r6, r7, 1, 0
; CHECK-NEXT: std r6, 56(r3)
; CHECK-NEXT: rotldi r6, r7, 1
; CHECK-NEXT: xxswapd vs0, vs0
; CHECK-NEXT: stxvd2x vs0, r3, r4
; CHECK-NEXT: rldimi r6, r5, 1, 0
; CHECK-NEXT: std r6, 64(r3)
; CHECK-NEXT: xxpermdi v3, v2, vs0, 2
; CHECK-NEXT: vsrd v3, v3, v4
; CHECK-NEXT: vaddudm v2, v2, v2
; CHECK-NEXT: xxlor vs0, v2, v3
; CHECK-NEXT: xxswapd vs0, vs0
; CHECK-NEXT: stxvd2x vs0, r3, r4
; CHECK-NEXT: blr
entry:
%0 = load i64, ptr %p, align 8
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