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[RISCV] Correct the SDTypeProfile for RISCVISD::PROBED_ALLOCA #139135

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Merged
merged 4 commits into from
May 8, 2025
Merged

[RISCV] Correct the SDTypeProfile for RISCVISD::PROBED_ALLOCA #139135

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3736822
[RISCV] Correct the SDTypeProfile for RISCVISD::PROBED_ALLOCA
topperc May 8, 2025
16f648f
fixup! Use SDTCisPtrTy
topperc May 8, 2025
759124e
fixup! Update PROBED_STACKALLOC_DYN
topperc May 8, 2025
849bec8
fixup! Rename $scratch->$target
topperc May 8, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24504,7 +24504,7 @@ RISCVTargetLowering::emitDynamicProbedAlloc(MachineInstr &MI,
MachineFunction &MF = *MBB->getParent();
MachineBasicBlock::iterator MBBI = MI.getIterator();
DebugLoc DL = MBB->findDebugLoc(MBBI);
Register TargetReg = MI.getOperand(1).getReg();
Register TargetReg = MI.getOperand(0).getReg();

const RISCVInstrInfo *TII = Subtarget.getInstrInfo();
bool IsRV64 = Subtarget.is64Bit();
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -1463,9 +1463,9 @@ def PROBED_STACKALLOC_RVV : Pseudo<(outs GPR:$sp),
[]>,
Sched<[]>;
let usesCustomInserter = 1 in
def PROBED_STACKALLOC_DYN : Pseudo<(outs GPR:$rd),
def PROBED_STACKALLOC_DYN : Pseudo<(outs),
(ins GPR:$scratch),
[(set GPR:$rd, (riscv_probed_alloca GPR:$scratch))]>,
[(riscv_probed_alloca GPR:$scratch)]>,
Sched<[]>;
}

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