Skip to content
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1391,7 +1391,7 @@ SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,

if (!CLI.IsTailCall) {
for (ISD::InputArg &Arg : CLI.Ins)
InVals.push_back(DAG.getUNDEF(Arg.VT));
InVals.push_back(DAG.getPOISON(Arg.VT));
}

return DAG.getEntryNode();
Expand Down Expand Up @@ -1537,7 +1537,7 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
SDValue OutputChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
Trap, DAG.getRoot());
DAG.setRoot(OutputChain);
return DAG.getUNDEF(Op.getValueType());
return DAG.getPOISON(Op.getValueType());
}

// XXX: What does the value of G->getOffset() mean?
Expand Down Expand Up @@ -1859,7 +1859,7 @@ SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
// This is the case that the vector is power of two so was evenly split.
Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad);
} else {
Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad,
Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getPOISON(VT), LoLoad,
DAG.getVectorIdxConstant(0, SL));
Join = DAG.getNode(
HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL,
Expand Down
Loading