From e05e3cf79781d85c26611adc66fc4393f33c0847 Mon Sep 17 00:00:00 2001 From: imkiva Date: Mon, 12 May 2025 17:07:20 +0800 Subject: [PATCH 1/8] [LLVM][RISCV] Implement `llvm.riscv.pause` intrinsic --- llvm/include/llvm/IR/IntrinsicsRISCV.td | 6 ++++++ llvm/lib/Target/RISCV/RISCVInstrInfo.td | 3 +++ llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td | 10 ++++++++++ llvm/test/CodeGen/RISCV/riscv-zihintpause.ll | 14 ++++++++++++++ 4 files changed, 33 insertions(+) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td create mode 100644 llvm/test/CodeGen/RISCV/riscv-zihintpause.ll diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 18b2883eb00e7..782c583db89de 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1886,6 +1886,12 @@ let TargetPrefix = "riscv" in { def int_riscv_vsm3me : RISCVBinaryAAXUnMasked; } // TargetPrefix = "riscv" +// Zihintpause extensions +//===----------------------------------------------------------------------===// +let TargetPrefix = "riscv" in { + def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; +} // TargetPrefix = "riscv" + // Vendor extensions //===----------------------------------------------------------------------===// include "llvm/IR/IntrinsicsRISCVXTHead.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index e9bdeb88e4ca8..8a5b52e591433 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2242,6 +2242,9 @@ include "RISCVInstrInfoZclsd.td" // Short Forward Branch include "RISCVInstrInfoSFB.td" +// Zihintpause extensions +include "RISCVInstrInfoZihintpause.td" + //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td new file mode 100644 index 0000000000000..60bfdf96c3f98 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td @@ -0,0 +1,10 @@ +//===-- RISCVInstrInfoZihintpause.td -----------------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// + +let Predicates = [HasStdExtZihintpause] in { + def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>; +} diff --git a/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll new file mode 100644 index 0000000000000..6c6f5e20a8b48 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll @@ -0,0 +1,14 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RVPAUSE + +declare void @llvm.riscv.pause() + +define void @test_pause() { +; RVPAUSE-LABEL: test_pause: +; RVPAUSE: # %bb.0: +; RVPAUSE-NEXT: pause +; RVPAUSE-NEXT: ret + call void @llvm.riscv.pause() + ret void +} From b8c63d6c331e57963c7c3a63af2a84e9fa5f927a Mon Sep 17 00:00:00 2001 From: imkiva Date: Mon, 12 May 2025 17:07:35 +0800 Subject: [PATCH 2/8] [Clang][RISCV] Implement `__builtin_riscv_pause` intrinsic --- clang/include/clang/Basic/BuiltinsRISCV.td | 7 +++++++ clang/lib/CodeGen/TargetBuiltins/RISCV.cpp | 6 ++++++ clang/test/CodeGen/RISCV/riscv-zihintpause.c | 14 ++++++++++++++ 3 files changed, 27 insertions(+) create mode 100644 clang/test/CodeGen/RISCV/riscv-zihintpause.c diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 3263603a8a1cf..598ec2abeeae1 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">; def ntl_store : RISCVBuiltin<"void(...)">; } // Features = "zihintntl", Attributes = [CustomTypeChecking] +//===----------------------------------------------------------------------===// +// Zihintpause extension. +//===----------------------------------------------------------------------===// +let Features = "zihintpause" in { +def pause : RISCVBuiltin<"void(...)">; +} // Features = "zihintntl" + //===----------------------------------------------------------------------===// // XCV extensions. //===----------------------------------------------------------------------===// diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index 3335239b0b6c2..0cd4f3c935e92 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -357,6 +357,12 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, return Store; } + // Zihintpause + case RISCV::BI__builtin_riscv_pause: { + llvm::Function *Fn = CGM.getIntrinsic(llvm::Intrinsic::riscv_pause); + return Builder.CreateCall(Fn, {}); + } + // XCValu case RISCV::BI__builtin_riscv_cv_alu_addN: ID = Intrinsic::riscv_cv_alu_addN; diff --git a/clang/test/CodeGen/RISCV/riscv-zihintpause.c b/clang/test/CodeGen/RISCV/riscv-zihintpause.c new file mode 100644 index 0000000000000..76d2f289a075b --- /dev/null +++ b/clang/test/CodeGen/RISCV/riscv-zihintpause.c @@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +#include + +// CHECK-LABEL: @test_builtin_pause( +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @llvm.riscv.pause() +// CHECK-NEXT: ret void +// +void test_builtin_pause() { + __builtin_riscv_pause(); +} From b5fbe804379e5a89e321e6fc7c34ba1aa89a25c0 Mon Sep 17 00:00:00 2001 From: imkiva Date: Mon, 12 May 2025 17:31:32 +0800 Subject: [PATCH 3/8] Address review comments --- clang/include/clang/Basic/BuiltinsRISCV.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 598ec2abeeae1..92b86a2d160fb 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -152,7 +152,7 @@ def ntl_store : RISCVBuiltin<"void(...)">; //===----------------------------------------------------------------------===// let Features = "zihintpause" in { def pause : RISCVBuiltin<"void(...)">; -} // Features = "zihintntl" +} // Features = "zihintpause" //===----------------------------------------------------------------------===// // XCV extensions. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td index 60bfdf96c3f98..1807609372836 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td @@ -5,6 +5,13 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard Pause Hint +// extension (Zihintpause). +// +//===----------------------------------------------------------------------===// + let Predicates = [HasStdExtZihintpause] in { def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>; } From 4fbf917dc53b6aff6bdc1913a72f2b2f163e0f83 Mon Sep 17 00:00:00 2001 From: imkiva Date: Mon, 12 May 2025 17:57:22 +0800 Subject: [PATCH 4/8] Address review comments --- clang/include/clang/Basic/BuiltinsRISCV.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 92b86a2d160fb..d429c658fb598 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -151,7 +151,7 @@ def ntl_store : RISCVBuiltin<"void(...)">; // Zihintpause extension. //===----------------------------------------------------------------------===// let Features = "zihintpause" in { -def pause : RISCVBuiltin<"void(...)">; +def pause : RISCVBuiltin<"void()">; } // Features = "zihintpause" //===----------------------------------------------------------------------===// From 42f465cf0dd5a4a231c881cd6b5096fb5c919fae Mon Sep 17 00:00:00 2001 From: imkiva Date: Mon, 12 May 2025 22:31:51 +0800 Subject: [PATCH 5/8] Address review comments --- clang/test/CodeGen/RISCV/riscv-zihintpause.c | 4 ++-- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 12 +++++++++--- .../Target/RISCV/RISCVInstrInfoZihintpause.td | 17 ----------------- 3 files changed, 11 insertions(+), 22 deletions(-) delete mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td diff --git a/clang/test/CodeGen/RISCV/riscv-zihintpause.c b/clang/test/CodeGen/RISCV/riscv-zihintpause.c index 76d2f289a075b..2e1369f3f6e0c 100644 --- a/clang/test/CodeGen/RISCV/riscv-zihintpause.c +++ b/clang/test/CodeGen/RISCV/riscv-zihintpause.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \ // RUN: | FileCheck %s - -#include +// RUN: %clang_cc1 -triple riscv64 -target-feature +zihintpause -emit-llvm %s -o - \ +// RUN: | FileCheck %s // CHECK-LABEL: @test_builtin_pause( // CHECK-NEXT: entry: diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 8a5b52e591433..fa1d0e033e656 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2198,6 +2198,15 @@ def : Pat<(binop_allwusers GPR:$rs1, immop_oneuse:$rs2), def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>; } +//===----------------------------------------------------------------------===// +// Zihintpause +//===----------------------------------------------------------------------===// + +// Zihintpause +let Predicates = [HasStdExtZihintpause] in { + def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>; +} + //===----------------------------------------------------------------------===// // Standard extensions //===----------------------------------------------------------------------===// @@ -2242,9 +2251,6 @@ include "RISCVInstrInfoZclsd.td" // Short Forward Branch include "RISCVInstrInfoSFB.td" -// Zihintpause extensions -include "RISCVInstrInfoZihintpause.td" - //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td deleted file mode 100644 index 1807609372836..0000000000000 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZihintpause.td +++ /dev/null @@ -1,17 +0,0 @@ -//===-- RISCVInstrInfoZihintpause.td -----------------------*- tablegen -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// - -//===----------------------------------------------------------------------===// -// -// This file describes the RISC-V instructions from the standard Pause Hint -// extension (Zihintpause). -// -//===----------------------------------------------------------------------===// - -let Predicates = [HasStdExtZihintpause] in { - def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>; -} From 653b54e72b91e4b717e91f2319ec21962049f009 Mon Sep 17 00:00:00 2001 From: imkiva Date: Tue, 13 May 2025 11:27:39 +0800 Subject: [PATCH 6/8] Add `NoThrow` attribute to `__builtin_riscv_pause()` --- clang/include/clang/Basic/BuiltinsRISCV.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index d429c658fb598..cf8bb2bbb735b 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -150,9 +150,9 @@ def ntl_store : RISCVBuiltin<"void(...)">; //===----------------------------------------------------------------------===// // Zihintpause extension. //===----------------------------------------------------------------------===// -let Features = "zihintpause" in { +let Features = "zihintpause", Attributes = [NoThrow] in { def pause : RISCVBuiltin<"void()">; -} // Features = "zihintpause" +} // Features = "zihintpause", Attributes = [NoThrow] //===----------------------------------------------------------------------===// // XCV extensions. From d8a62f95163b5092f2de1d0b9ae5f39b946dc9d4 Mon Sep 17 00:00:00 2001 From: imkiva Date: Tue, 13 May 2025 11:35:50 +0800 Subject: [PATCH 7/8] Add changes to clang release notes --- clang/docs/ReleaseNotes.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index e362ec595a3bb..87464723ef106 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -790,6 +790,8 @@ RISC-V Support - `Zicsr` / `Zifencei` are allowed to be duplicated in the presence of `g` in `-march`. +- Add support for the `__builtin_riscv_pause()` intrinsic from the `Zihintpause` extension. + CUDA/HIP Language Changes ^^^^^^^^^^^^^^^^^^^^^^^^^ From 798b8f2f515239cde5b0463b4014190de1f62924 Mon Sep 17 00:00:00 2001 From: imkiva Date: Tue, 13 May 2025 14:22:25 +0800 Subject: [PATCH 8/8] Format code --- clang/include/clang/Basic/BuiltinsRISCV.td | 3 +-- llvm/include/llvm/IR/IntrinsicsRISCV.td | 5 ++--- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 5 ++--- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index cf8bb2bbb735b..b2cd5648e008f 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -150,9 +150,8 @@ def ntl_store : RISCVBuiltin<"void(...)">; //===----------------------------------------------------------------------===// // Zihintpause extension. //===----------------------------------------------------------------------===// -let Features = "zihintpause", Attributes = [NoThrow] in { +let Features = "zihintpause", Attributes = [NoThrow] in def pause : RISCVBuiltin<"void()">; -} // Features = "zihintpause", Attributes = [NoThrow] //===----------------------------------------------------------------------===// // XCV extensions. diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 782c583db89de..642a74f097d9e 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1888,9 +1888,8 @@ let TargetPrefix = "riscv" in { // Zihintpause extensions //===----------------------------------------------------------------------===// -let TargetPrefix = "riscv" in { - def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; -} // TargetPrefix = "riscv" +let TargetPrefix = "riscv" in +def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index fa1d0e033e656..9c61a9aa4b9fe 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2203,9 +2203,8 @@ def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>; //===----------------------------------------------------------------------===// // Zihintpause -let Predicates = [HasStdExtZihintpause] in { - def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>; -} +let Predicates = [HasStdExtZihintpause] in +def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>; //===----------------------------------------------------------------------===// // Standard extensions