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[RISCV] Support LLVM IR intrinsics for XAndesVDot #140223

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Merged
merged 4 commits into from
May 25, 2025
Merged

[RISCV] Support LLVM IR intrinsics for XAndesVDot #140223

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d145d56
[RISCV] Support LLVM IR intrinsics for XAndesVDot
tclin914 May 16, 2025
77fd88b
Move VPatTernaryVD4DOT_VV to the section for multiclass
tclin914 May 19, 2025
9a32ed3
Remove unnecessary LMULInfos
tclin914 May 19, 2025
7f43a62
Remove declarations
tclin914 May 22, 2025
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5 changes: 5 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsRISCVXAndes.td
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Original file line number Diff line number Diff line change
Expand Up @@ -14,4 +14,9 @@ let TargetPrefix = "riscv" in {
// Andes Vector Packed FP16 Extension
defm nds_vfpmadt : RISCVBinaryAAXRoundingMode;
defm nds_vfpmadb : RISCVBinaryAAXRoundingMode;

// Andes Vector Dot Product Extension
defm nds_vd4dots : RISCVTernaryWide;
defm nds_vd4dotu : RISCVTernaryWide;
defm nds_vd4dotsu : RISCVTernaryWide;
}
43 changes: 43 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
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Expand Up @@ -388,6 +388,27 @@ multiclass VPatVFPMADBinaryV_VX_RM<string intrinsic, string instruction,
}
}

multiclass VPseudoVD4DOT_VV {
foreach m = [V_MF2, V_M1, V_M2, V_M4, V_M8] in {
defm "" : VPseudoBinaryV_VV<m>,
SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX,
forcePassthruRead=true>;
}
}

multiclass VPatTernaryVD4DOT_VV<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> {
foreach vtiToWti = vtilist in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
let Predicates = GetVTypePredicates<wti>.Predicates in
defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",
wti.Vector, vti.Vector, vti.Vector,
wti.Mask, wti.Log2SEW, vti.LMul,
wti.RegClass, vti.RegClass, vti.RegClass>;
}
}

//===----------------------------------------------------------------------===//
// XAndesPerf
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -499,3 +520,25 @@ defm PseudoNDS_VFPMADB : VPseudoVFPMAD_VF_RM;

defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT", AllFP16Vectors>;
defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB", AllFP16Vectors>;

let Predicates = [HasVendorXAndesVDot] in {
defm PseudoNDS_VD4DOTS : VPseudoVD4DOT_VV;
defm PseudoNDS_VD4DOTU : VPseudoVD4DOT_VV;
defm PseudoNDS_VD4DOTSU : VPseudoVD4DOT_VV;
}

defset list<VTypeInfoToWide> AllQuadWidenableVD4DOTVectors = {
def : VTypeInfoToWide<VI8MF2, VI32MF2>;
def : VTypeInfoToWide<VI8M1, VI32M1>;
def : VTypeInfoToWide<VI8M2, VI32M2>;
def : VTypeInfoToWide<VI8M4, VI32M4>;
def : VTypeInfoToWide<VI8M8, VI32M8>;
def : VTypeInfoToWide<VI16M1, VI64M1>;
def : VTypeInfoToWide<VI16M2, VI64M2>;
def : VTypeInfoToWide<VI16M4, VI64M4>;
def : VTypeInfoToWide<VI16M8, VI64M8>;
}

defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS", AllQuadWidenableVD4DOTVectors>;
defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU", AllQuadWidenableVD4DOTVectors>;
defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU", AllQuadWidenableVD4DOTVectors>;
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