diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 236c55cb04142..0985f47f7a6d4 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -4917,8 +4917,7 @@ unsigned ResourceSegments::getFirstAvailableAt(
     unsigned CurrCycle, unsigned AcquireAtCycle, unsigned ReleaseAtCycle,
     std::function<ResourceSegments::IntervalTy(unsigned, unsigned, unsigned)>
         IntervalBuilder) const {
-  assert(std::is_sorted(std::begin(_Intervals), std::end(_Intervals),
-                        sortIntervals) &&
+  assert(llvm::is_sorted(_Intervals, sortIntervals) &&
          "Cannot execute on an un-sorted set of intervals.");
 
   // Zero resource usage is allowed by TargetSchedule.td but we do not construct
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index e29aeb84f7669..8d781059c464f 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -1748,11 +1748,12 @@ static void assignSlotsUsingVGPRBlocks(MachineFunction &MF,
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 
-  assert(std::is_sorted(CSI.begin(), CSI.end(),
-                        [](const CalleeSavedInfo &A, const CalleeSavedInfo &B) {
-                          return A.getReg() < B.getReg();
-                        }) &&
-         "Callee saved registers not sorted");
+  assert(
+      llvm::is_sorted(CSI,
+                      [](const CalleeSavedInfo &A, const CalleeSavedInfo &B) {
+                        return A.getReg() < B.getReg();
+                      }) &&
+      "Callee saved registers not sorted");
 
   auto CanUseBlockOps = [&](const CalleeSavedInfo &CSI) {
     return !CSI.isSpilledToReg() &&