[AArch64] TableGen-erate SDNode descriptions #140472
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| @@ -1,12 +1,12 @@ | |||
| //===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp -------------------------===// | |||
| //===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp ------------------===// | |||
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The file path needs to be updated or the line replaced with
Suggested change
| //===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp ------------------===// | |
| //===----------------------------------------------------------------------===// |
as the coding standard no longer requires it to contain the file path.
The changes in unittests/ are necessary since the test now requires linking with AArch64CodeGen it didn't depend on before (even though it included AArch64ISelLowering.h).
Could be extracted into a separate PR.
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Replace the line 👍 (I have no strong feelings about splitting the unittests/ changes off or not).
MacDue
requested review from
davemgreen,
david-arm,
paulwalker-arm and
sdesmalen-arm
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|
@llvm/pr-subscribers-backend-aarch64 Author: Benjamin Maxwell (MacDue) ChangesThis is an attempt to continue @s-barannikov's work TableGen-erating SDNode descriptions. This takes the initial patch from #119709, moves the rest of the AArch64ISD nodes to TableGen, and fixes some issues found by the generated SDNode verification. The main changes (alongside generating AArch64ISD nodes and verification) are: The following (dead) AArch64ISD nodes (and associated code) are removed:
No code path could emit any of these nodes. Claims of having in/out glue were removed from the following nodes:
None of these nodes were ever emitted with glue (so failed the generated verification). The The following nodes are now always emitted with a glue return value:
The glue return value was added inconsistently for these nodes (which again failed verification). And finally, avoid using Patch is 88.35 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/140472.diff 16 Files Affected:
diff --git a/llvm/docs/AArch64SME.rst b/llvm/docs/AArch64SME.rst
index b5a01cb204b81..ac8ce32ddb9e6 100644
--- a/llvm/docs/AArch64SME.rst
+++ b/llvm/docs/AArch64SME.rst
@@ -213,12 +213,14 @@ Instruction Selection Nodes
.. code-block:: none
- AArch64ISD::SMSTART Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
- AArch64ISD::SMSTOP Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
-
-The ``SMSTART/SMSTOP`` nodes take ``CurrentState`` and ``ExpectedState`` operand for
-the case of a conditional SMSTART/SMSTOP. The instruction will only be executed
-if CurrentState != ExpectedState.
+ AArch64ISD::SMSTART Chain, [SM|ZA|Both][, RegMask]
+ AArch64ISD::SMSTOP Chain, [SM|ZA|Both][, RegMask]
+ AArch64ISD::COND_SMSTART Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
+ AArch64ISD::COND_SMSTOP Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
+
+The ``COND_SMSTART/COND_SMSTOP`` nodes additionally take ``CurrentState`` and
+``ExpectedState``, in this case the instruction will only be executed if
+``CurrentState != ExpectedState``.
When ``CurrentState`` and ``ExpectedState`` can be evaluated at compile-time
(i.e. they are both constants) then an unconditional ``smstart/smstop``
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 96fa85179d023..2eb8c6008db0f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -7216,57 +7216,6 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
}
break;
}
- case AArch64ISD::SVE_LD2_MERGE_ZERO: {
- if (VT == MVT::nxv16i8) {
- SelectPredicatedLoad(Node, 2, 0, AArch64::LD2B_IMM, AArch64::LD2B);
- return;
- } else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
- VT == MVT::nxv8bf16) {
- SelectPredicatedLoad(Node, 2, 1, AArch64::LD2H_IMM, AArch64::LD2H);
- return;
- } else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
- SelectPredicatedLoad(Node, 2, 2, AArch64::LD2W_IMM, AArch64::LD2W);
- return;
- } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
- SelectPredicatedLoad(Node, 2, 3, AArch64::LD2D_IMM, AArch64::LD2D);
- return;
- }
- break;
- }
- case AArch64ISD::SVE_LD3_MERGE_ZERO: {
- if (VT == MVT::nxv16i8) {
- SelectPredicatedLoad(Node, 3, 0, AArch64::LD3B_IMM, AArch64::LD3B);
- return;
- } else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
- VT == MVT::nxv8bf16) {
- SelectPredicatedLoad(Node, 3, 1, AArch64::LD3H_IMM, AArch64::LD3H);
- return;
- } else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
- SelectPredicatedLoad(Node, 3, 2, AArch64::LD3W_IMM, AArch64::LD3W);
- return;
- } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
- SelectPredicatedLoad(Node, 3, 3, AArch64::LD3D_IMM, AArch64::LD3D);
- return;
- }
- break;
- }
- case AArch64ISD::SVE_LD4_MERGE_ZERO: {
- if (VT == MVT::nxv16i8) {
- SelectPredicatedLoad(Node, 4, 0, AArch64::LD4B_IMM, AArch64::LD4B);
- return;
- } else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16 ||
- VT == MVT::nxv8bf16) {
- SelectPredicatedLoad(Node, 4, 1, AArch64::LD4H_IMM, AArch64::LD4H);
- return;
- } else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
- SelectPredicatedLoad(Node, 4, 2, AArch64::LD4W_IMM, AArch64::LD4W);
- return;
- } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
- SelectPredicatedLoad(Node, 4, 3, AArch64::LD4D_IMM, AArch64::LD4D);
- return;
- }
- break;
- }
}
// Select the default instruction
@@ -7340,15 +7289,6 @@ static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
return cast<VTSDNode>(Root->getOperand(3))->getVT();
case AArch64ISD::ST1_PRED:
return cast<VTSDNode>(Root->getOperand(4))->getVT();
- case AArch64ISD::SVE_LD2_MERGE_ZERO:
- return getPackedVectorTypeFromPredicateType(
- Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/2);
- case AArch64ISD::SVE_LD3_MERGE_ZERO:
- return getPackedVectorTypeFromPredicateType(
- Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/3);
- case AArch64ISD::SVE_LD4_MERGE_ZERO:
- return getPackedVectorTypeFromPredicateType(
- Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/4);
default:
break;
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 293292d47dd48..bbed51926e73f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2710,332 +2710,6 @@ AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
return AArch64::createFastISel(funcInfo, libInfo);
}
-const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
-#define MAKE_CASE(V) \
- case V: \
- return #V;
- switch ((AArch64ISD::NodeType)Opcode) {
- case AArch64ISD::FIRST_NUMBER:
- break;
- MAKE_CASE(AArch64ISD::ALLOCATE_ZA_BUFFER)
- MAKE_CASE(AArch64ISD::INIT_TPIDR2OBJ)
- MAKE_CASE(AArch64ISD::GET_SME_SAVE_SIZE)
- MAKE_CASE(AArch64ISD::ALLOC_SME_SAVE_BUFFER)
- MAKE_CASE(AArch64ISD::COALESCER_BARRIER)
- MAKE_CASE(AArch64ISD::VG_SAVE)
- MAKE_CASE(AArch64ISD::VG_RESTORE)
- MAKE_CASE(AArch64ISD::SMSTART)
- MAKE_CASE(AArch64ISD::SMSTOP)
- MAKE_CASE(AArch64ISD::RESTORE_ZA)
- MAKE_CASE(AArch64ISD::RESTORE_ZT)
- MAKE_CASE(AArch64ISD::SAVE_ZT)
- MAKE_CASE(AArch64ISD::CALL)
- MAKE_CASE(AArch64ISD::ADRP)
- MAKE_CASE(AArch64ISD::ADR)
- MAKE_CASE(AArch64ISD::ADDlow)
- MAKE_CASE(AArch64ISD::AUTH_CALL)
- MAKE_CASE(AArch64ISD::AUTH_TC_RETURN)
- MAKE_CASE(AArch64ISD::AUTH_CALL_RVMARKER)
- MAKE_CASE(AArch64ISD::LOADgot)
- MAKE_CASE(AArch64ISD::RET_GLUE)
- MAKE_CASE(AArch64ISD::BRCOND)
- MAKE_CASE(AArch64ISD::CSEL)
- MAKE_CASE(AArch64ISD::CSINV)
- MAKE_CASE(AArch64ISD::CSNEG)
- MAKE_CASE(AArch64ISD::CSINC)
- MAKE_CASE(AArch64ISD::THREAD_POINTER)
- MAKE_CASE(AArch64ISD::TLSDESC_CALLSEQ)
- MAKE_CASE(AArch64ISD::TLSDESC_AUTH_CALLSEQ)
- MAKE_CASE(AArch64ISD::PROBED_ALLOCA)
- MAKE_CASE(AArch64ISD::ABDS_PRED)
- MAKE_CASE(AArch64ISD::ABDU_PRED)
- MAKE_CASE(AArch64ISD::HADDS_PRED)
- MAKE_CASE(AArch64ISD::HADDU_PRED)
- MAKE_CASE(AArch64ISD::MUL_PRED)
- MAKE_CASE(AArch64ISD::MULHS_PRED)
- MAKE_CASE(AArch64ISD::MULHU_PRED)
- MAKE_CASE(AArch64ISD::RHADDS_PRED)
- MAKE_CASE(AArch64ISD::RHADDU_PRED)
- MAKE_CASE(AArch64ISD::SDIV_PRED)
- MAKE_CASE(AArch64ISD::SHL_PRED)
- MAKE_CASE(AArch64ISD::SMAX_PRED)
- MAKE_CASE(AArch64ISD::SMIN_PRED)
- MAKE_CASE(AArch64ISD::SRA_PRED)
- MAKE_CASE(AArch64ISD::SRL_PRED)
- MAKE_CASE(AArch64ISD::UDIV_PRED)
- MAKE_CASE(AArch64ISD::UMAX_PRED)
- MAKE_CASE(AArch64ISD::UMIN_PRED)
- MAKE_CASE(AArch64ISD::SRAD_MERGE_OP1)
- MAKE_CASE(AArch64ISD::FNEG_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FCEIL_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FFLOOR_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FNEARBYINT_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FRINT_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FROUND_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FTRUNC_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FP_ROUND_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FP_EXTEND_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FCVTX_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FCVTZU_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FCVTZS_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FSQRT_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FRECPX_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::FABS_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::ABS_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::NEG_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::SETCC_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::ADC)
- MAKE_CASE(AArch64ISD::SBC)
- MAKE_CASE(AArch64ISD::ADDS)
- MAKE_CASE(AArch64ISD::SUBS)
- MAKE_CASE(AArch64ISD::ADCS)
- MAKE_CASE(AArch64ISD::SBCS)
- MAKE_CASE(AArch64ISD::ANDS)
- MAKE_CASE(AArch64ISD::CCMP)
- MAKE_CASE(AArch64ISD::CCMN)
- MAKE_CASE(AArch64ISD::FCCMP)
- MAKE_CASE(AArch64ISD::FCMP)
- MAKE_CASE(AArch64ISD::STRICT_FCMP)
- MAKE_CASE(AArch64ISD::STRICT_FCMPE)
- MAKE_CASE(AArch64ISD::FCVTXN)
- MAKE_CASE(AArch64ISD::SME_ZA_LDR)
- MAKE_CASE(AArch64ISD::SME_ZA_STR)
- MAKE_CASE(AArch64ISD::DUP)
- MAKE_CASE(AArch64ISD::DUPLANE8)
- MAKE_CASE(AArch64ISD::DUPLANE16)
- MAKE_CASE(AArch64ISD::DUPLANE32)
- MAKE_CASE(AArch64ISD::DUPLANE64)
- MAKE_CASE(AArch64ISD::DUPLANE128)
- MAKE_CASE(AArch64ISD::MOVI)
- MAKE_CASE(AArch64ISD::MOVIshift)
- MAKE_CASE(AArch64ISD::MOVIedit)
- MAKE_CASE(AArch64ISD::MOVImsl)
- MAKE_CASE(AArch64ISD::FMOV)
- MAKE_CASE(AArch64ISD::MVNIshift)
- MAKE_CASE(AArch64ISD::MVNImsl)
- MAKE_CASE(AArch64ISD::BICi)
- MAKE_CASE(AArch64ISD::ORRi)
- MAKE_CASE(AArch64ISD::BSP)
- MAKE_CASE(AArch64ISD::ZIP1)
- MAKE_CASE(AArch64ISD::ZIP2)
- MAKE_CASE(AArch64ISD::UZP1)
- MAKE_CASE(AArch64ISD::UZP2)
- MAKE_CASE(AArch64ISD::TRN1)
- MAKE_CASE(AArch64ISD::TRN2)
- MAKE_CASE(AArch64ISD::REV16)
- MAKE_CASE(AArch64ISD::REV32)
- MAKE_CASE(AArch64ISD::REV64)
- MAKE_CASE(AArch64ISD::EXT)
- MAKE_CASE(AArch64ISD::SPLICE)
- MAKE_CASE(AArch64ISD::VSHL)
- MAKE_CASE(AArch64ISD::VLSHR)
- MAKE_CASE(AArch64ISD::VASHR)
- MAKE_CASE(AArch64ISD::VSLI)
- MAKE_CASE(AArch64ISD::VSRI)
- MAKE_CASE(AArch64ISD::FCMEQ)
- MAKE_CASE(AArch64ISD::FCMGE)
- MAKE_CASE(AArch64ISD::FCMGT)
- MAKE_CASE(AArch64ISD::SADDV)
- MAKE_CASE(AArch64ISD::UADDV)
- MAKE_CASE(AArch64ISD::UADDLV)
- MAKE_CASE(AArch64ISD::SADDLV)
- MAKE_CASE(AArch64ISD::SADDWT)
- MAKE_CASE(AArch64ISD::SADDWB)
- MAKE_CASE(AArch64ISD::UADDWT)
- MAKE_CASE(AArch64ISD::UADDWB)
- MAKE_CASE(AArch64ISD::SDOT)
- MAKE_CASE(AArch64ISD::UDOT)
- MAKE_CASE(AArch64ISD::USDOT)
- MAKE_CASE(AArch64ISD::SMINV)
- MAKE_CASE(AArch64ISD::UMINV)
- MAKE_CASE(AArch64ISD::SMAXV)
- MAKE_CASE(AArch64ISD::UMAXV)
- MAKE_CASE(AArch64ISD::SADDV_PRED)
- MAKE_CASE(AArch64ISD::UADDV_PRED)
- MAKE_CASE(AArch64ISD::SMAXV_PRED)
- MAKE_CASE(AArch64ISD::UMAXV_PRED)
- MAKE_CASE(AArch64ISD::SMINV_PRED)
- MAKE_CASE(AArch64ISD::UMINV_PRED)
- MAKE_CASE(AArch64ISD::ORV_PRED)
- MAKE_CASE(AArch64ISD::EORV_PRED)
- MAKE_CASE(AArch64ISD::ANDV_PRED)
- MAKE_CASE(AArch64ISD::CLASTA_N)
- MAKE_CASE(AArch64ISD::CLASTB_N)
- MAKE_CASE(AArch64ISD::LASTA)
- MAKE_CASE(AArch64ISD::LASTB)
- MAKE_CASE(AArch64ISD::REINTERPRET_CAST)
- MAKE_CASE(AArch64ISD::LS64_BUILD)
- MAKE_CASE(AArch64ISD::LS64_EXTRACT)
- MAKE_CASE(AArch64ISD::TBL)
- MAKE_CASE(AArch64ISD::FADD_PRED)
- MAKE_CASE(AArch64ISD::FADDA_PRED)
- MAKE_CASE(AArch64ISD::FADDV_PRED)
- MAKE_CASE(AArch64ISD::FDIV_PRED)
- MAKE_CASE(AArch64ISD::FMA_PRED)
- MAKE_CASE(AArch64ISD::FMAX_PRED)
- MAKE_CASE(AArch64ISD::FMAXV_PRED)
- MAKE_CASE(AArch64ISD::FMAXNM_PRED)
- MAKE_CASE(AArch64ISD::FMAXNMV_PRED)
- MAKE_CASE(AArch64ISD::FMIN_PRED)
- MAKE_CASE(AArch64ISD::FMINV_PRED)
- MAKE_CASE(AArch64ISD::FMINNM_PRED)
- MAKE_CASE(AArch64ISD::FMINNMV_PRED)
- MAKE_CASE(AArch64ISD::FMUL_PRED)
- MAKE_CASE(AArch64ISD::FSUB_PRED)
- MAKE_CASE(AArch64ISD::RDSVL)
- MAKE_CASE(AArch64ISD::BIC)
- MAKE_CASE(AArch64ISD::CBZ)
- MAKE_CASE(AArch64ISD::CBNZ)
- MAKE_CASE(AArch64ISD::TBZ)
- MAKE_CASE(AArch64ISD::TBNZ)
- MAKE_CASE(AArch64ISD::TC_RETURN)
- MAKE_CASE(AArch64ISD::PREFETCH)
- MAKE_CASE(AArch64ISD::SITOF)
- MAKE_CASE(AArch64ISD::UITOF)
- MAKE_CASE(AArch64ISD::NVCAST)
- MAKE_CASE(AArch64ISD::MRS)
- MAKE_CASE(AArch64ISD::SQSHL_I)
- MAKE_CASE(AArch64ISD::UQSHL_I)
- MAKE_CASE(AArch64ISD::SRSHR_I)
- MAKE_CASE(AArch64ISD::URSHR_I)
- MAKE_CASE(AArch64ISD::SQSHLU_I)
- MAKE_CASE(AArch64ISD::WrapperLarge)
- MAKE_CASE(AArch64ISD::LD2post)
- MAKE_CASE(AArch64ISD::LD3post)
- MAKE_CASE(AArch64ISD::LD4post)
- MAKE_CASE(AArch64ISD::ST2post)
- MAKE_CASE(AArch64ISD::ST3post)
- MAKE_CASE(AArch64ISD::ST4post)
- MAKE_CASE(AArch64ISD::LD1x2post)
- MAKE_CASE(AArch64ISD::LD1x3post)
- MAKE_CASE(AArch64ISD::LD1x4post)
- MAKE_CASE(AArch64ISD::ST1x2post)
- MAKE_CASE(AArch64ISD::ST1x3post)
- MAKE_CASE(AArch64ISD::ST1x4post)
- MAKE_CASE(AArch64ISD::LD1DUPpost)
- MAKE_CASE(AArch64ISD::LD2DUPpost)
- MAKE_CASE(AArch64ISD::LD3DUPpost)
- MAKE_CASE(AArch64ISD::LD4DUPpost)
- MAKE_CASE(AArch64ISD::LD1LANEpost)
- MAKE_CASE(AArch64ISD::LD2LANEpost)
- MAKE_CASE(AArch64ISD::LD3LANEpost)
- MAKE_CASE(AArch64ISD::LD4LANEpost)
- MAKE_CASE(AArch64ISD::ST2LANEpost)
- MAKE_CASE(AArch64ISD::ST3LANEpost)
- MAKE_CASE(AArch64ISD::ST4LANEpost)
- MAKE_CASE(AArch64ISD::SMULL)
- MAKE_CASE(AArch64ISD::UMULL)
- MAKE_CASE(AArch64ISD::PMULL)
- MAKE_CASE(AArch64ISD::FRECPE)
- MAKE_CASE(AArch64ISD::FRECPS)
- MAKE_CASE(AArch64ISD::FRSQRTE)
- MAKE_CASE(AArch64ISD::FRSQRTS)
- MAKE_CASE(AArch64ISD::STG)
- MAKE_CASE(AArch64ISD::STZG)
- MAKE_CASE(AArch64ISD::ST2G)
- MAKE_CASE(AArch64ISD::STZ2G)
- MAKE_CASE(AArch64ISD::SUNPKHI)
- MAKE_CASE(AArch64ISD::SUNPKLO)
- MAKE_CASE(AArch64ISD::UUNPKHI)
- MAKE_CASE(AArch64ISD::UUNPKLO)
- MAKE_CASE(AArch64ISD::INSR)
- MAKE_CASE(AArch64ISD::PTEST)
- MAKE_CASE(AArch64ISD::PTEST_ANY)
- MAKE_CASE(AArch64ISD::PTRUE)
- MAKE_CASE(AArch64ISD::LD1_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::LD1S_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::LDNF1_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::LDNF1S_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::LDFF1_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::LDFF1S_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::LD1RQ_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::LD1RO_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::SVE_LD2_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::SVE_LD3_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::SVE_LD4_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1_SXTW_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1_UXTW_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1_IMM_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1Q_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1Q_INDEX_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1S_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1S_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1S_SXTW_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1S_UXTW_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLD1S_IMM_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1_SXTW_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1_UXTW_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1_IMM_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1S_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDFF1S_IMM_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDNT1_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDNT1_INDEX_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::GLDNT1S_MERGE_ZERO)
- MAKE_CASE(AArch64ISD::SST1Q_PRED)
- MAKE_CASE(AArch64ISD::SST1Q_INDEX_PRED)
- MAKE_CASE(AArch64ISD::ST1_PRED)
- MAKE_CASE(AArch64ISD::SST1_PRED)
- MAKE_CASE(AArch64ISD::SST1_SCALED_PRED)
- MAKE_CASE(AArch64ISD::SST1_SXTW_PRED)
- MAKE_CASE(AArch64ISD::SST1_UXTW_PRED)
- MAKE_CASE(AArch64ISD::SST1_SXTW_SCALED_PRED)
- MAKE_CASE(AArch64ISD::SST1_UXTW_SCALED_PRED)
- MAKE_CASE(AArch64ISD::SST1_IMM_PRED)
- MAKE_CASE(AArch64ISD::SSTNT1_PRED)
- MAKE_CASE(AArch64ISD::SSTNT1_INDEX_PRED)
- MAKE_CASE(AArch64ISD::LDP)
- MAKE_CASE(AArch64ISD::LDIAPP)
- MAKE_CASE(AArch64ISD::LDNP)
- MAKE_CASE(AArch64ISD::STP)
- MAKE_CASE(AArch64ISD::STILP)
- MAKE_CASE(AArch64ISD::STNP)
- MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::BSWAP_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::REVH_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::REVW_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::REVD_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::CTLZ_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::CTPOP_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::DUP_MERGE_PASSTHRU)
- MAKE_CASE(AArch64ISD::INDEX_VECTOR)
- MAKE_CASE(AArch64ISD::ADDP)
- MAKE_CASE(AArch64ISD::SADDLP)
- MAKE_CASE(AArch64ISD::UADDLP)
- MAKE_CASE(AArch64ISD::CALL_RVMARKER)
- MAKE_CASE(AArch64ISD::ASSERT_ZEXT_BOOL)
- MAKE_CASE(AArch64ISD::CALL_BTI)
- MAKE_CASE(AArch64ISD::MRRS)
- MAKE_CASE(AArch64ISD::MSRR)
- MAKE_CASE(AArch64ISD::RSHRNB_I)
- MAKE_CASE(AArch64ISD::CTTZ_ELTS)
- MAKE_CASE(AArch64ISD::CALL_ARM64EC_TO_X64)
- MAKE_CASE(AArch64ISD::URSHR_I_PRED)
- MAKE_CASE(AArch64ISD::CB)
- }
-#undef MAKE_CASE
- return nullptr;
-}
-
MachineBasicBlock *
AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,
MachineBasicBlock *MBB) const {
@@ -6031,16 +5705,14 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_VOID(SDValue Op,
}
case Intrinsic::aarch64_sme_za_enable:
return DAG.getNode(
- AArch64ISD::SMSTART, DL, MVT::Other,
+ AArch64ISD::SMSTART, DL, DAG.getVTList(MVT::Other, MVT::Glue),
Op->getOperand(0), // Chain
- DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
- DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
+ DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
case Intrinsic::aarch64_sme_za_disable:
return DAG.getNode(
- AArch64ISD::SMSTOP, DL, MVT::Other,
+ AArch64ISD::SMSTOP, DL, DAG.getVTList(MVT::Other, MVT::Glue),
Op->getOperand(0), // Chain
- DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
- DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
+ DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
}
}
@@ -8529,8 +8201,8 @@ SDValue AArch64TargetLowering::LowerCallResult(
}
if (RequiresSMChange && isPassedInFPR(VA.getValVT()))
- Val = DAG.getNode(AArch64ISD::COALESCER_BARRIER, DL, Val.getValueType(),
- Val);
+ Val = DAG.getNode(AArch64ISD::COALESCER_BARRIER, DL,
+ DAG.getVTList(Val.getValueType(), MVT::Glue), Val);
InVals.push_back(Val);
}
@@ -8913,18 +8585,22 @@ SDValue AArch64TargetLowering::changeStreamingMode(SelectionDAG &DAG, SDLoc DL,
SDValue RegMask = DAG.getRegisterMask(TRI->getSMStartStopCallPreservedMask());
SDValue MSROp =
DAG.getTargetConstant((int32_t)AArch64SVCR::SVCRSM, DL, MVT::i32);
- SDValue ConditionOp = DAG.getTargetConstant(Condition, DL, MVT::i64);
- SmallVector<SDValue> Ops = {Chain, MSROp, ConditionOp};
+ SmallVector<SDValue> Ops = {Chain, MSROp};
+ unsigned Opcode;
if (Condition != AArch64SME::Always) {
+ SDValue ConditionOp = DAG.getTargetConstant(Condition, DL, MVT::i64);
+ Opcode = Enable ? AArch64ISD::COND_SMSTART : AArch64ISD::COND_SMSTOP;
assert(PStateSM && "PStateSM should be defined");
+ Ops.push_back(ConditionOp);
Ops.push_back(PStateSM);
+ } else {
+ Opcode = Enable ? AArch64ISD::SMSTART : AArch64ISD::SMSTOP;
}
Ops.push_back(RegMask);
if (InGlue)
Ops.push_back(InGlue);
- unsigned Opcode = Enable ? AArch64ISD::SMSTART : AArch64ISD::SMSTOP;
return DAG.getNode(Opcode, DL, DAG.getVTList(MVT::Other, MVT::Glue), Ops);
}
@@ -9189,9 +8865,8 @@ AArch64TargetLowe...
[truncated]
|
MacDue
commented
May 19, 2025
Collaborator
|
Can this PR be broken up? Removing unused nodes/code can be done in isolation? The same is hopefully true for things like the REV fix and the new documentation added to the td file. |
Member
Author
Sure, I'll split off some of the fixes/NFCs soon 👍 |
MacDue
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May 20, 2025
…OP (NFC) The conditional variants of SMSTART/STOP currently take the current PStateSM as a variadic value. This is not supported by the verification added in llvm#140472 (which requires variadic values to be of type Register or RegisterMask), so this patch splits the the conditional variants into new `COND_` nodes, where these extra parameters are fixed arguments. Suggested in llvm#140472 (comment) Part of llvm#140472.
MacDue
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May 20, 2025
…ings The use of `LowerToPredicatedOp` here seems like a mistake as `LowerToPredicatedOp` turns the SDValue passed to it into the desired predicated node by copying over operands (and adding a predicate). This results in two odd things here, the BITCASTs created and passed to `LowerToPredicatedOp` are not used, only the operands of those bitcasts are taken. Secondly, when a shuffle vector node is passed directly to `LowerToPredicatedOp` to create a `REVD_MERGE_PASSTHRU` node an invalid REV node is created as REV only takes one vector operand, but both operands from the shuffle vector are copied to the new REV node. This is not an issue in practice as the extra operand is ignored. These issues were found by the verification added in llvm#140472. Part of llvm#140472. Note: Test changes only result in the vxi64 lowering matching the vxf64 lowering.
MacDue
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1. This patch removes claims of having in/out glue from nodes that are never emitted with glue. 2. Ensures that nodes that _sometimes_ are emitted with glue consistently add it to their type declaration. These issues are not checked now, but were found by the verification added in llvm#140472. Part of llvm#140472.
Member
Author
|
I've split off the following PRs for now (as each are fairly independent): |
MacDue
added a commit
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May 21, 2025
…OP (NFC) (#140711) The conditional variants of SMSTART/STOP currently take the current PStateSM as a variadic value. This is not supported by the verification added in #140472 (which requires variadic values to be of type Register or RegisterMask), so this patch splits the the conditional variants into new `COND_` nodes, where these extra parameters are fixed arguments. Suggested in #140472 (comment) Part of #140472.
MacDue
added a commit
to MacDue/llvm-project
that referenced
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May 21, 2025
1. This patch removes claims of having in/out glue from nodes that are never emitted with glue. 2. Ensures that nodes that _sometimes_ are emitted with glue consistently add it to their type declaration. These issues are not checked now, but were found by the verification added in llvm#140472. Part of llvm#140472.
llvm-sync bot
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to arm/arm-toolchain
that referenced
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May 21, 2025
…:SMSTART/STOP (NFC) (#140711) The conditional variants of SMSTART/STOP currently take the current PStateSM as a variadic value. This is not supported by the verification added in #140472 (which requires variadic values to be of type Register or RegisterMask), so this patch splits the the conditional variants into new `COND_` nodes, where these extra parameters are fixed arguments. Suggested in llvm/llvm-project#140472 (comment) Part of #140472.
MacDue
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MacDue
added a commit
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May 23, 2025
…ings (#140713) The use of `LowerToPredicatedOp` here seems like a mistake as `LowerToPredicatedOp` turns the SDValue passed to it into the desired predicated node by copying over operands (and adding a predicate). This results in two odd things here, the BITCASTs created and passed to `LowerToPredicatedOp` are not used, only the operands of those bitcasts are taken. Secondly, when a shuffle vector node is passed directly to `LowerToPredicatedOp` to create a `REVD_MERGE_PASSTHRU` node an invalid REV node is created as REV only takes one vector operand, but both operands from the shuffle vector are copied to the new REV node. This is not an issue in practice as the extra operand is ignored. These issues were found by the verification added in #140472. Part of #140472. Note: Test changes only result in the vxf64 lowering matching the vxi64 lowering.
MacDue
added a commit
that referenced
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May 24, 2025
…#140715) 1. This patch removes claims of having in/out glue from nodes that are never emitted with glue. 2. Ensures that nodes that _sometimes_ are emitted with glue consistently add it to their type declaration. These issues are not checked now, but were found by the verification added in #140472. Part of #140472.
This also removes some unused SDNodes (rather than add the definitions)
The issues that led to these being disabled have been fixed upstream.
Member
Author
|
Rebased after landing the above patches. |
|
|
||
| #define GET_SDNODE_DESC | ||
| #include "AArch64GenSDNodeInfo.inc" | ||
|
|
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We typically undefined the generation macros straight after the include to avoid accidental uses.
Contributor
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It is undefined by the inc file
Collaborator
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That seems like bad design? because it second guesses the user's intent. I think those who defining it should have the responsibility to undef it.
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Most, if not all, generated headers undefine macros, so I just did the same.
paulwalker-arm
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May 27, 2025
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I agree with @s-barannikov indentation comment, but otherwise this looks good to me.
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/64/builds/3886 Here is the relevant piece of the build log for the reference |
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This is an attempt to continue @s-barannikov's work TableGen-erating SDNode descriptions. This takes the initial patch from #119709 and moves documentation and the rest of the AArch64ISD nodes to TableGen. Some issues were found by the generated SDNode verification added in this patch. These issues have been described and fixed in the following PRs: