From 73e4776b73989d294dda9e265d302d751e68f32e Mon Sep 17 00:00:00 2001 From: Francesco Petrogalli Date: Tue, 20 May 2025 10:19:11 -0700 Subject: [PATCH] [RISCV] Fix schedule info for FMVP_D_X. This binary instruction reads from two input registers. --- llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td index 184473821dfdb..a2737d247fe31 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td @@ -144,7 +144,7 @@ let mayRaiseFPException = 0 in { def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">, Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>; def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">, - Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>; + Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64, ReadFMovI64ToF64]>; } let isCodeGenOnly = 1, mayRaiseFPException = 0 in