diff --git a/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h b/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h index 738f33bf36c9e..9de3a66755778 100644 --- a/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h +++ b/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h @@ -184,19 +184,9 @@ class CIRBaseBuilderTy : public mlir::OpBuilder { global.getSymName()); } - cir::LoadOp createLoad(mlir::Location loc, mlir::Value ptr, - bool isVolatile = false, uint64_t alignment = 0) { - mlir::IntegerAttr intAttr; - if (alignment) - intAttr = mlir::IntegerAttr::get( - mlir::IntegerType::get(ptr.getContext(), 64), alignment); - - return create(loc, ptr); - } - - cir::StoreOp createStore(mlir::Location loc, mlir::Value val, - mlir::Value dst) { - return create(loc, val, dst); + cir::StoreOp createStore(mlir::Location loc, mlir::Value val, mlir::Value dst, + mlir::IntegerAttr align = {}) { + return create(loc, val, dst, align); } cir::GetMemberOp createGetMember(mlir::Location loc, mlir::Type resultTy, @@ -209,7 +199,12 @@ class CIRBaseBuilderTy : public mlir::OpBuilder { clang::CharUnits alignment) { auto addr = createAlloca(loc, getPointerTo(type), type, {}, getSizeFromCharUnits(getContext(), alignment)); - return createLoad(loc, addr); + mlir::IntegerAttr alignAttr; + uint64_t align = alignment.getQuantity(); + if (align) + alignAttr = getI64IntegerAttr(align); + + return create(loc, addr, /*isDeref=*/false, alignAttr); } cir::PtrStrideOp createPtrStride(mlir::Location loc, mlir::Value base, diff --git a/clang/include/clang/CIR/Dialect/IR/CIROps.td b/clang/include/clang/CIR/Dialect/IR/CIROps.td index 8267df92e3187..eaa4c9702137c 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIROps.td +++ b/clang/include/clang/CIR/Dialect/IR/CIROps.td @@ -417,11 +417,15 @@ def LoadOp : CIR_Op<"load", [ }]; let arguments = (ins Arg:$addr, UnitAttr:$isDeref); + [MemRead]>:$addr, + UnitAttr:$isDeref, + OptionalAttr:$alignment + ); let results = (outs CIR_AnyType:$result); let assemblyFormat = [{ (`deref` $isDeref^)? + (`align` `(` $alignment^ `)`)? $addr `:` qualified(type($addr)) `,` type($result) attr-dict }]; @@ -458,9 +462,11 @@ def StoreOp : CIR_Op<"store", [ let arguments = (ins CIR_AnyType:$value, Arg:$addr); + [MemWrite]>:$addr, + OptionalAttr:$alignment); let assemblyFormat = [{ + (`align` `(` $alignment^ `)`)? $value `,` $addr attr-dict `:` type($value) `,` qualified(type($addr)) }]; @@ -1643,7 +1649,8 @@ def GlobalOp : CIR_Op<"global"> { TypeAttr:$sym_type, Arg:$linkage, OptionalAttr:$initial_value, - UnitAttr:$dsolocal); + UnitAttr:$dsolocal, + OptionalAttr:$alignment); let assemblyFormat = [{ $linkage diff --git a/clang/include/clang/CIR/MissingFeatures.h b/clang/include/clang/CIR/MissingFeatures.h index d4952da326ac0..fb205e9cd85d1 100644 --- a/clang/include/clang/CIR/MissingFeatures.h +++ b/clang/include/clang/CIR/MissingFeatures.h @@ -34,11 +34,14 @@ struct MissingFeatures { static bool opGlobalDSOLocal() { return false; } static bool opGlobalThreadLocal() { return false; } static bool opGlobalConstant() { return false; } - static bool opGlobalAlignment() { return false; } static bool opGlobalWeakRef() { return false; } static bool opGlobalLinkage() { return false; } - static bool opGlobalSetVisitibility() { return false; } static bool opGlobalUnnamedAddr() { return false; } + static bool opGlobalSection() { return false; } + static bool opGlobalVisibility() { return false; } + static bool opGlobalDLLImportExport() { return false; } + static bool opGlobalPartition() { return false; } + static bool opGlobalCIRGlobalValueInterface() { return false; } static bool supportIFuncAttr() { return false; } static bool supportVisibility() { return false; } @@ -51,7 +54,6 @@ struct MissingFeatures { static bool opLoadStoreTbaa() { return false; } static bool opLoadStoreMemOrder() { return false; } static bool opLoadStoreVolatile() { return false; } - static bool opLoadStoreAlignment() { return false; } static bool opLoadStoreAtomic() { return false; } static bool opLoadStoreObjC() { return false; } diff --git a/clang/lib/CIR/CodeGen/CIRGenBuilder.h b/clang/lib/CIR/CodeGen/CIRGenBuilder.h index 9c0968f144eef..e53f5e9202961 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuilder.h +++ b/clang/lib/CIR/CodeGen/CIRGenBuilder.h @@ -9,6 +9,7 @@ #ifndef LLVM_CLANG_LIB_CIR_CODEGEN_CIRGENBUILDER_H #define LLVM_CLANG_LIB_CIR_CODEGEN_CIRGENBUILDER_H +#include "Address.h" #include "CIRGenTypeCache.h" #include "clang/CIR/MissingFeatures.h" @@ -279,6 +280,27 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy { return create(loc, cir::BinOpKind::Div, lhs, rhs); } + cir::LoadOp createLoad(mlir::Location loc, Address addr, + bool isVolatile = false) { + mlir::IntegerAttr align; + uint64_t alignment = addr.getAlignment().getQuantity(); + if (alignment) + align = getI64IntegerAttr(alignment); + return create(loc, addr.getPointer(), /*isDeref=*/false, + align); + } + + cir::StoreOp createStore(mlir::Location loc, mlir::Value val, Address dst, + ::mlir::IntegerAttr align = {}) { + if (!align) { + uint64_t alignment = dst.getAlignment().getQuantity(); + if (alignment) + align = mlir::IntegerAttr::get(mlir::IntegerType::get(getContext(), 64), + alignment); + } + return CIRBaseBuilderTy::createStore(loc, val, dst.getPointer(), align); + } + /// Create a cir.ptr_stride operation to get access to an array element. /// \p idx is the index of the element to access, \p shouldDecay is true if /// the result should decay to a pointer to the element type. diff --git a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp index a8fecafe4a1f3..5424c6a8d6f3c 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp @@ -209,10 +209,10 @@ void CIRGenFunction::emitStoreThroughLValue(RValue src, LValue dst, // Read/modify/write the vector, inserting the new element const mlir::Location loc = dst.getVectorPointer().getLoc(); const mlir::Value vector = - builder.createLoad(loc, dst.getVectorAddress().getPointer()); + builder.createLoad(loc, dst.getVectorAddress()); const mlir::Value newVector = builder.create( loc, vector, src.getScalarVal(), dst.getVectorIdx()); - builder.createStore(loc, newVector, dst.getVectorAddress().getPointer()); + builder.createStore(loc, newVector, dst.getVectorAddress()); return; } @@ -301,7 +301,7 @@ void CIRGenFunction::emitStoreOfScalar(mlir::Value value, Address addr, } assert(currSrcLoc && "must pass in source location"); - builder.createStore(*currSrcLoc, value, addr.getPointer() /*, isVolatile*/); + builder.createStore(*currSrcLoc, value, addr /*, isVolatile*/); if (isNontemporal) { cgm.errorNYI(addr.getPointer().getLoc(), "emitStoreOfScalar nontemporal"); @@ -409,12 +409,10 @@ mlir::Value CIRGenFunction::emitLoadOfScalar(LValue lvalue, Address addr = lvalue.getAddress(); mlir::Type eltTy = addr.getElementType(); - mlir::Value ptr = addr.getPointer(); if (mlir::isa(eltTy)) cgm.errorNYI(loc, "emitLoadOfScalar: void type"); - mlir::Value loadOp = builder.CIRBaseBuilderTy::createLoad( - getLoc(loc), ptr, false /*isVolatile*/); + mlir::Value loadOp = builder.createLoad(getLoc(loc), addr); return loadOp; } @@ -431,7 +429,7 @@ RValue CIRGenFunction::emitLoadOfLValue(LValue lv, SourceLocation loc) { if (lv.isVectorElt()) { const mlir::Value load = - builder.createLoad(getLoc(loc), lv.getVectorAddress().getPointer()); + builder.createLoad(getLoc(loc), lv.getVectorAddress()); return RValue::get(builder.create(getLoc(loc), load, lv.getVectorIdx())); } @@ -745,11 +743,12 @@ CIRGenFunction::emitArraySubscriptExpr(const clang::ArraySubscriptExpr *e) { LValue CIRGenFunction::emitStringLiteralLValue(const StringLiteral *e) { cir::GlobalOp globalOp = cgm.getGlobalForStringLiteral(e); - assert(!cir::MissingFeatures::opGlobalAlignment()); + assert(globalOp.getAlignment() && "expected alignment for string literal"); + unsigned align = *(globalOp.getAlignment()); mlir::Value addr = builder.createGetGlobal(getLoc(e->getSourceRange()), globalOp); return makeAddrLValue( - Address(addr, globalOp.getSymType(), CharUnits::fromQuantity(1)), + Address(addr, globalOp.getSymType(), CharUnits::fromQuantity(align)), e->getType(), AlignmentSource::Decl); } diff --git a/clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp b/clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp index e006a77c6e7d6..b375bcf2f483f 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp @@ -162,8 +162,7 @@ void AggExprEmitter::emitArrayInit(Address destPtr, cir::ArrayType arrayTy, // TODO(CIR): Replace this part later with cir::DoWhileOp for (unsigned i = numInitElements; i != numArrayElements; ++i) { - cir::LoadOp currentElement = - builder.createLoad(loc, tmpAddr.getPointer()); + cir::LoadOp currentElement = builder.createLoad(loc, tmpAddr); // Emit the actual filler expression. const LValue elementLV = cgf.makeAddrLValue( diff --git a/clang/lib/CIR/CodeGen/CIRGenFunction.cpp b/clang/lib/CIR/CodeGen/CIRGenFunction.cpp index ce88e656a38e8..4335214d77b7d 100644 --- a/clang/lib/CIR/CodeGen/CIRGenFunction.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenFunction.cpp @@ -607,7 +607,7 @@ void CIRGenFunction::emitNullInitialization(mlir::Location loc, Address destPtr, // respective address. // Builder.CreateMemSet(DestPtr, Builder.getInt8(0), SizeVal, false); const mlir::Value zeroValue = builder.getNullValue(convertType(ty), loc); - builder.createStore(loc, zeroValue, destPtr.getPointer()); + builder.createStore(loc, zeroValue, destPtr); } } // namespace clang::CIRGen diff --git a/clang/lib/CIR/CodeGen/CIRGenModule.cpp b/clang/lib/CIR/CodeGen/CIRGenModule.cpp index fba8c07b6860d..60a3048f548e8 100644 --- a/clang/lib/CIR/CodeGen/CIRGenModule.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenModule.cpp @@ -366,6 +366,39 @@ CIRGenModule::getOrCreateCIRGlobal(StringRef mangledName, mlir::Type ty, CIRGenModule::createGlobalOp(*this, loc, mangledName, ty, /*insertPoint=*/entry.getOperation()); + // Handle things which are present even on external declarations. + if (d) { + if (langOpts.OpenMP && !langOpts.OpenMPSimd) + errorNYI(d->getSourceRange(), "OpenMP target global variable"); + + gv.setAlignmentAttr(getSize(astContext.getDeclAlign(d))); + assert(!cir::MissingFeatures::opGlobalConstant()); + assert(!cir::MissingFeatures::opGlobalLinkage()); + + if (d->getTLSKind()) + errorNYI(d->getSourceRange(), "thread local global variable"); + + assert(!cir::MissingFeatures::opGlobalDLLImportExport()); + assert(!cir::MissingFeatures::opGlobalPartition()); + assert(!cir::MissingFeatures::setDSOLocal()); + + // If required by the ABI, treat declarations of static data members with + // inline initializers as definitions. + if (astContext.isMSStaticDataMemberInlineDefinition(d)) + errorNYI(d->getSourceRange(), "MS static data member inline definition"); + + assert(!cir::MissingFeatures::opGlobalSection()); + assert(!cir::MissingFeatures::opGlobalVisibility()); + + // Handle XCore specific ABI requirements. + if (getTriple().getArch() == llvm::Triple::xcore) + errorNYI(d->getSourceRange(), "XCore specific ABI requirements"); + + // We need to check for external const declarations with initializers here, + // but the 'isPublic()' part of the check uses the CIRGlobalValueInterface. + assert(!cir::MissingFeatures::opGlobalCIRGlobalValueInterface()); + } + return gv; } @@ -775,7 +808,8 @@ CIRGenModule::getCIRLinkageVarDefinition(const VarDecl *vd, bool isConstant) { static cir::GlobalOp generateStringLiteral(mlir::Location loc, mlir::TypedAttr c, CIRGenModule &cgm, - StringRef globalName) { + StringRef globalName, + CharUnits alignment) { assert(!cir::MissingFeatures::addressSpace()); // Create a global variable for this string @@ -784,7 +818,7 @@ static cir::GlobalOp generateStringLiteral(mlir::Location loc, CIRGenModule::createGlobalOp(cgm, loc, globalName, c.getType()); // Set up extra information and add to the module - assert(!cir::MissingFeatures::opGlobalAlignment()); + gv.setAlignmentAttr(cgm.getSize(alignment)); assert(!cir::MissingFeatures::opGlobalLinkage()); assert(!cir::MissingFeatures::opGlobalThreadLocal()); assert(!cir::MissingFeatures::opGlobalUnnamedAddr()); @@ -821,6 +855,9 @@ std::string CIRGenModule::getUniqueGlobalName(const std::string &baseName) { /// Return a pointer to a constant array for the given string literal. cir::GlobalOp CIRGenModule::getGlobalForStringLiteral(const StringLiteral *s, StringRef name) { + CharUnits alignment = + astContext.getAlignOfGlobalVarInChars(s->getType(), /*VD=*/nullptr); + mlir::Attribute c = getConstantArrayFromStringLiteral(s); if (getLangOpts().WritableStrings) { @@ -842,8 +879,8 @@ cir::GlobalOp CIRGenModule::getGlobalForStringLiteral(const StringLiteral *s, std::string uniqueName = getUniqueGlobalName(name.str()); mlir::Location loc = getLoc(s->getSourceRange()); auto typedC = llvm::cast(c); - assert(!cir::MissingFeatures::opGlobalAlignment()); - cir::GlobalOp gv = generateStringLiteral(loc, typedC, *this, uniqueName); + cir::GlobalOp gv = + generateStringLiteral(loc, typedC, *this, uniqueName, alignment); assert(!cir::MissingFeatures::opGlobalDSOLocal()); assert(!cir::MissingFeatures::sanitizers()); @@ -918,7 +955,7 @@ void CIRGenModule::emitTopLevelDecl(Decl *decl) { void CIRGenModule::setInitializer(cir::GlobalOp &op, mlir::Attribute value) { // Recompute visibility when updating initializer. op.setInitialValueAttr(value); - assert(!cir::MissingFeatures::opGlobalSetVisitibility()); + assert(!cir::MissingFeatures::opGlobalVisibility()); } cir::FuncOp CIRGenModule::getAddrOfFunction(clang::GlobalDecl gd, diff --git a/clang/lib/CIR/CodeGen/CIRGenStmt.cpp b/clang/lib/CIR/CodeGen/CIRGenStmt.cpp index 763d2b087cc85..019a44636ce3c 100644 --- a/clang/lib/CIR/CodeGen/CIRGenStmt.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenStmt.cpp @@ -391,7 +391,8 @@ mlir::LogicalResult CIRGenFunction::emitReturnStmt(const ReturnStmt &s) { // If this function returns a reference, take the address of the // expression rather than the value. RValue result = emitReferenceBindingToExpr(rv); - builder.createStore(loc, result.getScalarVal(), *fnRetAlloca); + builder.CIRBaseBuilderTy::createStore(loc, result.getScalarVal(), + *fnRetAlloca); } else { mlir::Value value = nullptr; switch (CIRGenFunction::getEvaluationKind(rv->getType())) { diff --git a/clang/lib/CIR/Dialect/IR/CIRTypes.cpp b/clang/lib/CIR/Dialect/IR/CIRTypes.cpp index 479d249516699..b402177a5ec18 100644 --- a/clang/lib/CIR/Dialect/IR/CIRTypes.cpp +++ b/clang/lib/CIR/Dialect/IR/CIRTypes.cpp @@ -353,6 +353,12 @@ uint64_t RecordType::getElementOffset(const ::mlir::DataLayout &dataLayout, offset += dataLayout.getTypeSize(ty); } + // Account for padding, if necessary, for the alignment of the field whose + // offset we are calculating. + const llvm::Align tyAlign = llvm::Align( + getPacked() ? 1 : dataLayout.getTypeABIAlignment(members[idx])); + offset = llvm::alignTo(offset, tyAlign); + return offset; } diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp index 3d86f3d4deffb..fbc1ec735a216 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp +++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp @@ -728,8 +728,9 @@ mlir::LogicalResult CIRToLLVMLoadOpLowering::matchAndRewrite( const mlir::Type llvmTy = convertTypeForMemory( *getTypeConverter(), dataLayout, op.getResult().getType()); assert(!cir::MissingFeatures::opLoadStoreMemOrder()); - assert(!cir::MissingFeatures::opLoadStoreAlignment()); - unsigned alignment = (unsigned)dataLayout.getTypeABIAlignment(llvmTy); + std::optional opAlign = op.getAlignment(); + unsigned alignment = + (unsigned)opAlign.value_or(dataLayout.getTypeABIAlignment(llvmTy)); assert(!cir::MissingFeatures::lowerModeOptLevel()); @@ -753,10 +754,11 @@ mlir::LogicalResult CIRToLLVMStoreOpLowering::matchAndRewrite( cir::StoreOp op, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const { assert(!cir::MissingFeatures::opLoadStoreMemOrder()); - assert(!cir::MissingFeatures::opLoadStoreAlignment()); const mlir::Type llvmTy = getTypeConverter()->convertType(op.getValue().getType()); - unsigned alignment = (unsigned)dataLayout.getTypeABIAlignment(llvmTy); + std::optional opAlign = op.getAlignment(); + unsigned alignment = + (unsigned)opAlign.value_or(dataLayout.getTypeABIAlignment(llvmTy)); assert(!cir::MissingFeatures::lowerModeOptLevel()); @@ -968,8 +970,7 @@ void CIRToLLVMGlobalOpLowering::setupRegionInitializedLLVMGlobalOp( const bool isDsoLocal = true; assert(!cir::MissingFeatures::opGlobalThreadLocal()); const bool isThreadLocal = false; - assert(!cir::MissingFeatures::opGlobalAlignment()); - const uint64_t alignment = 0; + const uint64_t alignment = op.getAlignment().value_or(0); const mlir::LLVM::Linkage linkage = convertLinkage(op.getLinkage()); const StringRef symbol = op.getSymName(); @@ -1024,8 +1025,7 @@ mlir::LogicalResult CIRToLLVMGlobalOpLowering::matchAndRewrite( const bool isDsoLocal = true; assert(!cir::MissingFeatures::opGlobalThreadLocal()); const bool isThreadLocal = false; - assert(!cir::MissingFeatures::opGlobalAlignment()); - const uint64_t alignment = 0; + const uint64_t alignment = op.getAlignment().value_or(0); const mlir::LLVM::Linkage linkage = convertLinkage(op.getLinkage()); const StringRef symbol = op.getSymName(); SmallVector attributes; diff --git a/clang/test/CIR/CodeGen/align-load.c b/clang/test/CIR/CodeGen/align-load.c new file mode 100644 index 0000000000000..06553a307f93a --- /dev/null +++ b/clang/test/CIR/CodeGen/align-load.c @@ -0,0 +1,96 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-llvm %s -o %t-cir.ll +// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG + +struct S { + char b; + short s; + int i; + float f; + double d; +}; + +void accessStruct(struct S u) { + u.b; + u.s; + u.i; + u.f; + u.d; +} + +// CIR: cir.func @accessStruct +// CIR: cir.load align(8) +// CIR: cir.load align(2) +// CIR: cir.load align(4) +// CIR: cir.load align(8) +// CIR: cir.load align(8) + +// LLVM: define{{.*}} @accessStruct +// LLVM: load i8, ptr {{.*}}, align 8 +// LLVM: load i16, ptr {{.*}}, align 2 +// LLVM: load i32, ptr {{.*}}, align 4 +// LLVM: load float, ptr {{.*}}, align 8 +// LLVM: load double, ptr {{.*}}, align 8 + +// OGCG: define{{.*}} @accessStruct +// OGCG: load i8, ptr {{.*}}, align 8 +// OGCG: load i16, ptr {{.*}}, align 2 +// OGCG: load i32, ptr {{.*}}, align 4 +// OGCG: load float, ptr {{.*}}, align 8 +// OGCG: load double, ptr {{.*}}, align 8 + +union U { + char b; + short s; + int i; + float f; + double d; +}; + +void accessUnion(union U u) { + u.b; + u.s; + u.i; + u.f; + u.d; +} + +// CIR: cir.func @accessUnion +// CIR: cir.load align(8) +// CIR: cir.load align(8) +// CIR: cir.load align(8) +// CIR: cir.load align(8) +// CIR: cir.load align(8) + +// LLVM: define{{.*}} @accessUnion +// LLVM: load i8, ptr {{.*}}, align 8 +// LLVM: load i16, ptr {{.*}}, align 8 +// LLVM: load i32, ptr {{.*}}, align 8 +// LLVM: load float, ptr {{.*}}, align 8 +// LLVM: load double, ptr {{.*}}, align 8 + +// OGCG: define{{.*}} @accessUnion +// OGCG: load i8, ptr {{.*}}, align 8 +// OGCG: load i16, ptr {{.*}}, align 8 +// OGCG: load i32, ptr {{.*}}, align 8 +// OGCG: load float, ptr {{.*}}, align 8 +// OGCG: load double, ptr {{.*}}, align 8 + +// PR5279 - Reduced alignment on typedef. +typedef int myint __attribute__((aligned(1))); + +int loadAligned(myint *p) { + return *p; +} + +// CIR: cir.func @loadAligned +// CIR: cir.load align(1) + +// LLVM: @loadAligned +// LLVM: load i32, ptr {{.*}}, align 1 + +// OGCG: @loadAligned +// OGCG: load i32, ptr {{.*}}, align 1 diff --git a/clang/test/CIR/CodeGen/align-store.c b/clang/test/CIR/CodeGen/align-store.c new file mode 100644 index 0000000000000..9ce26fa020eeb --- /dev/null +++ b/clang/test/CIR/CodeGen/align-store.c @@ -0,0 +1,94 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-llvm %s -o %t-cir.ll +// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG + +// PR5279 - Reduced alignment on typedef. +typedef int myint __attribute__((aligned(1))); + +void test1(myint *p) { + *p = 0; +} + +// CIR: cir.func @test1 +// CIR: cir.store align(1) + +// LLVM: @test1 +// LLVM: store i32 0, ptr {{.*}}, align 1 +// LLVM: ret void + +// OGCG: @test1 +// OGCG: store i32 0, ptr {{.*}}, align 1 +// OGCG: ret void + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +typedef struct +{ + uint16_t i16; + uint32_t i32; + uint16_t i16_2; + uint32_t i32_2; +} StructA; + +void test2(StructA* p) { + p->i16 = 1; + p->i32 = 2; + p->i16_2 = 3; + p->i32_2 = 4; +} + +// CIR-LABEL: @test2 +// CIR: cir.store align(4) %{{.*}}, %{{.*}} : !u16i, !cir.ptr +// CIR: cir.store align(4) %{{.*}}, %{{.*}} : !u32i, !cir.ptr +// CIR: cir.store align(4) %{{.*}}, %{{.*}} : !u16i, !cir.ptr +// CIR: cir.store align(4) %{{.*}}, %{{.*}} : !u32i, !cir.ptr + +// LLVM: @test2 +// LLVM: store i16 1, ptr {{.*}}, align 4 +// LLVM: store i32 2, ptr {{.*}}, align 4 +// LLVM: store i16 3, ptr {{.*}}, align 4 +// LLVM: store i32 4, ptr {{.*}}, align 4 + +// OGCG: @test2 +// OGCG: store i16 1, ptr {{.*}}, align 4 +// OGCG: store i32 2, ptr {{.*}}, align 4 +// OGCG: store i16 3, ptr {{.*}}, align 4 +// OGCG: store i32 4, ptr {{.*}}, align 4 + +typedef struct { + short a; + short b; + short c; + short d; + long e; // Make the struct 8-byte aligned +} StructB; + +void test3(StructB *ptr) { + ptr->a = 1; // align 8 + ptr->b = 2; // align 2 + ptr->c = 3; // align 4 + ptr->d = 4; // align 2 +} + +// CIR-LABEL: @test3 +// CIR: cir.store align(8) %{{.*}}, %{{.*}} : !s16i, !cir.ptr +// CIR: cir.store align(2) %{{.*}}, %{{.*}} : !s16i, !cir.ptr +// CIR: cir.store align(4) %{{.*}}, %{{.*}} : !s16i, !cir.ptr +// CIR: cir.store align(2) %{{.*}}, %{{.*}} : !s16i, !cir.ptr + +// LLVM: @test3 +// LLVM: store i16 1, ptr {{.*}}, align 8 +// LLVM: store i16 2, ptr {{.*}}, align 2 +// LLVM: store i16 3, ptr {{.*}}, align 4 +// LLVM: store i16 4, ptr {{.*}}, align 2 + +// OGCG: @test3 +// OGCG: store i16 1, ptr {{.*}}, align 8 +// OGCG: store i16 2, ptr {{.*}}, align 2 +// OGCG: store i16 3, ptr {{.*}}, align 4 +// OGCG: store i16 4, ptr {{.*}}, align 2 diff --git a/clang/test/CIR/CodeGen/alignment.c b/clang/test/CIR/CodeGen/alignment.c new file mode 100644 index 0000000000000..25acb6a0f570d --- /dev/null +++ b/clang/test/CIR/CodeGen/alignment.c @@ -0,0 +1,26 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-llvm %s -o %t-cir.ll +// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG + +__attribute((aligned(32))) float a[128]; +union {int a[4]; __attribute((aligned(32))) float b[4];} b; + +// CIR: @a = #cir.zero {{.*}}alignment = 32 +// CIR: @b = #cir.zero{{.*}}alignment = 32 + +// LLVM: @a = {{.*}}zeroinitializer, align 32 +// LLVM: @b = {{.*}}zeroinitializer, align 32 + +// OGCG: @a = {{.*}}zeroinitializer, align 32 +// OGCG: @b = {{.*}}zeroinitializer, align 32 + +long long int test5[1024]; +// CIR: @test5 = #cir.zero {{.*}}alignment = 16 +// LLVM: @test5 = {{.*}}global [1024 x i64] zeroinitializer, align 16 +// OGCG: @test5 = {{.*}}global [1024 x i64] zeroinitializer, align 16 + +// TODO: Add more test cases from clang/test/CodeGen/alignment.c when we have +// implemented compound literal expression support. diff --git a/clang/test/CIR/CodeGen/array.cpp b/clang/test/CIR/CodeGen/array.cpp index cae970aedf95d..a4b9398df3b1a 100644 --- a/clang/test/CIR/CodeGen/array.cpp +++ b/clang/test/CIR/CodeGen/array.cpp @@ -85,12 +85,12 @@ void func() { // CIR: %[[IDX:.*]] = cir.const #cir.int<0> : !s32i // CIR: %[[ARR_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR]] : !cir.ptr>), !cir.ptr // CIR: %[[ELE_PTR:.*]] = cir.ptr_stride(%[[ARR_PTR]] : !cir.ptr, %[[IDX]] : !s32i), !cir.ptr -// CIR: %[[TMP:.*]] = cir.load %[[ELE_PTR]] : !cir.ptr, !s32i +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[ELE_PTR]] : !cir.ptr, !s32i // CIR" cir.store %[[TMP]], %[[INIT]] : !s32i, !cir.ptr // CIR: %[[IDX:.*]] = cir.const #cir.int<1> : !s32i // CIR: %[[ARR_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR]] : !cir.ptr>), !cir.ptr // CIR: %[[ELE_PTR:.*]] = cir.ptr_stride(%[[ARR_PTR]] : !cir.ptr, %[[IDX]] : !s32i), !cir.ptr -// CIR: %[[TMP:.*]] = cir.load %[[ELE_PTR]] : !cir.ptr, !s32i +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[ELE_PTR]] : !cir.ptr, !s32i // CIR" cir.store %[[TMP]], %[[INIT_2]] : !s32i, !cir.ptr // LLVM: define void @_Z4funcv() @@ -99,7 +99,7 @@ void func() { // LLVM-NEXT: %[[INIT_2:.*]] = alloca i32, i64 1, align 4 // LLVM-NEXT: %[[ARR_PTR:.*]] = getelementptr i32, ptr %[[ARR]], i32 0 // LLVM-NEXT: %[[ELE_PTR:.*]] = getelementptr i32, ptr %[[ARR_PTR]], i64 0 -// LLVM-NEXT: %[[TMP_1:.*]] = load i32, ptr %[[ELE_PTR]], align 4 +// LLVM-NEXT: %[[TMP_1:.*]] = load i32, ptr %[[ELE_PTR]], align 16 // LLVM-NEXT: store i32 %[[TMP_1]], ptr %[[INIT]], align 4 // LLVM-NEXT: %[[ARR_PTR:.*]] = getelementptr i32, ptr %[[ARR]], i32 0 // LLVM-NEXT: %[[ELE_PTR:.*]] = getelementptr i32, ptr %[[ARR_PTR]], i64 1 @@ -124,16 +124,16 @@ void func2() { // CIR: %[[ELE_ALLOCA:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["arrayinit.temp", init] // CIR: %[[ARR_2_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR2]] : !cir.ptr>), !cir.ptr // CIR: %[[V1:.*]] = cir.const #cir.int<5> : !s32i -// CIR: cir.store %[[V1]], %[[ARR_2_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[V1]], %[[ARR_2_PTR]] : !s32i, !cir.ptr // CIR: %[[OFFSET_0:.*]] = cir.const #cir.int<1> : !s64i // CIR: %[[ELE_PTR:.*]] = cir.ptr_stride(%[[ARR_2_PTR]] : !cir.ptr, %[[OFFSET_0]] : !s64i), !cir.ptr -// CIR: cir.store %[[ELE_PTR]], %[[ELE_ALLOCA]] : !cir.ptr, !cir.ptr> -// CIR: %[[LOAD_1:.*]] = cir.load %[[ELE_ALLOCA]] : !cir.ptr>, !cir.ptr +// CIR: cir.store{{.*}} %[[ELE_PTR]], %[[ELE_ALLOCA]] : !cir.ptr, !cir.ptr> +// CIR: %[[LOAD_1:.*]] = cir.load{{.*}} %[[ELE_ALLOCA]] : !cir.ptr>, !cir.ptr // CIR: %[[V2:.*]] = cir.const #cir.int<0> : !s32i -// CIR: cir.store %[[V2]], %[[LOAD_1]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[V2]], %[[LOAD_1]] : !s32i, !cir.ptr // CIR: %[[OFFSET_1:.*]] = cir.const #cir.int<1> : !s64i // CIR: %[[ELE_1_PTR:.*]] = cir.ptr_stride(%[[LOAD_1]] : !cir.ptr, %[[OFFSET_1]] : !s64i), !cir.ptr -// CIR: cir.store %[[ELE_1_PTR]], %[[ELE_ALLOCA]] : !cir.ptr, !cir.ptr> +// CIR: cir.store{{.*}} %[[ELE_1_PTR]], %[[ELE_ALLOCA]] : !cir.ptr, !cir.ptr> // LLVM: define void @_Z5func2v() // LLVM: %[[ARR:.*]] = alloca [2 x i32], i64 1, align 4 @@ -162,18 +162,18 @@ void func3() { // CIR: %[[INIT:.*]] = cir.alloca !s32i, !cir.ptr, ["e", init] // CIR: %[[ARR_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR]] : !cir.ptr>), !cir.ptr // CIR: %[[V0:.*]] = cir.const #cir.int<5> : !s32i -// CIR: cir.store %[[V0]], %[[ARR_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[V0]], %[[ARR_PTR]] : !s32i, !cir.ptr // CIR: %[[OFFSET_0:.*]] = cir.const #cir.int<1> : !s64i // CIR: %[[ELE_1_PTR:.*]] = cir.ptr_stride(%[[ARR_PTR]] : !cir.ptr, %[[OFFSET_0]] : !s64i), !cir.ptr // CIR: %[[V1:.*]] = cir.const #cir.int<6> : !s32i -// CIR: cir.store %[[V1]], %[[ELE_1_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[V1]], %[[ELE_1_PTR]] : !s32i, !cir.ptr // CIR: %[[IDX_V:.*]] = cir.const #cir.int<1> : !s32i -// CIR: cir.store %[[IDX_V]], %[[IDX]] : !s32i, !cir.ptr -// CIR: %[[TMP_IDX:.*]] = cir.load %[[IDX]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[IDX_V]], %[[IDX]] : !s32i, !cir.ptr +// CIR: %[[TMP_IDX:.*]] = cir.load{{.*}} %[[IDX]] : !cir.ptr, !s32i // CIR: %[[ARR_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR]] : !cir.ptr>), !cir.ptr // CIR: %[[ELE_PTR:.*]] = cir.ptr_stride(%[[ARR_PTR]] : !cir.ptr, %[[TMP_IDX]] : !s32i), !cir.ptr -// CIR: %[[ELE_TMP:.*]] = cir.load %[[ELE_PTR]] : !cir.ptr, !s32i -// CIR: cir.store %[[ELE_TMP]], %[[INIT]] : !s32i, !cir.ptr +// CIR: %[[ELE_TMP:.*]] = cir.load{{.*}} %[[ELE_PTR]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[ELE_TMP]], %[[INIT]] : !s32i, !cir.ptr // LLVM: define void @_Z5func3v() // LLVM: %[[ARR:.*]] = alloca [2 x i32], i64 1, align 4 @@ -212,20 +212,20 @@ void func4() { // CIR: %[[ARR_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR]] : !cir.ptr x 2>>), !cir.ptr> // CIR: %[[ARR_0_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR_PTR]] : !cir.ptr>), !cir.ptr // CIR: %[[V_0_0:.*]] = cir.const #cir.int<5> : !s32i -// CIR: cir.store %[[V_0_0]], %[[ARR_0_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[V_0_0]], %[[ARR_0_PTR]] : !s32i, !cir.ptr // CIR: %[[OFFSET:.*]] = cir.const #cir.int<1> : !s64i // CIR: %[[ARR_1:.*]] = cir.ptr_stride(%[[ARR_PTR]] : !cir.ptr>, %[[OFFSET]] : !s64i), !cir.ptr> // CIR: %[[ARR_1_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR_1]] : !cir.ptr>), !cir.ptr // CIR: %[[V_1_0:.*]] = cir.const #cir.int<6> : !s32i -// CIR: cir.store %[[V_1_0]], %[[ARR_1_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[V_1_0]], %[[ARR_1_PTR]] : !s32i, !cir.ptr // CIR: %[[IDX:.*]] = cir.const #cir.int<0> : !s32i // CIR: %[[IDX_1:.*]] = cir.const #cir.int<1> : !s32i // CIR: %[[ARR_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR]] : !cir.ptr x 2>>), !cir.ptr> // CIR: %[[ARR_1:.*]] = cir.ptr_stride(%[[ARR_PTR]] : !cir.ptr>, %[[IDX_1]] : !s32i), !cir.ptr> // CIR: %[[ARR_1_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR_1]] : !cir.ptr>), !cir.ptr // CIR: %[[ELE_0:.*]] = cir.ptr_stride(%[[ARR_1_PTR]] : !cir.ptr, %[[IDX]] : !s32i), !cir.ptr -// CIR: %[[TMP:.*]] = cir.load %[[ELE_0]] : !cir.ptr, !s32i -// CIR: cir.store %[[TMP]], %[[INIT]] : !s32i, !cir.ptr +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[ELE_0]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[TMP]], %[[INIT]] : !s32i, !cir.ptr // LLVM: define void @_Z5func4v() // LLVM: %[[ARR:.*]] = alloca [2 x [1 x i32]], i64 1, align 4 @@ -260,16 +260,16 @@ void func5() { // CIR: %[[ARR_0:.*]] = cir.cast(array_to_ptrdecay, %0 : !cir.ptr x 2>>), !cir.ptr> // CIR: %[[ARR_0_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR_0]] : !cir.ptr>), !cir.ptr // CIR: %[[V_0_0:.*]] = cir.const #cir.int<5> : !s32i -// CIR: cir.store %[[V_0_0]], %[[ARR_0_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[V_0_0]], %[[ARR_0_PTR]] : !s32i, !cir.ptr // CIR: %[[OFFSET:.*]] = cir.const #cir.int<1> : !s64i // CIR: %6 = cir.ptr_stride(%[[ARR_0]] : !cir.ptr>, %[[OFFSET]] : !s64i), !cir.ptr> -// CIR: cir.store %6, %[[ARR_PTR]] : !cir.ptr>, !cir.ptr>> -// CIR: %7 = cir.load %[[ARR_PTR]] : !cir.ptr>>, !cir.ptr> +// CIR: cir.store{{.*}} %6, %[[ARR_PTR]] : !cir.ptr>, !cir.ptr>> +// CIR: %7 = cir.load{{.*}} %[[ARR_PTR]] : !cir.ptr>>, !cir.ptr> // CIR: %8 = cir.const #cir.zero : !cir.array -// CIR: cir.store %8, %7 : !cir.array, !cir.ptr> +// CIR: cir.store{{.*}} %8, %7 : !cir.array, !cir.ptr> // CIR: %[[OFFSET_1:.*]] = cir.const #cir.int<1> : !s64i // CIR: %10 = cir.ptr_stride(%7 : !cir.ptr>, %[[OFFSET_1]] : !s64i), !cir.ptr> -// CIR: cir.store %10, %[[ARR_PTR]] : !cir.ptr>, !cir.ptr>> +// CIR: cir.store{{.*}} %10, %[[ARR_PTR]] : !cir.ptr>, !cir.ptr>> // LLVM: define void @_Z5func5v() // LLVM: %[[ARR:.*]] = alloca [2 x [1 x i32]], i64 1, align 4 @@ -295,14 +295,14 @@ void func6() { // CIR: %[[VAR:.*]] = cir.alloca !s32i, !cir.ptr, ["x", init] // CIR: %[[ARR:.*]] = cir.alloca !cir.array, !cir.ptr>, ["arr", init] // CIR: %[[V:.*]] = cir.const #cir.int<4> : !s32i -// CIR: cir.store %[[V]], %[[VAR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[V]], %[[VAR]] : !s32i, !cir.ptr // CIR: %[[ARR_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR]] : !cir.ptr>), !cir.ptr -// CIR: %[[TMP:.*]] = cir.load %[[VAR]] : !cir.ptr, !s32i -// CIR: cir.store %[[TMP]], %[[ARR_PTR]] : !s32i, !cir.ptr +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[VAR]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[TMP]], %[[ARR_PTR]] : !s32i, !cir.ptr // CIR: %[[OFFSET:.*]] = cir.const #cir.int<1> : !s64i // CIR: %[[ELE_PTR:.*]] = cir.ptr_stride(%[[ARR_PTR]] : !cir.ptr, %[[OFFSET]] : !s64i), !cir.ptr // CIR: %[[V1:.*]] = cir.const #cir.int<5> : !s32i -// CIR: cir.store %[[V1]], %[[ELE_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[V1]], %[[ELE_PTR]] : !s32i, !cir.ptr // LLVM: define void @_Z5func6v() // LLVM: %[[VAR:.*]] = alloca i32, i64 1, align 4 @@ -329,13 +329,13 @@ void func7() { // CIR: %[[ARR:.*]] = cir.alloca !cir.array x 1>, !cir.ptr x 1>>, ["arr", init] // CIR: %[[ARR_TMP:.*]] = cir.alloca !cir.ptr>, !cir.ptr>>, ["arrayinit.temp", init] // CIR: %[[ARR_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR]] : !cir.ptr x 1>>), !cir.ptr> -// CIR: cir.store %[[ARR_PTR]], %[[ARR_TMP]] : !cir.ptr>, !cir.ptr>> -// CIR: %[[TMP:.*]] = cir.load %[[ARR_TMP]] : !cir.ptr>>, !cir.ptr> +// CIR: cir.store{{.*}} %[[ARR_PTR]], %[[ARR_TMP]] : !cir.ptr>, !cir.ptr>> +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[ARR_TMP]] : !cir.ptr>>, !cir.ptr> // CIR: %[[NULL_PTR:.*]] = cir.const #cir.ptr : !cir.ptr -// CIR: cir.store %[[NULL_PTR]], %[[TMP]] : !cir.ptr, !cir.ptr> +// CIR: cir.store{{.*}} %[[NULL_PTR]], %[[TMP]] : !cir.ptr, !cir.ptr> // CIR: %[[OFFSET:.*]] = cir.const #cir.int<1> : !s64i // CIR: %[[ELE_PTR:.*]] = cir.ptr_stride(%[[TMP]] : !cir.ptr>, %[[OFFSET]] : !s64i), !cir.ptr> -// CIR: cir.store %[[ELE_PTR]], %[[ARR_TMP]] : !cir.ptr>, !cir.ptr>> +// CIR: cir.store{{.*}} %[[ELE_PTR]], %[[ARR_TMP]] : !cir.ptr>, !cir.ptr>> // LLVM: define void @_Z5func7v() // LLVM: %[[ARR:.*]] = alloca [1 x ptr], i64 1, align 8 @@ -359,17 +359,17 @@ void func8(int arr[10]) { // CIR: %[[ARR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["arr", init] // CIR: %[[INIT:.*]] = cir.alloca !s32i, !cir.ptr, ["e", init] // CIR: %[[INIT_2:.*]] = cir.alloca !s32i, !cir.ptr, ["e2", init] -// CIR: cir.store %[[ARG]], %[[ARR]] : !cir.ptr, !cir.ptr> +// CIR: cir.store{{.*}} %[[ARG]], %[[ARR]] : !cir.ptr, !cir.ptr> // CIR: %[[IDX:.*]] = cir.const #cir.int<0> : !s32i -// CIR: %[[TMP_1:.*]] = cir.load %[[ARR]] : !cir.ptr>, !cir.ptr +// CIR: %[[TMP_1:.*]] = cir.load{{.*}} %[[ARR]] : !cir.ptr>, !cir.ptr // CIR: %[[ELE_0:.*]] = cir.ptr_stride(%[[TMP_1]] : !cir.ptr, %[[IDX]] : !s32i), !cir.ptr -// CIR: %[[TMP_2:.*]] = cir.load %[[ELE_0]] : !cir.ptr, !s32i -// CIR: cir.store %[[TMP_2]], %[[INIT]] : !s32i, !cir.ptr +// CIR: %[[TMP_2:.*]] = cir.load{{.*}} %[[ELE_0]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[TMP_2]], %[[INIT]] : !s32i, !cir.ptr // CIR: %[[IDX_1:.*]] = cir.const #cir.int<1> : !s32i -// CIR: %[[TMP_3:.*]] = cir.load %[[ARR]] : !cir.ptr>, !cir.ptr +// CIR: %[[TMP_3:.*]] = cir.load{{.*}} %[[ARR]] : !cir.ptr>, !cir.ptr // CIR: %[[ELE_1:.*]] = cir.ptr_stride(%[[TMP_3]] : !cir.ptr, %[[IDX_1]] : !s32i), !cir.ptr -// CIR: %[[TMP_4:.*]] = cir.load %[[ELE_1]] : !cir.ptr, !s32i -// CIR: cir.store %[[TMP_4]], %[[INIT_2]] : !s32i, !cir.ptr +// CIR: %[[TMP_4:.*]] = cir.load{{.*}} %[[ELE_1]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[TMP_4]], %[[INIT_2]] : !s32i, !cir.ptr // LLVM: define void @_Z5func8Pi(ptr %[[ARG:.*]]) // LLVM: %[[ARR:.*]] = alloca ptr, i64 1, align 8 @@ -405,15 +405,15 @@ void func9(int arr[10][5]) { // CIR: cir.func @_Z5func9PA5_i(%[[ARG:.*]]: !cir.ptr> // CIR: %[[ARR:.*]] = cir.alloca !cir.ptr>, !cir.ptr>>, ["arr", init] // CIR: %[[INIT:.*]] = cir.alloca !s32i, !cir.ptr, ["e", init] -// CIR: cir.store %[[ARG]], %[[ARR]] : !cir.ptr>, !cir.ptr>> +// CIR: cir.store{{.*}} %[[ARG]], %[[ARR]] : !cir.ptr>, !cir.ptr>> // CIR: %[[IDX:.*]] = cir.const #cir.int<2> : !s32i // CIR: %[[IDX_1:.*]] = cir.const #cir.int<1> : !s32i -// CIR: %[[TMP_1:.*]] = cir.load %[[ARR]] : !cir.ptr>>, !cir.ptr> +// CIR: %[[TMP_1:.*]] = cir.load{{.*}} %[[ARR]] : !cir.ptr>>, !cir.ptr> // CIR: %[[ARR_1:.*]] = cir.ptr_stride(%[[TMP_1]] : !cir.ptr>, %[[IDX_1]] : !s32i), !cir.ptr> // CIR: %[[ARR_1_PTR:.*]] = cir.cast(array_to_ptrdecay, %[[ARR_1]] : !cir.ptr>), !cir.ptr // CIR: %[[ARR_1_2:.*]] = cir.ptr_stride(%[[ARR_1_PTR]] : !cir.ptr, %[[IDX]] : !s32i), !cir.ptr -// CIR: %[[TMP_2:.*]] = cir.load %[[ARR_1_2]] : !cir.ptr, !s32i -// CIR: cir.store %[[TMP_2]], %[[INIT]] : !s32i, !cir.ptr +// CIR: %[[TMP_2:.*]] = cir.load{{.*}} %[[ARR_1_2]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[TMP_2]], %[[INIT]] : !s32i, !cir.ptr // LLVM: define void @_Z5func9PA5_i(ptr %[[ARG:.*]]) // LLVM: %[[ARR:.*]] = alloca ptr, i64 1, align 8 @@ -442,12 +442,12 @@ void func10(int *a) { // CIR: cir.func @_Z6func10Pi(%[[ARG:.*]]: !cir.ptr // CIR: %[[ARR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["a", init] // CIR: %[[INIT:.*]] = cir.alloca !s32i, !cir.ptr, ["e", init] -// CIR: cir.store %[[ARG]], %[[ARR]] : !cir.ptr, !cir.ptr> +// CIR: cir.store{{.*}} %[[ARG]], %[[ARR]] : !cir.ptr, !cir.ptr> // CIR: %[[IDX:.*]] = cir.const #cir.int<5> : !s32i -// CIR: %[[TMP_1:.*]] = cir.load %[[ARR]] : !cir.ptr>, !cir.ptr +// CIR: %[[TMP_1:.*]] = cir.load{{.*}} %[[ARR]] : !cir.ptr>, !cir.ptr // CIR: %[[ELE:.*]] = cir.ptr_stride(%[[TMP_1]] : !cir.ptr, %[[IDX]] : !s32i), !cir.ptr -// CIR: %[[TMP_2:.*]] = cir.load %[[ELE]] : !cir.ptr, !s32i -// CIR: cir.store %[[TMP_2]], %[[INIT]] : !s32i, !cir.ptr +// CIR: %[[TMP_2:.*]] = cir.load{{.*}} %[[ELE]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[TMP_2]], %[[INIT]] : !s32i, !cir.ptr // LLVM: define void @_Z6func10Pi(ptr %[[ARG:.*]]) { // LLVM: %[[ARR:.*]] = alloca ptr, i64 1, align 8 diff --git a/clang/test/CIR/CodeGen/basic.c b/clang/test/CIR/CodeGen/basic.c index d0e241cdc5ae9..835885cb3f4d1 100644 --- a/clang/test/CIR/CodeGen/basic.c +++ b/clang/test/CIR/CodeGen/basic.c @@ -16,11 +16,11 @@ int f1(int i) { // CIR-NEXT: cir.func @f1(%arg0: !s32i loc({{.*}})) -> !s32i // CIR-NEXT: %[[I_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["i", init] {alignment = 4 : i64} // CIR-NEXT: %[[RV:.*]] = cir.alloca !s32i, !cir.ptr, ["__retval"] {alignment = 4 : i64} -// CIR-NEXT: cir.store %arg0, %[[I_PTR]] : !s32i, !cir.ptr -// CIR-NEXT: %[[I_IGNORED:.*]] = cir.load %[[I_PTR]] : !cir.ptr, !s32i -// CIR-NEXT: %[[I:.*]] = cir.load %[[I_PTR]] : !cir.ptr, !s32i -// CIR-NEXT: cir.store %[[I]], %[[RV]] : !s32i, !cir.ptr -// CIR-NEXT: %[[R:.*]] = cir.load %[[RV]] : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %arg0, %[[I_PTR]] : !s32i, !cir.ptr +// CIR-NEXT: %[[I_IGNORED:.*]] = cir.load{{.*}} %[[I_PTR]] : !cir.ptr, !s32i +// CIR-NEXT: %[[I:.*]] = cir.load{{.*}} %[[I_PTR]] : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %[[I]], %[[RV]] : !s32i, !cir.ptr +// CIR-NEXT: %[[R:.*]] = cir.load{{.*}} %[[RV]] : !cir.ptr, !s32i // CIR-NEXT: cir.return %[[R]] : !s32i // LLVM: define i32 @f1(i32 %[[IP:.*]]) @@ -46,8 +46,8 @@ int f2(void) { return 3; } // CIR: cir.func @f2() -> !s32i // CIR-NEXT: %[[RV:.*]] = cir.alloca !s32i, !cir.ptr, ["__retval"] {alignment = 4 : i64} // CIR-NEXT: %[[THREE:.*]] = cir.const #cir.int<3> : !s32i -// CIR-NEXT: cir.store %[[THREE]], %[[RV]] : !s32i, !cir.ptr -// CIR-NEXT: %[[R:.*]] = cir.load %0 : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %[[THREE]], %[[RV]] : !s32i, !cir.ptr +// CIR-NEXT: %[[R:.*]] = cir.load{{.*}} %0 : !cir.ptr, !s32i // CIR-NEXT: cir.return %[[R]] : !s32i // LLVM: define i32 @f2() @@ -69,10 +69,10 @@ int f3(void) { // CIR-NEXT: %[[RV:.*]] = cir.alloca !s32i, !cir.ptr, ["__retval"] {alignment = 4 : i64} // CIR-NEXT: %[[I_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["i", init] {alignment = 4 : i64} // CIR-NEXT: %[[THREE:.*]] = cir.const #cir.int<3> : !s32i -// CIR-NEXT: cir.store %[[THREE]], %[[I_PTR]] : !s32i, !cir.ptr -// CIR-NEXT: %[[I:.*]] = cir.load %[[I_PTR]] : !cir.ptr, !s32i -// CIR-NEXT: cir.store %[[I]], %[[RV]] : !s32i, !cir.ptr -// CIR-NEXT: %[[R:.*]] = cir.load %[[RV]] : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %[[THREE]], %[[I_PTR]] : !s32i, !cir.ptr +// CIR-NEXT: %[[I:.*]] = cir.load{{.*}} %[[I_PTR]] : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %[[I]], %[[RV]] : !s32i, !cir.ptr +// CIR-NEXT: %[[R:.*]] = cir.load{{.*}} %[[RV]] : !cir.ptr, !s32i // CIR-NEXT: cir.return %[[R]] : !s32i // LLVM: define i32 @f3() @@ -153,9 +153,9 @@ int f6(void) { // CIR: cir.func @f6() -> !s32i // CIR-NEXT: %[[RV:.*]] = cir.alloca !s32i, !cir.ptr, ["__retval"] {alignment = 4 : i64} // CIR-NEXT: %[[GV_PTR:.*]] = cir.get_global @gv : !cir.ptr -// CIR-NEXT: %[[GV:.*]] = cir.load %[[GV_PTR]] : !cir.ptr, !s32i -// CIR-NEXT: cir.store %[[GV]], %[[RV]] : !s32i, !cir.ptr -// CIR-NEXT: %[[R:.*]] = cir.load %[[RV]] : !cir.ptr, !s32i +// CIR-NEXT: %[[GV:.*]] = cir.load{{.*}} %[[GV_PTR]] : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %[[GV]], %[[RV]] : !s32i, !cir.ptr +// CIR-NEXT: %[[R:.*]] = cir.load{{.*}} %[[RV]] : !cir.ptr, !s32i // CIR-NEXT: cir.return %[[R]] : !s32i // LLVM: define i32 @f6() @@ -178,9 +178,9 @@ int f7(int a, int b, int c) { // CIR: %[[A_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["a", init] // CIR: %[[B_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["b", init] // CIR: %[[C_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["c", init] -// CIR: %[[A:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !s32i -// CIR: %[[B:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !s32i -// CIR: %[[C:.*]] = cir.load %[[C_PTR]] : !cir.ptr, !s32i +// CIR: %[[A:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !s32i +// CIR: %[[B:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !s32i +// CIR: %[[C:.*]] = cir.load{{.*}} %[[C_PTR]] : !cir.ptr, !s32i // CIR: %[[B_PLUS_C:.*]] = cir.binop(add, %[[B]], %[[C]]) nsw : !s32i // CIR: %[[RETVAL:.*]] = cir.binop(add, %[[A]], %[[B_PLUS_C]]) nsw : !s32i @@ -213,10 +213,10 @@ int f8(int *p) { // CIR: cir.func @f8 // CIR: %[[P_PTR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["p", init] // CIR: %[[TWO:.*]] = cir.const #cir.int<2> : !s32i -// CIR: %[[P:.*]] = cir.load deref %[[P_PTR]] : !cir.ptr>, !cir.ptr -// CIR: cir.store %[[TWO]], %[[P]] : !s32i, !cir.ptr -// CIR: %[[P2:.*]] = cir.load deref %[[P_PTR]] : !cir.ptr>, !cir.ptr -// CIR: %[[STAR_P:.*]] = cir.load %[[P2]] : !cir.ptr, !s32i +// CIR: %[[P:.*]] = cir.load deref{{.*}} %[[P_PTR]] : !cir.ptr>, !cir.ptr +// CIR: cir.store{{.*}} %[[TWO]], %[[P]] : !s32i, !cir.ptr +// CIR: %[[P2:.*]] = cir.load deref{{.*}} %[[P_PTR]] : !cir.ptr>, !cir.ptr +// CIR: %[[STAR_P:.*]] = cir.load{{.*}} %[[P2]] : !cir.ptr, !s32i // LLVM: define i32 @f8 // LLVM: %[[P_PTR:.*]] = alloca ptr, i64 1, align 8 @@ -250,7 +250,7 @@ void f10(int arg0, ...) {} // CIR: cir.func @f10(%[[ARG0:.*]]: !s32i loc({{.*}}), ...) // CIR-NEXT: %[[ARG0_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["arg0", init] {alignment = 4 : i64} -// CIR-NEXT: cir.store %[[ARG0]], %[[ARG0_PTR]] : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ARG0]], %[[ARG0_PTR]] : !s32i, !cir.ptr // CIR-NEXT: cir.return // LLVM: define void @f10(i32 %[[ARG0:.*]], ...) @@ -284,8 +284,8 @@ size_type max_size(void) { // OGCG: define{{.*}} i64 @max_size() // OGCG: ret i64 2305843009213693951 -// CHECK: cir.store %5, %0 : !u64i, !cir.ptr -// CHECK: %6 = cir.load %0 : !cir.ptr, !u64i +// CHECK: cir.store{{.*}} %5, %0 : !u64i, !cir.ptr +// CHECK: %6 = cir.load{{.*}} %0 : !cir.ptr, !u64i // CHECK: cir.return %6 : !u64i // CHECK: } diff --git a/clang/test/CIR/CodeGen/basic.cpp b/clang/test/CIR/CodeGen/basic.cpp index 43542c249525d..53f13f13853fa 100644 --- a/clang/test/CIR/CodeGen/basic.cpp +++ b/clang/test/CIR/CodeGen/basic.cpp @@ -9,9 +9,9 @@ int f1() { // CHECK: cir.func @_Z2f1v() -> !s32i // CHECK: %[[RV:.*]] = cir.alloca !s32i, !cir.ptr, ["__retval"] {alignment = 4 : i64} // CHECK: %[[I_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["i"] {alignment = 4 : i64} -// CHECK: %[[I:.*]] = cir.load %[[I_PTR]] : !cir.ptr, !s32i -// CHECK: cir.store %[[I]], %[[RV]] : !s32i, !cir.ptr -// CHECK: %[[R:.*]] = cir.load %[[RV]] : !cir.ptr, !s32i +// CHECK: %[[I:.*]] = cir.load{{.*}} %[[I_PTR]] : !cir.ptr, !s32i +// CHECK: cir.store{{.*}} %[[I]], %[[RV]] : !s32i, !cir.ptr +// CHECK: %[[R:.*]] = cir.load{{.*}} %[[RV]] : !cir.ptr, !s32i // CHECK: cir.return %[[R]] : !s32i int f2() { @@ -23,10 +23,10 @@ int f2() { // CHECK: %[[RV:.*]] = cir.alloca !s32i, !cir.ptr, ["__retval"] {alignment = 4 : i64} // CHECK: %[[I_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["i", init, const] {alignment = 4 : i64} // CHECK: %[[TWO:.*]] = cir.const #cir.int<2> : !s32i -// CHECK: cir.store %[[TWO]], %[[I_PTR]] : !s32i, !cir.ptr -// CHECK: %[[I:.*]] = cir.load %[[I_PTR]] : !cir.ptr, !s32i -// CHECK: cir.store %[[I]], %[[RV]] : !s32i, !cir.ptr -// CHECK: %[[R:.*]] = cir.load %[[RV]] : !cir.ptr, !s32i +// CHECK: cir.store{{.*}} %[[TWO]], %[[I_PTR]] : !s32i, !cir.ptr +// CHECK: %[[I:.*]] = cir.load{{.*}} %[[I_PTR]] : !cir.ptr, !s32i +// CHECK: cir.store{{.*}} %[[I]], %[[RV]] : !s32i, !cir.ptr +// CHECK: %[[R:.*]] = cir.load{{.*}} %[[RV]] : !cir.ptr, !s32i // CHECK: cir.return %[[R]] : !s32i int f3(int i) { @@ -36,10 +36,10 @@ int f3(int i) { // CHECK: cir.func @_Z2f3i(%[[ARG:.*]]: !s32i loc({{.*}})) -> !s32i // CHECK: %[[ARG_ALLOCA:.*]] = cir.alloca !s32i, !cir.ptr, ["i", init] {alignment = 4 : i64} // CHECK: %[[RV:.*]] = cir.alloca !s32i, !cir.ptr, ["__retval"] {alignment = 4 : i64} -// CHECK: cir.store %[[ARG]], %[[ARG_ALLOCA]] : !s32i, !cir.ptr -// CHECK: %[[ARG_VAL:.*]] = cir.load %[[ARG_ALLOCA]] : !cir.ptr, !s32i -// CHECK: cir.store %[[ARG_VAL]], %[[RV]] : !s32i, !cir.ptr -// CHECK: %[[R:.*]] = cir.load %[[RV]] : !cir.ptr, !s32i +// CHECK: cir.store{{.*}} %[[ARG]], %[[ARG_ALLOCA]] : !s32i, !cir.ptr +// CHECK: %[[ARG_VAL:.*]] = cir.load{{.*}} %[[ARG_ALLOCA]] : !cir.ptr, !s32i +// CHECK: cir.store{{.*}} %[[ARG_VAL]], %[[RV]] : !s32i, !cir.ptr +// CHECK: %[[R:.*]] = cir.load{{.*}} %[[RV]] : !cir.ptr, !s32i // CHECK: cir.return %[[R]] : !s32i int f4(const int i) { @@ -49,10 +49,10 @@ int f4(const int i) { // CHECK: cir.func @_Z2f4i(%[[ARG:.*]]: !s32i loc({{.*}})) -> !s32i // CHECK: %[[ARG_ALLOCA:.*]] = cir.alloca !s32i, !cir.ptr, ["i", init, const] {alignment = 4 : i64} // CHECK: %[[RV:.*]] = cir.alloca !s32i, !cir.ptr, ["__retval"] {alignment = 4 : i64} -// CHECK: cir.store %[[ARG]], %[[ARG_ALLOCA]] : !s32i, !cir.ptr -// CHECK: %[[ARG_VAL:.*]] = cir.load %[[ARG_ALLOCA]] : !cir.ptr, !s32i -// CHECK: cir.store %[[ARG_VAL]], %[[RV]] : !s32i, !cir.ptr -// CHECK: %[[R:.*]] = cir.load %[[RV]] : !cir.ptr, !s32i +// CHECK: cir.store{{.*}} %[[ARG]], %[[ARG_ALLOCA]] : !s32i, !cir.ptr +// CHECK: %[[ARG_VAL:.*]] = cir.load{{.*}} %[[ARG_ALLOCA]] : !cir.ptr, !s32i +// CHECK: cir.store{{.*}} %[[ARG_VAL]], %[[RV]] : !s32i, !cir.ptr +// CHECK: %[[R:.*]] = cir.load{{.*}} %[[RV]] : !cir.ptr, !s32i // CHECK: cir.return %[[R]] : !s32i int *f5() { @@ -70,22 +70,22 @@ int *f5() { // CHECK-NEXT: %[[RET_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["__retval"] {alignment = 8 : i64} // CHECK-NEXT: %[[P_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["p", init] {alignment = 8 : i64} // CHECK-NEXT: %[[NULLPTR:.*]] = cir.const #cir.ptr : !cir.ptr -// CHECK-NEXT: cir.store %[[NULLPTR]], %[[P_ADDR]] : !cir.ptr, !cir.ptr> +// CHECK-NEXT: cir.store{{.*}} %[[NULLPTR]], %[[P_ADDR]] : !cir.ptr, !cir.ptr> // CHECK-NEXT: cir.scope { // CHECK-NEXT: %[[X_ADDR:.*]] = cir.alloca !s32i, !cir.ptr, ["x", init] {alignment = 4 : i64} // CHECK-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i -// CHECK-NEXT: cir.store %[[ZERO]], %[[X_ADDR]] : !s32i, !cir.ptr -// CHECK-NEXT: cir.store %[[X_ADDR]], %[[P_ADDR]] : !cir.ptr, !cir.ptr> +// CHECK-NEXT: cir.store{{.*}} %[[ZERO]], %[[X_ADDR]] : !s32i, !cir.ptr +// CHECK-NEXT: cir.store{{.*}} %[[X_ADDR]], %[[P_ADDR]] : !cir.ptr, !cir.ptr> // CHECK-NEXT: %[[FOURTYTWO:.*]] = cir.const #cir.int<42> : !s32i -// CHECK-NEXT: %[[P:.*]] = cir.load deref %[[P_ADDR]] : !cir.ptr>, !cir.ptr -// CHECK-NEXT: cir.store %[[FOURTYTWO]], %[[P]] : !s32i, !cir.ptr +// CHECK-NEXT: %[[P:.*]] = cir.load deref{{.*}} %[[P_ADDR]] : !cir.ptr>, !cir.ptr +// CHECK-NEXT: cir.store{{.*}} %[[FOURTYTWO]], %[[P]] : !s32i, !cir.ptr // CHECK-NEXT: } // CHECK-NEXT: %[[FOURTYTHREE:.*]] = cir.const #cir.int<43> : !s32i -// CHECK-NEXT: %[[P:.*]] = cir.load deref %[[P_ADDR]] : !cir.ptr>, !cir.ptr -// CHECK-NEXT: cir.store %[[FOURTYTHREE]], %[[P]] : !s32i, !cir.ptr -// CHECK-NEXT: %[[P:.*]] = cir.load %[[P_ADDR]] : !cir.ptr>, !cir.ptr -// CHECK-NEXT: cir.store %[[P]], %[[RET_ADDR]] : !cir.ptr, !cir.ptr> -// CHECK-NEXT: %[[RET_VAL:.*]] = cir.load %[[RET_ADDR]] : !cir.ptr>, !cir.ptr +// CHECK-NEXT: %[[P:.*]] = cir.load deref{{.*}} %[[P_ADDR]] : !cir.ptr>, !cir.ptr +// CHECK-NEXT: cir.store{{.*}} %[[FOURTYTHREE]], %[[P]] : !s32i, !cir.ptr +// CHECK-NEXT: %[[P:.*]] = cir.load{{.*}} %[[P_ADDR]] : !cir.ptr>, !cir.ptr +// CHECK-NEXT: cir.store{{.*}} %[[P]], %[[RET_ADDR]] : !cir.ptr, !cir.ptr> +// CHECK-NEXT: %[[RET_VAL:.*]] = cir.load{{.*}} %[[RET_ADDR]] : !cir.ptr>, !cir.ptr // CHECK-NEXT: cir.return %[[RET_VAL]] : !cir.ptr using size_type = unsigned long; @@ -102,8 +102,8 @@ size_type max_size() { // CHECK: %3 = cir.cast(integral, %2 : !s32i), !u64i // CHECK: %4 = cir.const #cir.int<8> : !u64i // CHECK: %5 = cir.binop(div, %3, %4) : !u64i -// CHECK: cir.store %5, %0 : !u64i, !cir.ptr -// CHECK: %6 = cir.load %0 : !cir.ptr, !u64i +// CHECK: cir.store{{.*}} %5, %0 : !u64i, !cir.ptr +// CHECK: %6 = cir.load{{.*}} %0 : !cir.ptr, !u64i // CHECK: cir.return %6 : !u64i // CHECK: } @@ -115,13 +115,13 @@ void ref_arg(int &x) { // CHECK: cir.func @_Z7ref_argRi(%[[ARG:.*]]: !cir.ptr {{.*}}) // CHECK: %[[X_REF_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["x", init, const] {alignment = 8 : i64} // CHECK: %[[Y_ADDR:.*]] = cir.alloca !s32i, !cir.ptr, ["y", init] {alignment = 4 : i64} -// CHECK: cir.store %[[ARG]], %[[X_REF_ADDR]] : !cir.ptr, !cir.ptr> -// CHECK: %[[X_REF:.*]] = cir.load %[[X_REF_ADDR]] : !cir.ptr>, !cir.ptr -// CHECK: %[[Y:.*]] = cir.load %[[X_REF]] : !cir.ptr, !s32i -// CHECK: cir.store %[[Y]], %[[Y_ADDR]] : !s32i, !cir.ptr +// CHECK: cir.store{{.*}} %[[ARG]], %[[X_REF_ADDR]] : !cir.ptr, !cir.ptr> +// CHECK: %[[X_REF:.*]] = cir.load{{.*}} %[[X_REF_ADDR]] : !cir.ptr>, !cir.ptr +// CHECK: %[[Y:.*]] = cir.load{{.*}} %[[X_REF]] : !cir.ptr, !s32i +// CHECK: cir.store{{.*}} %[[Y]], %[[Y_ADDR]] : !s32i, !cir.ptr // CHECK: %[[THREE:.*]] = cir.const #cir.int<3> : !s32i -// CHECK: %[[X_REF:.*]] = cir.load %[[X_REF_ADDR]] : !cir.ptr>, !cir.ptr -// CHECK: cir.store %[[THREE]], %[[X_REF]] : !s32i, !cir.ptr +// CHECK: %[[X_REF:.*]] = cir.load{{.*}} %[[X_REF_ADDR]] : !cir.ptr>, !cir.ptr +// CHECK: cir.store{{.*}} %[[THREE]], %[[X_REF]] : !s32i, !cir.ptr // CHECK: cir.return short gs; @@ -132,8 +132,8 @@ short &return_ref() { // CHECK: cir.func @_Z10return_refv() -> !cir.ptr // CHECK: %[[RETVAL_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["__retval"] {alignment = 8 : i64} // CHECK: %[[GS_ADDR:.*]] = cir.get_global @gs : !cir.ptr -// CHECK: cir.store %[[GS_ADDR]], %[[RETVAL_ADDR]] : !cir.ptr, !cir.ptr> -// CHECK: %[[RETVAL:.*]] = cir.load %[[RETVAL_ADDR]] : !cir.ptr>, !cir.ptr +// CHECK: cir.store{{.*}} %[[GS_ADDR]], %[[RETVAL_ADDR]] : !cir.ptr, !cir.ptr> +// CHECK: %[[RETVAL:.*]] = cir.load{{.*}} %[[RETVAL_ADDR]] : !cir.ptr>, !cir.ptr // CHECK: cir.return %[[RETVAL]] : !cir.ptr void ref_local(short x) { @@ -143,8 +143,8 @@ void ref_local(short x) { // CHECK: cir.func @_Z9ref_locals(%[[ARG:.*]]: !s16i {{.*}}) // CHECK: %[[X_ADDR:.*]] = cir.alloca !s16i, !cir.ptr, ["x", init] {alignment = 2 : i64} // CHECK: %[[Y_REF_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["y", init, const] {alignment = 8 : i64} -// CHECK: cir.store %[[ARG]], %[[X_ADDR]] : !s16i, !cir.ptr -// CHECK: cir.store %[[X_ADDR]], %[[Y_REF_ADDR]] : !cir.ptr, !cir.ptr> +// CHECK: cir.store{{.*}} %[[ARG]], %[[X_ADDR]] : !s16i, !cir.ptr +// CHECK: cir.store{{.*}} %[[X_ADDR]], %[[Y_REF_ADDR]] : !cir.ptr, !cir.ptr> enum A { A_one, diff --git a/clang/test/CIR/CodeGen/binassign.c b/clang/test/CIR/CodeGen/binassign.c index 5a7f0b7fd3f79..4955c988ec095 100644 --- a/clang/test/CIR/CodeGen/binassign.c +++ b/clang/test/CIR/CodeGen/binassign.c @@ -23,14 +23,14 @@ void binary_assign(void) { // CIR: %[[F:.*]] = cir.alloca !cir.float, !cir.ptr, ["f"] // CIR: %[[I:.*]] = cir.alloca !s32i, !cir.ptr, ["i"] // CIR: %[[TRUE:.*]] = cir.const #true -// CIR: cir.store %[[TRUE]], %[[B]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} %[[TRUE]], %[[B]] : !cir.bool, !cir.ptr // CIR: %[[CHAR_INI_INIT:.*]] = cir.const #cir.int<65> : !s32i // CIR: %[[CHAR_VAL:.*]] = cir.cast(integral, %[[CHAR_INI_INIT]] : !s32i), !s8i -// CIR: cir.store %[[CHAR_VAL]], %[[C]] : !s8i, !cir.ptr +// CIR: cir.store{{.*}} %[[CHAR_VAL]], %[[C]] : !s8i, !cir.ptr // CIR: %[[FLOAT_VAL:.*]] = cir.const #cir.fp<3.140000e+00> : !cir.float -// CIR: cir.store %[[FLOAT_VAL]], %[[F]] : !cir.float, !cir.ptr +// CIR: cir.store{{.*}} %[[FLOAT_VAL]], %[[F]] : !cir.float, !cir.ptr // CIR: %[[INT_VAL:.*]] = cir.const #cir.int<42> : !s32i -// CIR: cir.store %[[INT_VAL]], %[[I]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[INT_VAL]], %[[I]] : !s32i, !cir.ptr // CIR: cir.return // LLVM-LABEL: define {{.*}}void @binary_assign() { diff --git a/clang/test/CIR/CodeGen/binop.cpp b/clang/test/CIR/CodeGen/binop.cpp index 086be8a2bba21..dbd17fb7ba83d 100644 --- a/clang/test/CIR/CodeGen/binop.cpp +++ b/clang/test/CIR/CodeGen/binop.cpp @@ -200,18 +200,18 @@ void signed_shift(int a, int b) { // CIR: %[[B_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["b", init] // CIR: %[[X_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["x", init] -// CIR: cir.store %[[ARG0]], %[[A_PTR]] : !s32i, !cir.ptr -// CIR: cir.store %[[ARG1]], %[[B_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !s32i, !cir.ptr -// CIR: %[[A1:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !s32i -// CIR: %[[B1:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !s32i +// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !s32i +// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !s32i // CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !s32i, %[[B1]] : !s32i) -> !s32i -// CIR: cir.store %[[ASHR]], %[[X_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !s32i, !cir.ptr -// CIR: %[[A2:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !s32i -// CIR: %[[B2:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !s32i +// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !s32i +// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !s32i // CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !s32i, %[[B2]] : !s32i) -> !s32i -// CIR: cir.store %[[SHL]], %[[X_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !s32i, !cir.ptr // CIR: cir.return @@ -266,18 +266,18 @@ void unsigned_shift(unsigned a, unsigned b) { // CIR: %[[B_PTR:.*]] = cir.alloca !u32i, !cir.ptr, ["b", init] // CIR: %[[X_PTR:.*]] = cir.alloca !u32i, !cir.ptr, ["x", init] -// CIR: cir.store %[[ARG0]], %[[A_PTR]] : !u32i, !cir.ptr -// CIR: cir.store %[[ARG1]], %[[B_PTR]] : !u32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !u32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !u32i, !cir.ptr -// CIR: %[[A1:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !u32i -// CIR: %[[B1:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !u32i +// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !u32i +// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !u32i // CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !u32i, %[[B1]] : !u32i) -> !u32i -// CIR: cir.store %[[ASHR]], %[[X_PTR]] : !u32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !u32i, !cir.ptr -// CIR: %[[A2:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !u32i -// CIR: %[[B2:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !u32i +// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !u32i +// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !u32i // CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !u32i, %[[B2]] : !u32i) -> !u32i -// CIR: cir.store %[[SHL]], %[[X_PTR]] : !u32i, !cir.ptr +// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !u32i, !cir.ptr // CIR: cir.return @@ -332,20 +332,20 @@ void zext_shift_example(int a, unsigned char b) { // CIR: %[[B_PTR:.*]] = cir.alloca !u8i, !cir.ptr, ["b", init] // CIR: %[[X_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["x", init] -// CIR: cir.store %[[ARG0]], %[[A_PTR]] : !s32i, !cir.ptr -// CIR: cir.store %[[ARG1]], %[[B_PTR]] : !u8i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !u8i, !cir.ptr -// CIR: %[[A1:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !s32i -// CIR: %[[B1:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !u8i +// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !s32i +// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !u8i // CIR: %[[B1_EXT:.*]] = cir.cast(integral, %[[B1]] : !u8i), !s32i // CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !s32i, %[[B1_EXT]] : !s32i) -> !s32i -// CIR: cir.store %[[ASHR]], %[[X_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !s32i, !cir.ptr -// CIR: %[[A2:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !s32i -// CIR: %[[B2:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !u8i +// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !s32i +// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !u8i // CIR: %[[B2_EXT:.*]] = cir.cast(integral, %[[B2]] : !u8i), !s32i // CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !s32i, %[[B2_EXT]] : !s32i) -> !s32i -// CIR: cir.store %[[SHL]], %[[X_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !s32i, !cir.ptr // CIR: cir.return @@ -404,20 +404,20 @@ void sext_shift_example(int a, signed char b) { // CIR: %[[B_PTR:.*]] = cir.alloca !s8i, !cir.ptr, ["b", init] // CIR: %[[X_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["x", init] -// CIR: cir.store %[[ARG0]], %[[A_PTR]] : !s32i, !cir.ptr -// CIR: cir.store %[[ARG1]], %[[B_PTR]] : !s8i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !s8i, !cir.ptr -// CIR: %[[A1:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !s32i -// CIR: %[[B1:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !s8i +// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !s32i +// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !s8i // CIR: %[[B1_EXT:.*]] = cir.cast(integral, %[[B1]] : !s8i), !s32i // CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !s32i, %[[B1_EXT]] : !s32i) -> !s32i -// CIR: cir.store %[[ASHR]], %[[X_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !s32i, !cir.ptr -// CIR: %[[A2:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !s32i -// CIR: %[[B2:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !s8i +// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !s32i +// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !s8i // CIR: %[[B2_EXT:.*]] = cir.cast(integral, %[[B2]] : !s8i), !s32i // CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !s32i, %[[B2_EXT]] : !s32i) -> !s32i -// CIR: cir.store %[[SHL]], %[[X_PTR]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !s32i, !cir.ptr // CIR: cir.return @@ -476,20 +476,20 @@ void long_shift_example(long long a, short b) { // CIR: %[[B_PTR:.*]] = cir.alloca !s16i, !cir.ptr, ["b", init] // CIR: %[[X_PTR:.*]] = cir.alloca !s64i, !cir.ptr, ["x", init] -// CIR: cir.store %[[ARG0]], %[[A_PTR]] : !s64i, !cir.ptr -// CIR: cir.store %[[ARG1]], %[[B_PTR]] : !s16i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG0]], %[[A_PTR]] : !s64i, !cir.ptr +// CIR: cir.store{{.*}} %[[ARG1]], %[[B_PTR]] : !s16i, !cir.ptr -// CIR: %[[A1:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !s64i -// CIR: %[[B1:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !s16i +// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !s64i +// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !s16i // CIR: %[[B1_EXT:.*]] = cir.cast(integral, %[[B1]] : !s16i), !s32i // CIR: %[[ASHR:.*]] = cir.shift(right, %[[A1]] : !s64i, %[[B1_EXT]] : !s32i) -> !s64i -// CIR: cir.store %[[ASHR]], %[[X_PTR]] : !s64i, !cir.ptr +// CIR: cir.store{{.*}} %[[ASHR]], %[[X_PTR]] : !s64i, !cir.ptr -// CIR: %[[A2:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !s64i -// CIR: %[[B2:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !s16i +// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !s64i +// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !s16i // CIR: %[[B2_EXT:.*]] = cir.cast(integral, %[[B2]] : !s16i), !s32i // CIR: %[[SHL:.*]] = cir.shift(left, %[[A2]] : !s64i, %[[B2_EXT]] : !s32i) -> !s64i -// CIR: cir.store %[[SHL]], %[[X_PTR]] : !s64i, !cir.ptr +// CIR: cir.store{{.*}} %[[SHL]], %[[X_PTR]] : !s64i, !cir.ptr // CIR: cir.return diff --git a/clang/test/CIR/CodeGen/call.cpp b/clang/test/CIR/CodeGen/call.cpp index 8b8f1296b5108..792f57afd6bd1 100644 --- a/clang/test/CIR/CodeGen/call.cpp +++ b/clang/test/CIR/CodeGen/call.cpp @@ -48,7 +48,7 @@ int f7(int (*ptr)(int, int)) { } // CIR-LABEL: cir.func @_Z2f7PFiiiE -// CIR: %[[#ptr:]] = cir.load %{{.+}} : !cir.ptr !s32i>>>, !cir.ptr !s32i>> +// CIR: %[[#ptr:]] = cir.load{{.*}} %{{.+}} : !cir.ptr !s32i>>>, !cir.ptr !s32i>> // CIR-NEXT: %[[#a:]] = cir.const #cir.int<1> : !s32i // CIR-NEXT: %[[#b:]] = cir.const #cir.int<2> : !s32i // CIR-NEXT: %{{.+}} = cir.call %[[#ptr]](%[[#a]], %[[#b]]) : (!cir.ptr !s32i>>, !s32i, !s32i) -> !s32i diff --git a/clang/test/CIR/CodeGen/cast.cpp b/clang/test/CIR/CodeGen/cast.cpp index 9da72cd35d963..a7c11b1939ba5 100644 --- a/clang/test/CIR/CodeGen/cast.cpp +++ b/clang/test/CIR/CodeGen/cast.cpp @@ -11,10 +11,10 @@ unsigned char cxxstaticcast_0(unsigned int x) { // CIR: %[[XPTR:[0-9]+]] = cir.alloca !u32i, !cir.ptr, ["x", init] {alignment = 4 : i64} // CIR: %[[RV:[0-9]+]] = cir.alloca !u8i, !cir.ptr, ["__retval"] {alignment = 1 : i64} // CIR: cir.store %arg0, %[[XPTR]] : !u32i, !cir.ptr -// CIR: %[[XVAL:[0-9]+]] = cir.load %[[XPTR]] : !cir.ptr, !u32i +// CIR: %[[XVAL:[0-9]+]] = cir.load{{.*}} %[[XPTR]] : !cir.ptr, !u32i // CIR: %[[CASTED:[0-9]+]] = cir.cast(integral, %[[XVAL]] : !u32i), !u8i // CIR: cir.store %[[CASTED]], %[[RV]] : !u8i, !cir.ptr -// CIR: %[[R:[0-9]+]] = cir.load %1 : !cir.ptr, !u8i +// CIR: %[[R:[0-9]+]] = cir.load{{.*}} %1 : !cir.ptr, !u8i // CIR: cir.return %[[R]] : !u8i // CIR: } @@ -84,7 +84,7 @@ bool cptr(void *d) { // CIR: cir.func @_Z4cptrPv(%arg0: !cir.ptr // CIR: %[[DPTR:[0-9]+]] = cir.alloca !cir.ptr, !cir.ptr>, ["d", init] {alignment = 8 : i64} -// CIR: %[[DVAL:[0-9]+]] = cir.load %[[DPTR]] : !cir.ptr>, !cir.ptr +// CIR: %[[DVAL:[0-9]+]] = cir.load{{.*}} %[[DPTR]] : !cir.ptr>, !cir.ptr // CIR: %{{[0-9]+}} = cir.cast(ptr_to_bool, %[[DVAL]] : !cir.ptr), !cir.bool // LLVM-LABEL: define i1 @_Z4cptrPv(ptr %0) @@ -118,7 +118,7 @@ void bitcast() { vi4 b = (vi4)a; } -// CIR: %[[D_VEC:.*]] = cir.load {{.*}} : !cir.ptr>, !cir.vector<2 x !cir.double> +// CIR: %[[D_VEC:.*]] = cir.load{{.*}} {{.*}} : !cir.ptr>, !cir.vector<2 x !cir.double> // CIR: %[[I_VEC:.*]] = cir.cast(bitcast, %[[D_VEC]] : !cir.vector<2 x !cir.double>), !cir.vector<4 x !s32i> // LLVM: %[[D_VEC:.*]] = load <2 x double>, ptr {{.*}}, align 16 diff --git a/clang/test/CIR/CodeGen/cmp.cpp b/clang/test/CIR/CodeGen/cmp.cpp index 21f440cdefaa0..40529d92b2a05 100644 --- a/clang/test/CIR/CodeGen/cmp.cpp +++ b/clang/test/CIR/CodeGen/cmp.cpp @@ -20,29 +20,29 @@ void c0(int a, int b) { // CIR: %[[B_PTR:.*]] = cir.alloca !s32i, !cir.ptr, ["b", init] // CIR: %[[X_PTR:.*]] = cir.alloca !cir.bool, !cir.ptr, ["x", init] -// CIR: %[[A1:.*]] = cir.load %[[A_PTR]] -// CIR: %[[B1:.*]] = cir.load %[[B_PTR]] +// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] +// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] // CIR: %{{.*}} = cir.cmp(gt, %[[A1]], %[[B1]]) : !s32i, !cir.bool -// CIR: cir.store {{.*}}, %[[X_PTR]] +// CIR: cir.store{{.*}} {{.*}}, %[[X_PTR]] -// CIR: %[[A2:.*]] = cir.load %[[A_PTR]] -// CIR: %[[B2:.*]] = cir.load %[[B_PTR]] +// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] +// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] // CIR: %{{.*}} = cir.cmp(lt, %[[A2]], %[[B2]]) : !s32i, !cir.bool -// CIR: %[[A3:.*]] = cir.load %[[A_PTR]] -// CIR: %[[B3:.*]] = cir.load %[[B_PTR]] +// CIR: %[[A3:.*]] = cir.load{{.*}} %[[A_PTR]] +// CIR: %[[B3:.*]] = cir.load{{.*}} %[[B_PTR]] // CIR: %{{.*}} = cir.cmp(le, %[[A3]], %[[B3]]) : !s32i, !cir.bool -// CIR: %[[A4:.*]] = cir.load %[[A_PTR]] -// CIR: %[[B4:.*]] = cir.load %[[B_PTR]] +// CIR: %[[A4:.*]] = cir.load{{.*}} %[[A_PTR]] +// CIR: %[[B4:.*]] = cir.load{{.*}} %[[B_PTR]] // CIR: %{{.*}} = cir.cmp(ge, %[[A4]], %[[B4]]) : !s32i, !cir.bool -// CIR: %[[A5:.*]] = cir.load %[[A_PTR]] -// CIR: %[[B5:.*]] = cir.load %[[B_PTR]] +// CIR: %[[A5:.*]] = cir.load{{.*}} %[[A_PTR]] +// CIR: %[[B5:.*]] = cir.load{{.*}} %[[B_PTR]] // CIR: %{{.*}} = cir.cmp(ne, %[[A5]], %[[B5]]) : !s32i, !cir.bool -// CIR: %[[A6:.*]] = cir.load %[[A_PTR]] -// CIR: %[[B6:.*]] = cir.load %[[B_PTR]] +// CIR: %[[A6:.*]] = cir.load{{.*}} %[[A_PTR]] +// CIR: %[[B6:.*]] = cir.load{{.*}} %[[B_PTR]] // CIR: %{{.*}} = cir.cmp(eq, %[[A6]], %[[B6]]) : !s32i, !cir.bool // LLVM-LABEL: define void @_Z2c0ii(i32 %0, i32 %1) { @@ -146,28 +146,28 @@ void c0_unsigned(unsigned int a, unsigned int b) { // CIR: %[[U_B_PTR:.*]] = cir.alloca !u32i, !cir.ptr, ["b", init] // CIR: %[[U_X_PTR:.*]] = cir.alloca !cir.bool, !cir.ptr, ["x", init] -// CIR: %[[UA1:.*]] = cir.load %[[U_A_PTR]] -// CIR: %[[UB1:.*]] = cir.load %[[U_B_PTR]] +// CIR: %[[UA1:.*]] = cir.load{{.*}} %[[U_A_PTR]] +// CIR: %[[UB1:.*]] = cir.load{{.*}} %[[U_B_PTR]] // CIR: %{{.*}} = cir.cmp(gt, %[[UA1]], %[[UB1]]) : !u32i, !cir.bool -// CIR: %[[UA2:.*]] = cir.load %[[U_A_PTR]] -// CIR: %[[UB2:.*]] = cir.load %[[U_B_PTR]] +// CIR: %[[UA2:.*]] = cir.load{{.*}} %[[U_A_PTR]] +// CIR: %[[UB2:.*]] = cir.load{{.*}} %[[U_B_PTR]] // CIR: %{{.*}} = cir.cmp(lt, %[[UA2]], %[[UB2]]) : !u32i, !cir.bool -// CIR: %[[UA3:.*]] = cir.load %[[U_A_PTR]] -// CIR: %[[UB3:.*]] = cir.load %[[U_B_PTR]] +// CIR: %[[UA3:.*]] = cir.load{{.*}} %[[U_A_PTR]] +// CIR: %[[UB3:.*]] = cir.load{{.*}} %[[U_B_PTR]] // CIR: %{{.*}} = cir.cmp(le, %[[UA3]], %[[UB3]]) : !u32i, !cir.bool -// CIR: %[[UA4:.*]] = cir.load %[[U_A_PTR]] -// CIR: %[[UB4:.*]] = cir.load %[[U_B_PTR]] +// CIR: %[[UA4:.*]] = cir.load{{.*}} %[[U_A_PTR]] +// CIR: %[[UB4:.*]] = cir.load{{.*}} %[[U_B_PTR]] // CIR: %{{.*}} = cir.cmp(ge, %[[UA4]], %[[UB4]]) : !u32i, !cir.bool -// CIR: %[[UA5:.*]] = cir.load %[[U_A_PTR]] -// CIR: %[[UB5:.*]] = cir.load %[[U_B_PTR]] +// CIR: %[[UA5:.*]] = cir.load{{.*}} %[[U_A_PTR]] +// CIR: %[[UB5:.*]] = cir.load{{.*}} %[[U_B_PTR]] // CIR: %{{.*}} = cir.cmp(ne, %[[UA5]], %[[UB5]]) : !u32i, !cir.bool -// CIR: %[[UA6:.*]] = cir.load %[[U_A_PTR]] -// CIR: %[[UB6:.*]] = cir.load %[[U_B_PTR]] +// CIR: %[[UA6:.*]] = cir.load{{.*}} %[[U_A_PTR]] +// CIR: %[[UB6:.*]] = cir.load{{.*}} %[[U_B_PTR]] // CIR: %{{.*}} = cir.cmp(eq, %[[UA6]], %[[UB6]]) : !u32i, !cir.bool // LLVM-LABEL: define void @_Z11c0_unsignedjj(i32 %0, i32 %1) { @@ -270,38 +270,38 @@ void c0_float(float a, float b) { // CIR: %[[B_PTR:.*]] = cir.alloca !cir.float, !cir.ptr, ["b", init] // CIR: %[[X_PTR:.*]] = cir.alloca !cir.bool, !cir.ptr, ["x", init] -// CIR: cir.store %arg0, %[[A_PTR]] : !cir.float, !cir.ptr -// CIR: cir.store %arg1, %[[B_PTR]] : !cir.float, !cir.ptr +// CIR: cir.store{{.*}} %arg0, %[[A_PTR]] : !cir.float, !cir.ptr +// CIR: cir.store{{.*}} %arg1, %[[B_PTR]] : !cir.float, !cir.ptr -// CIR: %[[A1:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !cir.float -// CIR: %[[B1:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !cir.float +// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !cir.float +// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !cir.float // CIR: %[[CMP1:.*]] = cir.cmp(gt, %[[A1]], %[[B1]]) : !cir.float, !cir.bool -// CIR: cir.store %[[CMP1]], %[[X_PTR]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} %[[CMP1]], %[[X_PTR]] : !cir.bool, !cir.ptr -// CIR: %[[A2:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !cir.float -// CIR: %[[B2:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !cir.float +// CIR: %[[A2:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !cir.float +// CIR: %[[B2:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !cir.float // CIR: %[[CMP2:.*]] = cir.cmp(lt, %[[A2]], %[[B2]]) : !cir.float, !cir.bool -// CIR: cir.store %[[CMP2]], %[[X_PTR]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} %[[CMP2]], %[[X_PTR]] : !cir.bool, !cir.ptr -// CIR: %[[A3:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !cir.float -// CIR: %[[B3:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !cir.float +// CIR: %[[A3:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !cir.float +// CIR: %[[B3:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !cir.float // CIR: %[[CMP3:.*]] = cir.cmp(le, %[[A3]], %[[B3]]) : !cir.float, !cir.bool -// CIR: cir.store %[[CMP3]], %[[X_PTR]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} %[[CMP3]], %[[X_PTR]] : !cir.bool, !cir.ptr -// CIR: %[[A4:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !cir.float -// CIR: %[[B4:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !cir.float +// CIR: %[[A4:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !cir.float +// CIR: %[[B4:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !cir.float // CIR: %[[CMP4:.*]] = cir.cmp(ge, %[[A4]], %[[B4]]) : !cir.float, !cir.bool -// CIR: cir.store %[[CMP4]], %[[X_PTR]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} %[[CMP4]], %[[X_PTR]] : !cir.bool, !cir.ptr -// CIR: %[[A5:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !cir.float -// CIR: %[[B5:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !cir.float +// CIR: %[[A5:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !cir.float +// CIR: %[[B5:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !cir.float // CIR: %[[CMP5:.*]] = cir.cmp(ne, %[[A5]], %[[B5]]) : !cir.float, !cir.bool -// CIR: cir.store %[[CMP5]], %[[X_PTR]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} %[[CMP5]], %[[X_PTR]] : !cir.bool, !cir.ptr -// CIR: %[[A6:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !cir.float -// CIR: %[[B6:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !cir.float +// CIR: %[[A6:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !cir.float +// CIR: %[[B6:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !cir.float // CIR: %[[CMP6:.*]] = cir.cmp(eq, %[[A6]], %[[B6]]) : !cir.float, !cir.bool -// CIR: cir.store %[[CMP6]], %[[X_PTR]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} %[[CMP6]], %[[X_PTR]] : !cir.bool, !cir.ptr // LLVM-LABEL: define void @_Z8c0_floatff(float %0, float %1) { // LLVM: %[[A_PTR:.*]] = alloca float @@ -350,8 +350,8 @@ void pointer_cmp(int *a, int *b) { // CIR: %[[A_PTR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["a", init] // CIR: %[[B_PTR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["b", init] -// CIR: %[[A1:.*]] = cir.load %[[A_PTR]] : !cir.ptr>, !cir.ptr -// CIR: %[[B1:.*]] = cir.load %[[B_PTR]] : !cir.ptr>, !cir.ptr +// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr>, !cir.ptr +// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr>, !cir.ptr // CIR: %{{.*}} = cir.cmp(gt, %[[A1]], %[[B1]]) : !cir.ptr, !cir.bool // CIR: cir.cmp(lt, {{.*}}, {{.*}}) : !cir.ptr, !cir.bool @@ -406,12 +406,12 @@ void bool_cmp(bool a, bool b) { // CIR: %[[B_PTR:.*]] = cir.alloca !cir.bool, !cir.ptr, ["b", init] // CIR: %[[X_PTR:.*]] = cir.alloca !cir.bool, !cir.ptr, ["x", init] -// CIR: %[[A1:.*]] = cir.load %[[A_PTR]] : !cir.ptr, !cir.bool +// CIR: %[[A1:.*]] = cir.load{{.*}} %[[A_PTR]] : !cir.ptr, !cir.bool // CIR: %[[A1_INT:.*]] = cir.cast(bool_to_int, %[[A1]] : !cir.bool), !s32i -// CIR: %[[B1:.*]] = cir.load %[[B_PTR]] : !cir.ptr, !cir.bool +// CIR: %[[B1:.*]] = cir.load{{.*}} %[[B_PTR]] : !cir.ptr, !cir.bool // CIR: %[[B1_INT:.*]] = cir.cast(bool_to_int, %[[B1]] : !cir.bool), !s32i // CIR: %{{.*}} = cir.cmp(gt, %[[A1_INT]], %[[B1_INT]]) : !s32i, !cir.bool -// CIR: cir.store {{.*}}, %[[X_PTR]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} {{.*}}, %[[X_PTR]] : !cir.bool, !cir.ptr // CIR: cir.cmp(lt // CIR: cir.cmp(ge diff --git a/clang/test/CIR/CodeGen/comma.c b/clang/test/CIR/CodeGen/comma.c index 7ce53eaf1a238..d811f5a72bddf 100644 --- a/clang/test/CIR/CodeGen/comma.c +++ b/clang/test/CIR/CodeGen/comma.c @@ -22,16 +22,16 @@ void comma(void) { // CIR: %[[F:.*]] = cir.alloca !cir.float, !cir.ptr, ["f"] // CIR: %[[I:.*]] = cir.alloca !s32i, !cir.ptr, ["i"] // CIR: %[[TRUE:.*]] = cir.const #true -// CIR: cir.store %[[TRUE]], %[[B]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} %[[TRUE]], %[[B]] : !cir.bool, !cir.ptr // CIR: %[[CHAR_INI_INIT:.*]] = cir.const #cir.int<65> : !s32i // CIR: %[[CHAR_VAL:.*]] = cir.cast(integral, %[[CHAR_INI_INIT]] : !s32i), !s8i -// CIR: cir.store %[[CHAR_VAL]], %[[C]] : !s8i, !cir.ptr +// CIR: cir.store{{.*}} %[[CHAR_VAL]], %[[C]] : !s8i, !cir.ptr // CIR: %[[FLOAT_VAL:.*]] = cir.const #cir.fp<3.140000e+00> : !cir.float -// CIR: cir.store %[[FLOAT_VAL]], %[[F]] : !cir.float, !cir.ptr +// CIR: cir.store{{.*}} %[[FLOAT_VAL]], %[[F]] : !cir.float, !cir.ptr // CIR: %[[INT_VAL:.*]] = cir.const #cir.int<42> : !s32i -// CIR: cir.store %[[INT_VAL]], %[[I]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[INT_VAL]], %[[I]] : !s32i, !cir.ptr // CIR: %[[HUNDRED:.*]] = cir.const #cir.int<100> : !s32i -// CIR: cir.store %[[HUNDRED]], %[[I]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[HUNDRED]], %[[I]] : !s32i, !cir.ptr // CIR: cir.return // LLVM-LABEL: define {{.*}}void @comma() { diff --git a/clang/test/CIR/CodeGen/compound_assign.cpp b/clang/test/CIR/CodeGen/compound_assign.cpp index c54eb9e626016..60442bcdf912e 100644 --- a/clang/test/CIR/CodeGen/compound_assign.cpp +++ b/clang/test/CIR/CodeGen/compound_assign.cpp @@ -22,25 +22,25 @@ int compound_assign(int b) { // CIR: cir.func @_Z15compound_assigni // CIR: %[[MUL:.*]] = cir.binop(mul, %{{.*}}, %{{.*}}) nsw : !s32i -// CIR: cir.store %[[MUL]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[MUL]], %{{.*}} : !s32i, !cir.ptr // CIR: %[[DIV:.*]] = cir.binop(div, %{{.*}}, %{{.*}}) : !s32i -// CIR: cir.store %[[DIV]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[DIV]], %{{.*}} : !s32i, !cir.ptr // CIR: %[[REM:.*]] = cir.binop(rem, %{{.*}}, %{{.*}}) : !s32i -// CIR: cir.store %[[REM]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[REM]], %{{.*}} : !s32i, !cir.ptr // CIR: %[[ADD:.*]] = cir.binop(add, %{{.*}}, %{{.*}}) nsw : !s32i -// CIR: cir.store %[[ADD]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ADD]], %{{.*}} : !s32i, !cir.ptr // CIR: %[[SUB:.*]] = cir.binop(sub, %{{.*}}, %{{.*}}) nsw : !s32i -// CIR: cir.store %[[SUB]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[SUB]], %{{.*}} : !s32i, !cir.ptr // CIR: %[[SHR:.*]] = cir.shift(right, %{{.*}} : !s32i, %{{.*}} : !s32i) -> !s32i -// CIR: cir.store %[[SHR]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[SHR]], %{{.*}} : !s32i, !cir.ptr // CIR: %[[SHL:.*]] = cir.shift(left, %{{.*}} : !s32i, %{{.*}} : !s32i) -> !s32i -// CIR: cir.store %[[SHL]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[SHL]], %{{.*}} : !s32i, !cir.ptr // CIR: %[[AND:.*]] = cir.binop(and, %{{.*}}, %{{.*}}) : !s32i -// CIR: cir.store %[[AND]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[AND]], %{{.*}} : !s32i, !cir.ptr // CIR: %[[XOR:.*]] = cir.binop(xor, %{{.*}}, %{{.*}}) : !s32i -// CIR: cir.store %[[XOR]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[XOR]], %{{.*}} : !s32i, !cir.ptr // CIR: %[[OR:.*]] = cir.binop(or, %{{.*}}, %{{.*}}) : !s32i -// CIR: cir.store %[[OR]], %{{.*}} : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[OR]], %{{.*}} : !s32i, !cir.ptr // LLVM: define {{.*}}i32 @_Z15compound_assigni // LLVM: %[[MUL:.*]] = mul nsw i32 %{{.*}}, %{{.*}} diff --git a/clang/test/CIR/CodeGen/forrange.cpp b/clang/test/CIR/CodeGen/forrange.cpp index 8a3570a35a325..6b6ccc79e59dd 100644 --- a/clang/test/CIR/CodeGen/forrange.cpp +++ b/clang/test/CIR/CodeGen/forrange.cpp @@ -23,27 +23,27 @@ void for_range() { // CIR: %[[BEGIN_ADDR:.*]] = cir.alloca !cir.ptr{{.*}} ["__begin1", init] // CIR: %[[END_ADDR:.*]] = cir.alloca !cir.ptr{{.*}} ["__end1", init] // CIR: %[[E_ADDR:.*]] = cir.alloca !cir.ptr{{.*}} ["e", init, const] -// CIR: cir.store %[[C_ADDR]], %[[RANGE_ADDR]] -// CIR: %[[C_REF:.*]] = cir.load %[[RANGE_ADDR]] +// CIR: cir.store{{.*}} %[[C_ADDR]], %[[RANGE_ADDR]] +// CIR: %[[C_REF:.*]] = cir.load{{.*}} %[[RANGE_ADDR]] // CIR: %[[BEGIN:.*]] = cir.call @_Z5beginR9Container(%[[C_REF]]) -// CIR: cir.store %[[BEGIN]], %[[BEGIN_ADDR]] -// CIR: %[[C_REF2:.*]] = cir.load %[[RANGE_ADDR]] +// CIR: cir.store{{.*}} %[[BEGIN]], %[[BEGIN_ADDR]] +// CIR: %[[C_REF2:.*]] = cir.load{{.*}} %[[RANGE_ADDR]] // CIR: %[[END:.*]] = cir.call @_Z3endR9Container(%[[C_REF2]]) -// CIR: cir.store %[[END]], %[[END_ADDR]] +// CIR: cir.store{{.*}} %[[END]], %[[END_ADDR]] // CIR: cir.for : cond { -// CIR: %[[BEGIN:.*]] = cir.load %[[BEGIN_ADDR]] -// CIR: %[[END:.*]] = cir.load %[[END_ADDR]] +// CIR: %[[BEGIN:.*]] = cir.load{{.*}} %[[BEGIN_ADDR]] +// CIR: %[[END:.*]] = cir.load{{.*}} %[[END_ADDR]] // CIR: %[[CMP:.*]] = cir.cmp(ne, %[[BEGIN]], %[[END]]) // CIR: cir.condition(%[[CMP]]) // CIR: } body { -// CIR: %[[E:.*]] = cir.load deref %[[BEGIN_ADDR]] -// CIR: cir.store %[[E]], %[[E_ADDR]] +// CIR: %[[E:.*]] = cir.load deref{{.*}} %[[BEGIN_ADDR]] +// CIR: cir.store{{.*}} %[[E]], %[[E_ADDR]] // CIR: cir.yield // CIR: } step { -// CIR: %[[BEGIN:.*]] = cir.load %[[BEGIN_ADDR]] +// CIR: %[[BEGIN:.*]] = cir.load{{.*}} %[[BEGIN_ADDR]] // CIR: %[[STEP:.*]] = cir.const #cir.int<1> // CIR: %[[NEXT:.*]] = cir.ptr_stride(%[[BEGIN]] {{.*}}, %[[STEP]] {{.*}}) -// CIR: cir.store %[[NEXT]], %[[BEGIN_ADDR]] +// CIR: cir.store{{.*}} %[[NEXT]], %[[BEGIN_ADDR]] // CIR: cir.yield // CIR: } // CIR: } @@ -66,27 +66,27 @@ void for_range2() { // CIR: %[[BEGIN_ADDR:.*]] = cir.alloca !cir.ptr{{.*}} ["__begin1", init] // CIR: %[[END_ADDR:.*]] = cir.alloca !cir.ptr{{.*}} ["__end1", init] // CIR: %[[E_ADDR:.*]] = cir.alloca !cir.ptr{{.*}} ["e", init, const] -// CIR: cir.store %[[C_ADDR]], %[[RANGE_ADDR]] -// CIR: %[[C_REF:.*]] = cir.load %[[RANGE_ADDR]] +// CIR: cir.store{{.*}} %[[C_ADDR]], %[[RANGE_ADDR]] +// CIR: %[[C_REF:.*]] = cir.load{{.*}} %[[RANGE_ADDR]] // CIR: %[[BEGIN:.*]] = cir.call @_ZN2C25beginEv(%[[C_REF]]) -// CIR: cir.store %[[BEGIN]], %[[BEGIN_ADDR]] -// CIR: %[[C_REF2:.*]] = cir.load %[[RANGE_ADDR]] +// CIR: cir.store{{.*}} %[[BEGIN]], %[[BEGIN_ADDR]] +// CIR: %[[C_REF2:.*]] = cir.load{{.*}} %[[RANGE_ADDR]] // CIR: %[[END:.*]] = cir.call @_ZN2C23endEv(%[[C_REF2]]) -// CIR: cir.store %[[END]], %[[END_ADDR]] +// CIR: cir.store{{.*}} %[[END]], %[[END_ADDR]] // CIR: cir.for : cond { -// CIR: %[[BEGIN:.*]] = cir.load %[[BEGIN_ADDR]] -// CIR: %[[END:.*]] = cir.load %[[END_ADDR]] +// CIR: %[[BEGIN:.*]] = cir.load{{.*}} %[[BEGIN_ADDR]] +// CIR: %[[END:.*]] = cir.load{{.*}} %[[END_ADDR]] // CIR: %[[CMP:.*]] = cir.cmp(ne, %[[BEGIN]], %[[END]]) // CIR: cir.condition(%[[CMP]]) // CIR: } body { -// CIR: %[[E:.*]] = cir.load deref %[[BEGIN_ADDR]] -// CIR: cir.store %[[E]], %[[E_ADDR]] +// CIR: %[[E:.*]] = cir.load deref{{.*}} %[[BEGIN_ADDR]] +// CIR: cir.store{{.*}} %[[E]], %[[E_ADDR]] // CIR: cir.yield // CIR: } step { -// CIR: %[[BEGIN:.*]] = cir.load %[[BEGIN_ADDR]] +// CIR: %[[BEGIN:.*]] = cir.load{{.*}} %[[BEGIN_ADDR]] // CIR: %[[STEP:.*]] = cir.const #cir.int<1> // CIR: %[[NEXT:.*]] = cir.ptr_stride(%[[BEGIN]] {{.*}}, %[[STEP]] {{.*}}) -// CIR: cir.store %[[NEXT]], %[[BEGIN_ADDR]] +// CIR: cir.store{{.*}} %[[NEXT]], %[[BEGIN_ADDR]] // CIR: cir.yield // CIR: } // CIR: } @@ -118,13 +118,13 @@ void for_range3() { // CIR: %[[BEGIN_ADDR:.*]] = cir.alloca !rec_Iterator, !cir.ptr{{.*}} ["__begin1"] // CIR: %[[END_ADDR:.*]] = cir.alloca !rec_Iterator, !cir.ptr{{.*}} ["__end1"] // CIR: %[[E_ADDR:.*]] = cir.alloca !cir.ptr{{.*}} ["e", init, const] -// CIR: cir.store %[[C_ADDR]], %[[RANGE_ADDR]] +// CIR: cir.store{{.*}} %[[C_ADDR]], %[[RANGE_ADDR]] // CIR: cir.for : cond { // CIR: %[[ITER_NE:.*]] = cir.call @_ZNK8IteratorneERKS_(%[[BEGIN_ADDR]], %[[END_ADDR]]) // CIR: cir.condition(%[[ITER_NE]]) // CIR: } body { // CIR: %[[E:.*]] = cir.call @_ZN8IteratordeEv(%[[BEGIN_ADDR]]) -// CIR: cir.store %[[E]], %[[E_ADDR]] +// CIR: cir.store{{.*}} %[[E]], %[[E_ADDR]] // CIR: cir.yield // CIR: } step { // CIR: %[[ITER_NEXT:.*]] = cir.call @_ZN8IteratorppEv(%[[BEGIN_ADDR]]) diff --git a/clang/test/CIR/CodeGen/if.cpp b/clang/test/CIR/CodeGen/if.cpp index 42855354fab87..c78ca103de63b 100644 --- a/clang/test/CIR/CodeGen/if.cpp +++ b/clang/test/CIR/CodeGen/if.cpp @@ -16,11 +16,11 @@ int if0(bool a) { // CIR: cir.func @_Z3if0b(%arg0: !cir.bool loc({{.*}})) -> !s32i // CIR: cir.scope { -// CIR: %4 = cir.load %0 : !cir.ptr, !cir.bool +// CIR: %4 = cir.load{{.*}} %0 : !cir.ptr, !cir.bool // CIR-NEXT: cir.if %4 { // CIR-NEXT: %5 = cir.const #cir.int<2> : !s32i -// CIR-NEXT: cir.store %5, %1 : !s32i, !cir.ptr -// CIR-NEXT: %6 = cir.load %1 : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %5, %1 : !s32i, !cir.ptr +// CIR-NEXT: %6 = cir.load{{.*}} %1 : !cir.ptr, !s32i // CIR-NEXT: cir.return %6 : !s32i // CIR-NEXT: } // CIR-NEXT: } @@ -73,14 +73,14 @@ void if1(int a) { // CIR: cir.func @_Z3if1i(%arg0: !s32i loc({{.*}})) // CIR: cir.scope { -// CIR: %3 = cir.load %0 : !cir.ptr, !s32i +// CIR: %3 = cir.load{{.*}} %0 : !cir.ptr, !s32i // CIR: %4 = cir.cast(int_to_bool, %3 : !s32i), !cir.bool // CIR-NEXT: cir.if %4 { // CIR-NEXT: %5 = cir.const #cir.int<3> : !s32i -// CIR-NEXT: cir.store %5, %1 : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %5, %1 : !s32i, !cir.ptr // CIR-NEXT: } else { // CIR-NEXT: %5 = cir.const #cir.int<4> : !s32i -// CIR-NEXT: cir.store %5, %1 : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %5, %1 : !s32i, !cir.ptr // CIR-NEXT: } // CIR: } @@ -140,28 +140,28 @@ void if2(int a, bool b, bool c) { // CIR: cir.func @_Z3if2ibb(%arg0: !s32i loc({{.*}}), %arg1: !cir.bool loc({{.*}}), %arg2: !cir.bool loc({{.*}})) // CIR: cir.scope { -// CIR: %5 = cir.load %0 : !cir.ptr, !s32i +// CIR: %5 = cir.load{{.*}} %0 : !cir.ptr, !s32i // CIR: %6 = cir.cast(int_to_bool, %5 : !s32i), !cir.bool // CIR: cir.if %6 { // CIR: %7 = cir.const #cir.int<3> : !s32i -// CIR: cir.store %7, %3 : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %7, %3 : !s32i, !cir.ptr // CIR: cir.scope { -// CIR: %8 = cir.load %1 : !cir.ptr, !cir.bool +// CIR: %8 = cir.load{{.*}} %1 : !cir.ptr, !cir.bool // CIR-NEXT: cir.if %8 { // CIR-NEXT: %9 = cir.const #cir.int<8> : !s32i -// CIR-NEXT: cir.store %9, %3 : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %9, %3 : !s32i, !cir.ptr // CIR-NEXT: } // CIR: } // CIR: } else { // CIR: cir.scope { -// CIR: %8 = cir.load %2 : !cir.ptr, !cir.bool +// CIR: %8 = cir.load{{.*}} %2 : !cir.ptr, !cir.bool // CIR-NEXT: cir.if %8 { // CIR-NEXT: %9 = cir.const #cir.int<14> : !s32i -// CIR-NEXT: cir.store %9, %3 : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %9, %3 : !s32i, !cir.ptr // CIR-NEXT: } // CIR: } // CIR: %7 = cir.const #cir.int<4> : !s32i -// CIR: cir.store %7, %3 : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %7, %3 : !s32i, !cir.ptr // CIR: } // CIR: } @@ -265,22 +265,22 @@ int if_init() { // CIR: cir.scope { // CIR: %[[X:.*]] = cir.alloca !s32i, !cir.ptr, // CIR: %[[CONST42:.*]] = cir.const #cir.int<42> : !s32i -// CIR: cir.store %[[CONST42]], %[[X]] : !s32i, !cir.ptr -// CIR: %[[X_VAL:.*]] = cir.load %[[X]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[CONST42]], %[[X]] : !s32i, !cir.ptr +// CIR: %[[X_VAL:.*]] = cir.load{{.*}} %[[X]] : !cir.ptr, !s32i // CIR: %[[COND:.*]] = cir.cast(int_to_bool, %[[X_VAL]] : !s32i), !cir.bool // CIR: cir.if %[[COND]] { -// CIR: %[[X_IF:.*]] = cir.load %[[X]] : !cir.ptr, !s32i +// CIR: %[[X_IF:.*]] = cir.load{{.*}} %[[X]] : !cir.ptr, !s32i // CIR: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i // CIR: %[[ADD:.*]] = cir.binop(add, %[[X_IF]], %[[ONE]]) nsw : !s32i -// CIR: cir.store %[[ADD]], %[[RETVAL]] : !s32i, !cir.ptr -// CIR: %[[RETVAL_LOAD1:.*]] = cir.load %[[RETVAL]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[ADD]], %[[RETVAL]] : !s32i, !cir.ptr +// CIR: %[[RETVAL_LOAD1:.*]] = cir.load{{.*}} %[[RETVAL]] : !cir.ptr, !s32i // CIR: cir.return %[[RETVAL_LOAD1]] : !s32i // CIR: } else { -// CIR: %[[X_ELSE:.*]] = cir.load %[[X]] : !cir.ptr, !s32i +// CIR: %[[X_ELSE:.*]] = cir.load{{.*}} %[[X]] : !cir.ptr, !s32i // CIR: %[[ONE2:.*]] = cir.const #cir.int<1> : !s32i // CIR: %[[SUB:.*]] = cir.binop(sub, %[[X_ELSE]], %[[ONE2]]) nsw : !s32i -// CIR: cir.store %[[SUB]], %[[RETVAL]] : !s32i, !cir.ptr -// CIR: %[[RETVAL_LOAD2:.*]] = cir.load %[[RETVAL]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[SUB]], %[[RETVAL]] : !s32i, !cir.ptr +// CIR: %[[RETVAL_LOAD2:.*]] = cir.load{{.*}} %[[RETVAL]] : !cir.ptr, !s32i // CIR: cir.return %[[RETVAL_LOAD2]] : !s32i // CIR: } // CIR: } diff --git a/clang/test/CIR/CodeGen/local-vars.cpp b/clang/test/CIR/CodeGen/local-vars.cpp index 45c63216b5126..42d6433645354 100644 --- a/clang/test/CIR/CodeGen/local-vars.cpp +++ b/clang/test/CIR/CodeGen/local-vars.cpp @@ -1,4 +1,5 @@ -// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o - 2>&1 | FileCheck %s +// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t-cir.ll +// RUN: FileCheck -input-file=%t-cir.ll %s void test() { int i = 1; @@ -40,26 +41,26 @@ void test() { // CHECK: %[[UID_PTR:.*]] = cir.alloca !cir.double, !cir.ptr, ["uid"] {alignment = 8 : i64} // CHECK: %[[UIB_PTR:.*]] = cir.alloca !cir.bool, !cir.ptr, ["uib"] {alignment = 1 : i64} // CHECK: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i -// CHECK: cir.store %[[ONE]], %[[I_PTR]] : !s32i, !cir.ptr +// CHECK: cir.store align(4) %[[ONE]], %[[I_PTR]] : !s32i, !cir.ptr // CHECK: %[[TWO:.*]] = cir.const #cir.int<2> : !s64i -// CHECK: cir.store %[[TWO]], %[[L_PTR]] : !s64i, !cir.ptr +// CHECK: cir.store align(8) %[[TWO]], %[[L_PTR]] : !s64i, !cir.ptr // CHECK: %[[THREE:.*]] = cir.const #cir.fp<3.0{{.*}}> : !cir.float -// CHECK: cir.store %[[THREE]], %[[F_PTR]] : !cir.float, !cir.ptr +// CHECK: cir.store align(4) %[[THREE]], %[[F_PTR]] : !cir.float, !cir.ptr // CHECK: %[[FOUR:.*]] = cir.const #cir.fp<4.0{{.*}}> : !cir.double -// CHECK: cir.store %[[FOUR]], %[[D_PTR]] : !cir.double, !cir.ptr +// CHECK: cir.store align(8) %[[FOUR]], %[[D_PTR]] : !cir.double, !cir.ptr // CHECK: %[[TRUE:.*]] = cir.const #true -// CHECK: cir.store %[[TRUE]], %[[B1_PTR]] : !cir.bool, !cir.ptr +// CHECK: cir.store align(1) %[[TRUE]], %[[B1_PTR]] : !cir.bool, !cir.ptr // CHECK: %[[FALSE:.*]] = cir.const #false -// CHECK: cir.store %[[FALSE]], %[[B2_PTR]] : !cir.bool, !cir.ptr +// CHECK: cir.store align(1) %[[FALSE]], %[[B2_PTR]] : !cir.bool, !cir.ptr // CHECK: %[[ONEC:.*]] = cir.const #cir.int<1> : !s32i -// CHECK: cir.store %[[ONEC]], %[[CI_PTR]] : !s32i, !cir.ptr +// CHECK: cir.store align(4) %[[ONEC]], %[[CI_PTR]] : !s32i, !cir.ptr // CHECK: %[[TWOC:.*]] = cir.const #cir.int<2> : !s64i -// CHECK: cir.store %[[TWOC]], %[[CL_PTR]] : !s64i, !cir.ptr +// CHECK: cir.store align(8) %[[TWOC]], %[[CL_PTR]] : !s64i, !cir.ptr // CHECK: %[[THREEC:.*]] = cir.const #cir.fp<3.0{{.*}}> : !cir.float -// CHECK: cir.store %[[THREEC]], %[[CF_PTR]] : !cir.float, !cir.ptr +// CHECK: cir.store align(4) %[[THREEC]], %[[CF_PTR]] : !cir.float, !cir.ptr // CHECK: %[[FOURC:.*]] = cir.const #cir.fp<4.0{{.*}}> : !cir.double -// CHECK: cir.store %[[FOURC]], %[[CD_PTR]] : !cir.double, !cir.ptr +// CHECK: cir.store align(8) %[[FOURC]], %[[CD_PTR]] : !cir.double, !cir.ptr // CHECK: %[[TRUEC:.*]] = cir.const #true -// CHECK: cir.store %[[TRUEC]], %[[CB1_PTR]] : !cir.bool, !cir.ptr +// CHECK: cir.store align(1) %[[TRUEC]], %[[CB1_PTR]] : !cir.bool, !cir.ptr // CHECK: %[[FALSEC:.*]] = cir.const #false -// CHECK: cir.store %[[FALSEC]], %[[CB2_PTR]] : !cir.bool, !cir.ptr +// CHECK: cir.store align(1) %[[FALSEC]], %[[CB2_PTR]] : !cir.bool, !cir.ptr diff --git a/clang/test/CIR/CodeGen/loop.cpp b/clang/test/CIR/CodeGen/loop.cpp index e0165c91d0a75..ba117c54b743d 100644 --- a/clang/test/CIR/CodeGen/loop.cpp +++ b/clang/test/CIR/CodeGen/loop.cpp @@ -54,7 +54,7 @@ void l1() { // CIR-NEXT: cir.scope { // CIR-NEXT: %[[I:.*]] = cir.alloca !s32i, !cir.ptr, ["i", init] {alignment = 4 : i64} // CIR-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i -// CIR-NEXT: cir.store %[[ZERO]], %[[I]] : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ZERO]], %[[I]] : !s32i, !cir.ptr // CIR-NEXT: cir.for : cond { // CIR-NEXT: %[[TRUE:.*]] = cir.const #true // CIR-NEXT: cir.condition(%[[TRUE]]) @@ -107,7 +107,7 @@ void l2() { // CIR-NEXT: cir.scope { // CIR-NEXT: %[[I:.*]] = cir.alloca !s32i, !cir.ptr, ["i", init] {alignment = 4 : i64} // CIR-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i -// CIR-NEXT: cir.store %[[ZERO]], %[[I]] : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ZERO]], %[[I]] : !s32i, !cir.ptr // CIR-NEXT: } // CIR-NEXT: cir.yield // CIR-NEXT: } step { @@ -156,7 +156,7 @@ void l3() { // CIR-NEXT: cir.condition(%[[TRUE]]) // CIR-NEXT: } body { // CIR-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i -// CIR-NEXT: cir.store %[[ZERO]], %[[I]] : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ZERO]], %[[I]] : !s32i, !cir.ptr // CIR-NEXT: cir.yield // CIR-NEXT: } step { // CIR-NEXT: cir.yield @@ -203,30 +203,30 @@ void l4() { // CIR: %[[BEGIN_ADDR:.*]] = cir.alloca {{.*}} ["__begin1", init] // CIR: %[[END_ADDR:.*]] = cir.alloca {{.*}} ["__end1", init] // CIR: %[[N_ADDR:.*]] = cir.alloca {{.*}} ["n", init] -// CIR: cir.store %[[A_ADDR]], %[[RANGE_ADDR]] -// CIR: %[[RANGE_LOAD:.*]] = cir.load %[[RANGE_ADDR]] +// CIR: cir.store{{.*}} %[[A_ADDR]], %[[RANGE_ADDR]] +// CIR: %[[RANGE_LOAD:.*]] = cir.load{{.*}} %[[RANGE_ADDR]] // CIR: %[[RANGE_CAST:.*]] = cir.cast(array_to_ptrdecay, %[[RANGE_LOAD]] : {{.*}}) -// CIR: cir.store %[[RANGE_CAST]], %[[BEGIN_ADDR]] -// CIR: %[[BEGIN:.*]] = cir.load %[[RANGE_ADDR]] +// CIR: cir.store{{.*}} %[[RANGE_CAST]], %[[BEGIN_ADDR]] +// CIR: %[[BEGIN:.*]] = cir.load{{.*}} %[[RANGE_ADDR]] // CIR: %[[BEGIN_CAST:.*]] = cir.cast(array_to_ptrdecay, %[[BEGIN]] : {{.*}}) // CIR: %[[TEN:.*]] = cir.const #cir.int<10> // CIR: %[[END_PTR:.*]] = cir.ptr_stride(%[[BEGIN_CAST]] : {{.*}}, %[[TEN]] : {{.*}}) -// CIR: cir.store %[[END_PTR]], %[[END_ADDR]] +// CIR: cir.store{{.*}} %[[END_PTR]], %[[END_ADDR]] // CIR: cir.for : cond { -// CIR: %[[CUR:.*]] = cir.load %[[BEGIN_ADDR]] -// CIR: %[[END:.*]] = cir.load %[[END_ADDR]] +// CIR: %[[CUR:.*]] = cir.load{{.*}} %[[BEGIN_ADDR]] +// CIR: %[[END:.*]] = cir.load{{.*}} %[[END_ADDR]] // CIR: %[[CMP:.*]] = cir.cmp(ne, %[[CUR]], %[[END]]) // CIR: cir.condition(%[[CMP]]) // CIR: } body { -// CIR: %[[CUR:.*]] = cir.load deref %[[BEGIN_ADDR]] -// CIR: %[[N:.*]] = cir.load %[[CUR]] -// CIR: cir.store %[[N]], %[[N_ADDR]] +// CIR: %[[CUR:.*]] = cir.load deref{{.*}} %[[BEGIN_ADDR]] +// CIR: %[[N:.*]] = cir.load{{.*}} %[[CUR]] +// CIR: cir.store{{.*}} %[[N]], %[[N_ADDR]] // CIR: cir.yield // CIR: } step { -// CIR: %[[CUR:.*]] = cir.load %[[BEGIN_ADDR]] +// CIR: %[[CUR:.*]] = cir.load{{.*}} %[[BEGIN_ADDR]] // CIR: %[[ONE:.*]] = cir.const #cir.int<1> // CIR: %[[NEXT:.*]] = cir.ptr_stride(%[[CUR]] : {{.*}}, %[[ONE]] : {{.*}}) -// CIR: cir.store %[[NEXT]], %[[BEGIN_ADDR]] +// CIR: cir.store{{.*}} %[[NEXT]], %[[BEGIN_ADDR]] // CIR: cir.yield // CIR: } // CIR: } @@ -314,43 +314,43 @@ void l5() { // CIR: %[[X_ADDR:.*]] = cir.alloca {{.*}} ["x", init] // CIR: %[[ARR_CAST:.*]] = cir.cast(array_to_ptrdecay, %[[ARR_ADDR]] : {{.*}}) // CIR: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i -// CIR: cir.store %[[ONE]], %[[ARR_CAST]] +// CIR: cir.store{{.*}} %[[ONE]], %[[ARR_CAST]] // CIR: %[[OFFSET1:.*]] = cir.const #cir.int<1> : !s64i // CIR: %[[STRIDE:.*]] = cir.ptr_stride(%[[ARR_CAST]] : {{.*}}, %[[OFFSET1]] : {{.*}}) // CIR: %[[TWO:.*]] = cir.const #cir.int<2> : !s32i -// CIR: cir.store %[[TWO]], %[[STRIDE]] +// CIR: cir.store{{.*}} %[[TWO]], %[[STRIDE]] // CIR: %[[OFFSET2:.*]] = cir.const #cir.int<2> : !s64i // CIR: %[[STRIDE2:.*]] = cir.ptr_stride(%[[ARR_CAST]] : {{.*}}, %[[OFFSET2]] : {{.*}}) // CIR: %[[THREE:.*]] = cir.const #cir.int<3> : !s32i -// CIR: cir.store %[[THREE]], %[[STRIDE2]] +// CIR: cir.store{{.*}} %[[THREE]], %[[STRIDE2]] // CIR: %[[OFFSET3:.*]] = cir.const #cir.int<3> : !s64i // CIR: %[[STRIDE3:.*]] = cir.ptr_stride(%[[ARR_CAST]] : {{.*}}, %[[OFFSET3]] : {{.*}}) // CIR: %[[FOUR:.*]] = cir.const #cir.int<4> : !s32i -// CIR: cir.store %[[FOUR]], %[[STRIDE3]] -// CIR: cir.store %[[ARR_ADDR]], %[[RANGE_ADDR]] -// CIR: %[[RANGE_LOAD:.*]] = cir.load %[[RANGE_ADDR]] +// CIR: cir.store{{.*}} %[[FOUR]], %[[STRIDE3]] +// CIR: cir.store{{.*}} %[[ARR_ADDR]], %[[RANGE_ADDR]] +// CIR: %[[RANGE_LOAD:.*]] = cir.load{{.*}} %[[RANGE_ADDR]] // CIR: %[[RANGE_CAST:.*]] = cir.cast(array_to_ptrdecay, %[[RANGE_LOAD]] : {{.*}}) -// CIR: cir.store %[[RANGE_CAST]], %[[BEGIN_ADDR]] -// CIR: %[[BEGIN:.*]] = cir.load %[[RANGE_ADDR]] +// CIR: cir.store{{.*}} %[[RANGE_CAST]], %[[BEGIN_ADDR]] +// CIR: %[[BEGIN:.*]] = cir.load{{.*}} %[[RANGE_ADDR]] // CIR: %[[BEGIN_CAST:.*]] = cir.cast(array_to_ptrdecay, %[[BEGIN]] : {{.*}}) // CIR: %[[FOUR:.*]] = cir.const #cir.int<4> : !s64i // CIR: %[[END_PTR:.*]] = cir.ptr_stride(%[[BEGIN_CAST]] : {{.*}}, %[[FOUR]] : {{.*}}) -// CIR: cir.store %[[END_PTR]], %[[END_ADDR]] +// CIR: cir.store{{.*}} %[[END_PTR]], %[[END_ADDR]] // CIR: cir.for : cond { -// CIR: %[[CUR:.*]] = cir.load %[[BEGIN_ADDR]] -// CIR: %[[END:.*]] = cir.load %[[END_ADDR]] +// CIR: %[[CUR:.*]] = cir.load{{.*}} %[[BEGIN_ADDR]] +// CIR: %[[END:.*]] = cir.load{{.*}} %[[END_ADDR]] // CIR: %[[CMP:.*]] = cir.cmp(ne, %[[CUR]], %[[END]]) // CIR: cir.condition(%[[CMP]]) // CIR: } body { -// CIR: %[[CUR:.*]] = cir.load deref %[[BEGIN_ADDR]] -// CIR: %[[X:.*]] = cir.load %[[CUR]] -// CIR: cir.store %[[X]], %[[X_ADDR]] +// CIR: %[[CUR:.*]] = cir.load deref{{.*}} %[[BEGIN_ADDR]] +// CIR: %[[X:.*]] = cir.load{{.*}} %[[CUR]] +// CIR: cir.store{{.*}} %[[X]], %[[X_ADDR]] // CIR: cir.yield // CIR: } step { -// CIR: %[[CUR:.*]] = cir.load %[[BEGIN_ADDR]] +// CIR: %[[CUR:.*]] = cir.load{{.*}} %[[BEGIN_ADDR]] // CIR: %[[ONE:.*]] = cir.const #cir.int<1> // CIR: %[[NEXT:.*]] = cir.ptr_stride(%[[CUR]] : {{.*}}, %[[ONE]] : {{.*}}) -// CIR: cir.store %[[NEXT]], %[[BEGIN_ADDR]] +// CIR: cir.store{{.*}} %[[NEXT]], %[[BEGIN_ADDR]] // CIR: cir.yield // CIR: } // CIR: } @@ -528,7 +528,7 @@ void unreachable_after_continue() { // CIR: cir.continue // CIR: ^bb1: // no predecessors // CIR: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i -// CIR: cir.store %[[ONE]], %[[X]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ONE]], %[[X]] : !s32i, !cir.ptr // CIR: cir.yield // CIR: } // CIR: cir.yield @@ -588,7 +588,7 @@ void unreachable_after_break() { // CIR: cir.break // CIR: ^bb1: // no predecessors // CIR: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i -// CIR: cir.store %[[ONE]], %[[X]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ONE]], %[[X]] : !s32i, !cir.ptr // CIR: cir.yield // CIR: } // CIR: cir.yield diff --git a/clang/test/CIR/CodeGen/namespace.cpp b/clang/test/CIR/CodeGen/namespace.cpp index c89adcbfc7811..bfb4e37c2fa74 100644 --- a/clang/test/CIR/CodeGen/namespace.cpp +++ b/clang/test/CIR/CodeGen/namespace.cpp @@ -43,10 +43,10 @@ int f4(void) { // CHECK: cir.call @_ZN4test2f2Ev() // CHECK: cir.call @_ZN4test5test22f3Ev() // CHECK: %[[G1_ADDR:.*]] = cir.get_global @_ZN12_GLOBAL__N_12g1E : !cir.ptr -// CHECK: %[[G1_VAL:.*]] = cir.load %[[G1_ADDR]] : !cir.ptr, !s32i +// CHECK: %[[G1_VAL:.*]] = cir.load{{.*}} %[[G1_ADDR]] : !cir.ptr, !s32i // CHECK: %[[G2_ADDR:.*]] = cir.get_global @_ZN4test2g2E : !cir.ptr -// CHECK: %[[G2_VAL:.*]] = cir.load %[[G2_ADDR]] : !cir.ptr, !s32i +// CHECK: %[[G2_VAL:.*]] = cir.load{{.*}} %[[G2_ADDR]] : !cir.ptr, !s32i // CHECK: %[[SUM:.*]] = cir.binop(add, %[[G1_VAL]], %[[G2_VAL]]) nsw : !s32i // CHECK: %[[G3_ADDR:.*]] = cir.get_global @_ZN4test5test22g3E : !cir.ptr -// CHECK: %[[G3_VAL:.*]] = cir.load %[[G3_ADDR]] : !cir.ptr, !s32i +// CHECK: %[[G3_VAL:.*]] = cir.load{{.*}} %[[G3_ADDR]] : !cir.ptr, !s32i // CHECK: %[[SUM2:.*]] = cir.binop(add, %[[SUM]], %[[G3_VAL]]) nsw : !s32i diff --git a/clang/test/CIR/CodeGen/nullptr-init.cpp b/clang/test/CIR/CodeGen/nullptr-init.cpp index ed1a814e94ee9..76965ce78469e 100644 --- a/clang/test/CIR/CodeGen/nullptr-init.cpp +++ b/clang/test/CIR/CodeGen/nullptr-init.cpp @@ -16,11 +16,11 @@ void t1() { // CIR-NEXT: %[[P2:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["p2", init] {alignment = 8 : i64} // CIR-NEXT: %[[P3:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["p3", init] {alignment = 8 : i64} // CIR-NEXT: %[[NULLPTR1:.*]] = cir.const #cir.ptr : !cir.ptr -// CIR-NEXT: cir.store %[[NULLPTR1]], %[[P1]] : !cir.ptr, !cir.ptr> +// CIR-NEXT: cir.store{{.*}} %[[NULLPTR1]], %[[P1]] : !cir.ptr, !cir.ptr> // CIR-NEXT: %[[NULLPTR2:.*]] = cir.const #cir.ptr : !cir.ptr -// CIR-NEXT: cir.store %[[NULLPTR2]], %[[P2]] : !cir.ptr, !cir.ptr> +// CIR-NEXT: cir.store{{.*}} %[[NULLPTR2]], %[[P2]] : !cir.ptr, !cir.ptr> // CIR-NEXT: %[[NULLPTR3:.*]] = cir.const #cir.ptr : !cir.ptr -// CIR-NEXT: cir.store %[[NULLPTR3]], %[[P3]] : !cir.ptr, !cir.ptr> +// CIR-NEXT: cir.store{{.*}} %[[NULLPTR3]], %[[P3]] : !cir.ptr, !cir.ptr> // CIR-NEXT: cir.return // CIR-NEXT: } diff --git a/clang/test/CIR/CodeGen/pointers.cpp b/clang/test/CIR/CodeGen/pointers.cpp index 06beecf076e20..dcfcc723f4da1 100644 --- a/clang/test/CIR/CodeGen/pointers.cpp +++ b/clang/test/CIR/CodeGen/pointers.cpp @@ -18,12 +18,12 @@ void foo(int *iptr, char *cptr, unsigned ustride) { // CHECK: %[[#NEGSTRIDE:]] = cir.unary(minus, %[[#STRIDE]]) : !s32i, !s32i // CHECK: cir.ptr_stride(%{{.+}} : !cir.ptr, %[[#NEGSTRIDE]] : !s32i), !cir.ptr iptr + ustride; - // CHECK: %[[#STRIDE:]] = cir.load %{{.+}} : !cir.ptr, !u32i + // CHECK: %[[#STRIDE:]] = cir.load{{.*}} %{{.+}} : !cir.ptr, !u32i // CHECK: cir.ptr_stride(%{{.+}} : !cir.ptr, %[[#STRIDE]] : !u32i), !cir.ptr // Must convert unsigned stride to a signed one. iptr - ustride; - // CHECK: %[[#STRIDE:]] = cir.load %{{.+}} : !cir.ptr, !u32i + // CHECK: %[[#STRIDE:]] = cir.load{{.*}} %{{.+}} : !cir.ptr, !u32i // CHECK: %[[#SIGNSTRIDE:]] = cir.cast(integral, %[[#STRIDE]] : !u32i), !s32i // CHECK: %[[#NEGSTRIDE:]] = cir.unary(minus, %[[#SIGNSTRIDE]]) : !s32i, !s32i // CHECK: cir.ptr_stride(%{{.+}} : !cir.ptr, %[[#NEGSTRIDE]] : !s32i), !cir.ptr @@ -45,7 +45,7 @@ void testPointerSubscriptAccess(int *ptr) { // CHECK: testPointerSubscriptAccess ptr[1]; // CHECK: %[[#STRIDE:]] = cir.const #cir.int<1> : !s32i - // CHECK: %[[#PTR:]] = cir.load %{{.+}} : !cir.ptr>, !cir.ptr + // CHECK: %[[#PTR:]] = cir.load{{.*}} %{{.+}} : !cir.ptr>, !cir.ptr // CHECK: cir.ptr_stride(%[[#PTR]] : !cir.ptr, %[[#STRIDE]] : !s32i), !cir.ptr } @@ -54,9 +54,9 @@ void testPointerMultiDimSubscriptAccess(int **ptr) { ptr[1][2]; // CHECK: %[[#STRIDE2:]] = cir.const #cir.int<2> : !s32i // CHECK: %[[#STRIDE1:]] = cir.const #cir.int<1> : !s32i - // CHECK: %[[#PTR1:]] = cir.load %{{.+}} : !cir.ptr>>, !cir.ptr> + // CHECK: %[[#PTR1:]] = cir.load{{.*}} %{{.+}} : !cir.ptr>>, !cir.ptr> // CHECK: %[[#PTR2:]] = cir.ptr_stride(%[[#PTR1]] : !cir.ptr>, %[[#STRIDE1]] : !s32i), !cir.ptr> - // CHECK: %[[#PTR3:]] = cir.load %[[#PTR2]] : !cir.ptr>, !cir.ptr + // CHECK: %[[#PTR3:]] = cir.load{{.*}} %[[#PTR2]] : !cir.ptr>, !cir.ptr // CHECK: cir.ptr_stride(%[[#PTR3]] : !cir.ptr, %[[#STRIDE2]] : !s32i), !cir.ptr } @@ -72,6 +72,6 @@ int *testGnuNullPtrArithmetic(unsigned n) { // CHECK: testGnuNullPtrArithmetic return NULLPTRINT + n; // CHECK: %[[NULLPTR:.*]] = cir.const #cir.ptr : !cir.ptr - // CHECK: %[[N:.*]] = cir.load %{{.*}} : !cir.ptr, !u32i + // CHECK: %[[N:.*]] = cir.load{{.*}} %{{.*}} : !cir.ptr, !u32i // CHECK: %[[RESULT:.*]] = cir.ptr_stride(%[[NULLPTR]] : !cir.ptr, %[[N]] : !u32i), !cir.ptr } diff --git a/clang/test/CIR/CodeGen/struct.c b/clang/test/CIR/CodeGen/struct.c index 725b56a068488..9c4a730d19a83 100644 --- a/clang/test/CIR/CodeGen/struct.c +++ b/clang/test/CIR/CodeGen/struct.c @@ -191,16 +191,16 @@ char f3(int a) { // CIR: cir.func @f3(%[[ARG_A:.*]]: !s32i // CIR-NEXT: %[[A_ADDR:.*]] = cir.alloca {{.*}} ["a", init] {alignment = 4 : i64} // CIR-NEXT: %[[RETVAL_ADDR:.*]] = cir.alloca {{.*}} ["__retval"] {alignment = 1 : i64} -// CIR-NEXT: cir.store %[[ARG_A]], %[[A_ADDR]] -// CIR-NEXT: %[[A_VAL:.*]] = cir.load %[[A_ADDR]] +// CIR-NEXT: cir.store{{.*}} %[[ARG_A]], %[[A_ADDR]] +// CIR-NEXT: %[[A_VAL:.*]] = cir.load{{.*}} %[[A_ADDR]] // CIR-NEXT: %[[CS:.*]] = cir.get_global @cs // CIR-NEXT: %[[CS_A:.*]] = cir.get_member %[[CS]][0] {name = "a"} -// CIR-NEXT: cir.store %[[A_VAL]], %[[CS_A]] +// CIR-NEXT: cir.store{{.*}} %[[A_VAL]], %[[CS_A]] // CIR-NEXT: %[[CS2:.*]] = cir.get_global @cs // CIR-NEXT: %[[CS_B:.*]] = cir.get_member %[[CS2]][1] {name = "b"} -// CIR-NEXT: %[[CS_B_VAL:.*]] = cir.load %[[CS_B]] -// CIR-NEXT: cir.store %[[CS_B_VAL]], %[[RETVAL_ADDR]] -// CIR-NEXT: %[[RETVAL:.*]] = cir.load %[[RETVAL_ADDR]] +// CIR-NEXT: %[[CS_B_VAL:.*]] = cir.load{{.*}} %[[CS_B]] +// CIR-NEXT: cir.store{{.*}} %[[CS_B_VAL]], %[[RETVAL_ADDR]] +// CIR-NEXT: %[[RETVAL:.*]] = cir.load{{.*}} %[[RETVAL_ADDR]] // CIR-NEXT: cir.return %[[RETVAL]] // LLVM: define i8 @f3(i32 %[[ARG_A:.*]]) @@ -209,7 +209,7 @@ char f3(int a) { // LLVM-NEXT: store i32 %[[ARG_A]], ptr %[[A_ADDR]], align 4 // LLVM-NEXT: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4 // LLVM-NEXT: store i32 %[[A_VAL]], ptr @cs, align 4 -// LLVM-NEXT: %[[CS_B_VAL:.*]] = load i8, ptr getelementptr inbounds nuw (i8, ptr @cs, i64 4), align 1 +// LLVM-NEXT: %[[CS_B_VAL:.*]] = load i8, ptr getelementptr inbounds nuw (i8, ptr @cs, i64 4), align 4 // LLVM-NEXT: store i8 %[[CS_B_VAL]], ptr %[[RETVAL_ADDR]], align 1 // LLVM-NEXT: %[[RETVAL:.*]] = load i8, ptr %[[RETVAL_ADDR]], align 1 // LLVM-NEXT: ret i8 %[[RETVAL]] @@ -232,17 +232,17 @@ char f4(int a, struct CompleteS *p) { // CIR-NEXT: %[[A_ADDR:.*]] = cir.alloca {{.*}} ["a", init] {alignment = 4 : i64} // CIR-NEXT: %[[P_ADDR:.*]] = cir.alloca {{.*}} ["p", init] {alignment = 8 : i64} // CIR-NEXT: %[[RETVAL_ADDR:.*]] = cir.alloca {{.*}} ["__retval"] {alignment = 1 : i64} -// CIR-NEXT: cir.store %[[ARG_A]], %[[A_ADDR]] -// CIR-NEXT: cir.store %[[ARG_P]], %[[P_ADDR]] -// CIR-NEXT: %[[A_VAL:.*]] = cir.load %[[A_ADDR]] -// CIR-NEXT: %[[P:.*]] = cir.load %[[P_ADDR]] +// CIR-NEXT: cir.store{{.*}} %[[ARG_A]], %[[A_ADDR]] +// CIR-NEXT: cir.store{{.*}} %[[ARG_P]], %[[P_ADDR]] +// CIR-NEXT: %[[A_VAL:.*]] = cir.load{{.*}} %[[A_ADDR]] +// CIR-NEXT: %[[P:.*]] = cir.load{{.*}} %[[P_ADDR]] // CIR-NEXT: %[[P_A:.*]] = cir.get_member %[[P]][0] {name = "a"} -// CIR-NEXT: cir.store %[[A_VAL]], %[[P_A]] -// CIR-NEXT: %[[P2:.*]] = cir.load %[[P_ADDR]] +// CIR-NEXT: cir.store{{.*}} %[[A_VAL]], %[[P_A]] +// CIR-NEXT: %[[P2:.*]] = cir.load{{.*}} %[[P_ADDR]] // CIR-NEXT: %[[P_B:.*]] = cir.get_member %[[P2]][1] {name = "b"} -// CIR-NEXT: %[[P_B_VAL:.*]] = cir.load %[[P_B]] -// CIR-NEXT: cir.store %[[P_B_VAL]], %[[RETVAL_ADDR]] -// CIR-NEXT: %[[RETVAL:.*]] = cir.load %[[RETVAL_ADDR]] +// CIR-NEXT: %[[P_B_VAL:.*]] = cir.load{{.*}} %[[P_B]] +// CIR-NEXT: cir.store{{.*}} %[[P_B_VAL]], %[[RETVAL_ADDR]] +// CIR-NEXT: %[[RETVAL:.*]] = cir.load{{.*}} %[[RETVAL_ADDR]] // CIR-NEXT: cir.return %[[RETVAL]] // LLVM: define i8 @f4(i32 %[[ARG_A:.*]], ptr %[[ARG_P:.*]]) @@ -257,7 +257,7 @@ char f4(int a, struct CompleteS *p) { // LLVM-NEXT: store i32 %[[A_VAL]], ptr %[[P_A]], align 4 // LLVM-NEXT: %[[P_VAL2:.*]] = load ptr, ptr %[[P_ADDR]], align 8 // LLVM-NEXT: %[[P_B:.*]] = getelementptr %struct.CompleteS, ptr %[[P_VAL2]], i32 0, i32 1 -// LLVM-NEXT: %[[P_B_VAL:.*]] = load i8, ptr %[[P_B]], align 1 +// LLVM-NEXT: %[[P_B_VAL:.*]] = load i8, ptr %[[P_B]], align 4 // LLVM-NEXT: store i8 %[[P_B_VAL]], ptr %[[RETVAL_ADDR]], align 1 // LLVM-NEXT: %[[RETVAL:.*]] = load i8, ptr %[[RETVAL_ADDR]], align 1 // LLVM-NEXT: ret i8 %[[RETVAL]] diff --git a/clang/test/CIR/CodeGen/struct.cpp b/clang/test/CIR/CodeGen/struct.cpp index 208d8f184475c..5948d1423d448 100644 --- a/clang/test/CIR/CodeGen/struct.cpp +++ b/clang/test/CIR/CodeGen/struct.cpp @@ -47,9 +47,9 @@ char f2(CompleteS &s) { // CIR: cir.func @_Z2f2R9CompleteS(%[[ARG_S:.*]]: !cir.ptr{{.*}}) // CIR: %[[S_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["s", init, const] // CIR: cir.store %[[ARG_S]], %[[S_ADDR]] -// CIR: %[[S_REF:.*]] = cir.load %[[S_ADDR]] +// CIR: %[[S_REF:.*]] = cir.load{{.*}} %[[S_ADDR]] // CIR: %[[S_ADDR2:.*]] = cir.get_member %[[S_REF]][1] {name = "b"} -// CIR: %[[S_B:.*]] = cir.load %[[S_ADDR2]] +// CIR: %[[S_B:.*]] = cir.load{{.*}} %[[S_ADDR2]] // LLVM: define i8 @_Z2f2R9CompleteS(ptr %[[ARG_S:.*]]) // LLVM: %[[S_ADDR:.*]] = alloca ptr diff --git a/clang/test/CIR/CodeGen/switch.cpp b/clang/test/CIR/CodeGen/switch.cpp index a3dbac89fb856..8786c2350c192 100644 --- a/clang/test/CIR/CodeGen/switch.cpp +++ b/clang/test/CIR/CodeGen/switch.cpp @@ -104,7 +104,7 @@ void sw2(int a) { // CIR: cir.switch (%[[COND:.*]] : !s32i) { // CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) { // CIR-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i -// CIR-NEXT: cir.store %[[ZERO]], %[[FOMO]] : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ZERO]], %[[FOMO]] : !s32i, !cir.ptr // LLVM: define void @_Z3sw2i // LLVM: store i32 2, ptr %[[YOLO_ADDR:.*]], align 4 @@ -153,7 +153,7 @@ void sw3(int a) { // CIR: cir.func @_Z3sw3i // CIR: cir.scope { -// CIR-NEXT: %[[COND:.*]] = cir.load %[[A:.*]] : !cir.ptr, !s32i +// CIR-NEXT: %[[COND:.*]] = cir.load{{.*}} %[[A:.*]] : !cir.ptr, !s32i // CIR-NEXT: cir.switch (%[[COND]] : !s32i) { // CIR-NEXT: cir.case(default, []) { // CIR-NEXT: cir.break @@ -200,16 +200,16 @@ int sw4(int a) { // CIR-NEXT: cir.case(equal, [#cir.int<42> : !s32i]) { // CIR-NEXT: cir.scope { // CIR-NEXT: %[[THREE:.*]] = cir.const #cir.int<3> : !s32i -// CIR-NEXT: cir.store %[[THREE]], %[[RETVAL:.*]] : !s32i, !cir.ptr -// CIR-NEXT: %[[RET3:.*]] = cir.load %[[RETVAL]] : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %[[THREE]], %[[RETVAL:.*]] : !s32i, !cir.ptr +// CIR-NEXT: %[[RET3:.*]] = cir.load{{.*}} %[[RETVAL]] : !cir.ptr, !s32i // CIR-NEXT: cir.return %[[RET3]] : !s32i // CIR-NEXT: } // CIR-NEXT: cir.yield // CIR-NEXT: } // CIR-NEXT: cir.case(default, []) { // CIR-NEXT: %[[TWO:.*]] = cir.const #cir.int<2> : !s32i -// CIR-NEXT: cir.store %[[TWO]], %[[RETVAL]] : !s32i, !cir.ptr -// CIR-NEXT: %[[RET2:.*]] = cir.load %[[RETVAL]] : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %[[TWO]], %[[RETVAL]] : !s32i, !cir.ptr +// CIR-NEXT: %[[RET2:.*]] = cir.load{{.*}} %[[RETVAL]] : !cir.ptr, !s32i // CIR-NEXT: cir.return %[[RET2]] : !s32i // CIR-NEXT: } // CIR-NEXT: cir.yield @@ -985,7 +985,7 @@ void sw15(int x) { // CIR-NEXT: } // CIR-NEXT: cir.case(equal, [#cir.int<2> : !s32i]) { // CIR-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i -// CIR-NEXT: cir.store %[[ZERO]], %[[Y]] : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ZERO]], %[[Y]] : !s32i, !cir.ptr // CIR-NEXT: cir.yield // CIR-NEXT: } // CIR-NEXT: cir.case(equal, [#cir.int<3> : !s32i]) { diff --git a/clang/test/CIR/CodeGen/switch_flat_op.cpp b/clang/test/CIR/CodeGen/switch_flat_op.cpp index a9fc095025eb0..f917bd59f7ce3 100644 --- a/clang/test/CIR/CodeGen/switch_flat_op.cpp +++ b/clang/test/CIR/CodeGen/switch_flat_op.cpp @@ -23,17 +23,17 @@ void swf(int a) { // BEFORE: %[[CONST_3:.*]] = cir.const #cir.int<3> : !s32i // BEFORE: cir.switch (%[[COND:.*]] : !s32i) { // BEFORE: cir.case(equal, [#cir.int<3> : !s32i]) { -// BEFORE: %[[LOAD_B_EQ:.*]] = cir.load %[[VAR_B]] : !cir.ptr, !s32i +// BEFORE: %[[LOAD_B_EQ:.*]] = cir.load{{.*}} %[[VAR_B]] : !cir.ptr, !s32i // BEFORE: %[[CONST_2:.*]] = cir.const #cir.int<2> : !s32i // BEFORE: %[[MUL_EQ:.*]] = cir.binop(mul, %[[LOAD_B_EQ]], %[[CONST_2]]) nsw : !s32i -// BEFORE: cir.store %[[MUL_EQ]], %[[VAR_B]] : !s32i, !cir.ptr +// BEFORE: cir.store{{.*}} %[[MUL_EQ]], %[[VAR_B]] : !s32i, !cir.ptr // BEFORE: cir.break // BEFORE: } // BEFORE: cir.case(range, [#cir.int<4> : !s32i, #cir.int<5> : !s32i]) { -// BEFORE: %[[LOAD_B_RANGE:.*]] = cir.load %[[VAR_B]] : !cir.ptr, !s32i +// BEFORE: %[[LOAD_B_RANGE:.*]] = cir.load{{.*}} %[[VAR_B]] : !cir.ptr, !s32i // BEFORE: %[[CONST_3_RANGE:.*]] = cir.const #cir.int<3> : !s32i // BEFORE: %[[MUL_RANGE:.*]] = cir.binop(mul, %[[LOAD_B_RANGE]], %[[CONST_3_RANGE]]) nsw : !s32i -// BEFORE: cir.store %[[MUL_RANGE]], %[[VAR_B]] : !s32i, !cir.ptr +// BEFORE: cir.store{{.*}} %[[MUL_RANGE]], %[[VAR_B]] : !s32i, !cir.ptr // BEFORE: cir.break // BEFORE: } // BEFORE: cir.case(default, []) { @@ -46,26 +46,26 @@ void swf(int a) { // AFTER: cir.func @_Z3swfi // AFTER: %[[VAR_A:.*]] = cir.alloca !s32i, !cir.ptr, ["a", init] {alignment = 4 : i64} -// AFTER: cir.store %arg0, %[[VAR_A]] : !s32i, !cir.ptr +// AFTER: cir.store{{.*}} %arg0, %[[VAR_A]] : !s32i, !cir.ptr // AFTER: %[[VAR_B:.*]] = cir.alloca !s32i, !cir.ptr, ["b", init] {alignment = 4 : i64} // AFTER: %[[CONST_3:.*]] = cir.const #cir.int<3> : !s32i -// AFTER: cir.store %[[CONST_3]], %[[VAR_B]] : !s32i, !cir.ptr +// AFTER: cir.store{{.*}} %[[CONST_3]], %[[VAR_B]] : !s32i, !cir.ptr // AFTER: cir.switch.flat %[[COND:.*]] : !s32i, ^bb[[#BB6:]] [ // AFTER: 3: ^bb[[#BB4:]], // AFTER: 4: ^bb[[#BB5:]], // AFTER: 5: ^bb[[#BB5:]] // AFTER: ] // AFTER: ^bb[[#BB4]]: -// AFTER: %[[LOAD_B_EQ:.*]] = cir.load %[[VAR_B]] : !cir.ptr, !s32i +// AFTER: %[[LOAD_B_EQ:.*]] = cir.load{{.*}} %[[VAR_B]] : !cir.ptr, !s32i // AFTER: %[[CONST_2:.*]] = cir.const #cir.int<2> : !s32i // AFTER: %[[MUL_EQ:.*]] = cir.binop(mul, %[[LOAD_B_EQ]], %[[CONST_2]]) nsw : !s32i -// AFTER: cir.store %[[MUL_EQ]], %[[VAR_B]] : !s32i, !cir.ptr +// AFTER: cir.store{{.*}} %[[MUL_EQ]], %[[VAR_B]] : !s32i, !cir.ptr // AFTER: cir.br ^bb[[#BB7:]] // AFTER: ^bb[[#BB5]]: -// AFTER: %[[LOAD_B_RANGE:.*]] = cir.load %[[VAR_B]] : !cir.ptr, !s32i +// AFTER: %[[LOAD_B_RANGE:.*]] = cir.load{{.*}} %[[VAR_B]] : !cir.ptr, !s32i // AFTER: %[[CONST_3_AGAIN:.*]] = cir.const #cir.int<3> : !s32i // AFTER: %[[MUL_RANGE:.*]] = cir.binop(mul, %[[LOAD_B_RANGE]], %[[CONST_3_AGAIN]]) nsw : !s32i -// AFTER: cir.store %[[MUL_RANGE]], %[[VAR_B]] : !s32i, !cir.ptr +// AFTER: cir.store{{.*}} %[[MUL_RANGE]], %[[VAR_B]] : !s32i, !cir.ptr // AFTER: cir.br ^bb[[#BB7]] // AFTER: ^bb[[#BB6]]: // AFTER: cir.br ^bb[[#BB7]] diff --git a/clang/test/CIR/CodeGen/unary.cpp b/clang/test/CIR/CodeGen/unary.cpp index c041b142bf14f..0633cc3fd8e15 100644 --- a/clang/test/CIR/CodeGen/unary.cpp +++ b/clang/test/CIR/CodeGen/unary.cpp @@ -12,7 +12,7 @@ unsigned up0() { // CHECK: cir.func @_Z3up0v() -> !u32i // CHECK: %[[A:.*]] = cir.alloca !u32i, !cir.ptr, ["a", init] -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[OUTPUT:.*]] = cir.unary(plus, %[[INPUT]]) // LLVM: define i32 @_Z3up0v() @@ -33,7 +33,7 @@ unsigned um0() { // CHECK: cir.func @_Z3um0v() -> !u32i // CHECK: %[[A:.*]] = cir.alloca !u32i, !cir.ptr, ["a", init] -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[OUTPUT:.*]] = cir.unary(minus, %[[INPUT]]) // LLVM: define i32 @_Z3um0v() @@ -56,7 +56,7 @@ unsigned un0() { // CHECK: cir.func @_Z3un0v() -> !u32i // CHECK: %[[A:.*]] = cir.alloca !u32i, !cir.ptr, ["a", init] -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[OUTPUT:.*]] = cir.unary(not, %[[INPUT]]) // LLVM: define i32 @_Z3un0v() @@ -81,11 +81,11 @@ int inc0() { // CHECK: cir.func @_Z4inc0v() -> !s32i // CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr, ["a", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i -// CHECK: cir.store %[[ATMP]], %[[A]] : !s32i -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[INCREMENTED:.*]] = cir.unary(inc, %[[INPUT]]) nsw -// CHECK: cir.store %[[INCREMENTED]], %[[A]] -// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]] +// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]] // LLVM: define i32 @_Z4inc0v() // LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4 @@ -109,11 +109,11 @@ int dec0() { // CHECK: cir.func @_Z4dec0v() -> !s32i // CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr, ["a", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i -// CHECK: cir.store %[[ATMP]], %[[A]] : !s32i -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[DECREMENTED:.*]] = cir.unary(dec, %[[INPUT]]) nsw -// CHECK: cir.store %[[DECREMENTED]], %[[A]] -// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[DECREMENTED]], %[[A]] +// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]] // LLVM: define i32 @_Z4dec0v() // LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4 @@ -137,11 +137,11 @@ int inc1() { // CHECK: cir.func @_Z4inc1v() -> !s32i // CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr, ["a", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i -// CHECK: cir.store %[[ATMP]], %[[A]] : !s32i -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[INCREMENTED:.*]] = cir.unary(inc, %[[INPUT]]) nsw -// CHECK: cir.store %[[INCREMENTED]], %[[A]] -// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]] +// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]] // LLVM: define i32 @_Z4inc1v() // LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4 @@ -165,11 +165,11 @@ int dec1() { // CHECK: cir.func @_Z4dec1v() -> !s32i // CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr, ["a", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i -// CHECK: cir.store %[[ATMP]], %[[A]] : !s32i -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[DECREMENTED:.*]] = cir.unary(dec, %[[INPUT]]) nsw -// CHECK: cir.store %[[DECREMENTED]], %[[A]] -// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[DECREMENTED]], %[[A]] +// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]] // LLVM: define i32 @_Z4dec1v() // LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4 @@ -195,12 +195,12 @@ int inc2() { // CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr, ["a", init] // CHECK: %[[B:.*]] = cir.alloca !s32i, !cir.ptr, ["b", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i -// CHECK: cir.store %[[ATMP]], %[[A]] : !s32i -// CHECK: %[[ATOB:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i +// CHECK: %[[ATOB:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[INCREMENTED:.*]] = cir.unary(inc, %[[ATOB]]) nsw -// CHECK: cir.store %[[INCREMENTED]], %[[A]] -// CHECK: cir.store %[[ATOB]], %[[B]] -// CHECK: %[[B_TO_OUTPUT:.*]] = cir.load %[[B]] +// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]] +// CHECK: cir.store{{.*}} %[[ATOB]], %[[B]] +// CHECK: %[[B_TO_OUTPUT:.*]] = cir.load{{.*}} %[[B]] // LLVM: define i32 @_Z4inc2v() // LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4 @@ -230,7 +230,7 @@ float fpPlus() { // CHECK: cir.func @_Z6fpPlusv() -> !cir.float // CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr, ["a", init] -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[OUTPUT:.*]] = cir.unary(plus, %[[INPUT]]) // LLVM: define float @_Z6fpPlusv() @@ -251,7 +251,7 @@ float fpMinus() { // CHECK: cir.func @_Z7fpMinusv() -> !cir.float // CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr, ["a", init] -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[OUTPUT:.*]] = cir.unary(minus, %[[INPUT]]) // LLVM: define float @_Z7fpMinusv() @@ -275,8 +275,8 @@ float fpPreInc() { // CHECK: cir.func @_Z8fpPreIncv() -> !cir.float // CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr, ["a", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float -// CHECK: cir.store %[[ATMP]], %[[A]] : !cir.float -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[INCREMENTED:.*]] = cir.unary(inc, %[[INPUT]]) // LLVM: define float @_Z8fpPreIncv() @@ -300,8 +300,8 @@ float fpPreDec() { // CHECK: cir.func @_Z8fpPreDecv() -> !cir.float // CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr, ["a", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float -// CHECK: cir.store %[[ATMP]], %[[A]] : !cir.float -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[DECREMENTED:.*]] = cir.unary(dec, %[[INPUT]]) // LLVM: define float @_Z8fpPreDecv() @@ -325,8 +325,8 @@ float fpPostInc() { // CHECK: cir.func @_Z9fpPostIncv() -> !cir.float // CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr, ["a", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float -// CHECK: cir.store %[[ATMP]], %[[A]] : !cir.float -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[INCREMENTED:.*]] = cir.unary(inc, %[[INPUT]]) // LLVM: define float @_Z9fpPostIncv() @@ -350,8 +350,8 @@ float fpPostDec() { // CHECK: cir.func @_Z9fpPostDecv() -> !cir.float // CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr, ["a", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float -// CHECK: cir.store %[[ATMP]], %[[A]] : !cir.float -// CHECK: %[[INPUT:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[DECREMENTED:.*]] = cir.unary(dec, %[[INPUT]]) // LLVM: define float @_Z9fpPostDecv() @@ -378,12 +378,12 @@ float fpPostInc2() { // CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr, ["a", init] // CHECK: %[[B:.*]] = cir.alloca !cir.float, !cir.ptr, ["b", init] // CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float -// CHECK: cir.store %[[ATMP]], %[[A]] : !cir.float -// CHECK: %[[ATOB:.*]] = cir.load %[[A]] +// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float +// CHECK: %[[ATOB:.*]] = cir.load{{.*}} %[[A]] // CHECK: %[[INCREMENTED:.*]] = cir.unary(inc, %[[ATOB]]) -// CHECK: cir.store %[[INCREMENTED]], %[[A]] -// CHECK: cir.store %[[ATOB]], %[[B]] -// CHECK: %[[B_TO_OUTPUT:.*]] = cir.load %[[B]] +// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]] +// CHECK: cir.store{{.*}} %[[ATOB]], %[[B]] +// CHECK: %[[B_TO_OUTPUT:.*]] = cir.load{{.*}} %[[B]] // LLVM: define float @_Z10fpPostInc2v() // LLVM: %[[RV:.*]] = alloca float, i64 1, align 4 @@ -430,7 +430,7 @@ _Float16 fp16UPlus(_Float16 f) { } // CHECK: cir.func @_Z9fp16UPlusDF16_({{.*}}) -> !cir.f16 -// CHECK: %[[INPUT:.*]] = cir.load %[[F:.*]] +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]] // CHECK: %[[PROMOTED:.*]] = cir.cast(floating, %[[INPUT]] : !cir.f16), !cir.float // CHECK: %[[RESULT:.*]] = cir.unary(plus, %[[PROMOTED]]) // CHECK: %[[UNPROMOTED:.*]] = cir.cast(floating, %[[RESULT]] : !cir.float), !cir.f16 @@ -450,7 +450,7 @@ _Float16 fp16UMinus(_Float16 f) { } // CHECK: cir.func @_Z10fp16UMinusDF16_({{.*}}) -> !cir.f16 -// CHECK: %[[INPUT:.*]] = cir.load %[[F:.*]] +// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]] // CHECK: %[[PROMOTED:.*]] = cir.cast(floating, %[[INPUT]] : !cir.f16), !cir.float // CHECK: %[[RESULT:.*]] = cir.unary(minus, %[[PROMOTED]]) // CHECK: %[[UNPROMOTED:.*]] = cir.cast(floating, %[[RESULT]] : !cir.float), !cir.f16 @@ -481,27 +481,27 @@ void test_logical_not() { } // CHECK: cir.func @_Z16test_logical_notv() -// CHECK: %[[A:.*]] = cir.load %[[A_ADDR:.*]] : !cir.ptr, !s32i +// CHECK: %[[A:.*]] = cir.load{{.*}} %[[A_ADDR:.*]] : !cir.ptr, !s32i // CHECK: %[[A_BOOL:.*]] = cir.cast(int_to_bool, %[[A]] : !s32i), !cir.bool // CHECK: %[[A_NOT:.*]] = cir.unary(not, %[[A_BOOL]]) : !cir.bool, !cir.bool // CHECK: %[[A_CAST:.*]] = cir.cast(bool_to_int, %[[A_NOT]] : !cir.bool), !s32i -// CHECK: cir.store %[[A_CAST]], %[[A_ADDR]] : !s32i, !cir.ptr -// CHECK: %[[B:.*]] = cir.load %[[B_ADDR:.*]] : !cir.ptr, !cir.bool +// CHECK: cir.store{{.*}} %[[A_CAST]], %[[A_ADDR]] : !s32i, !cir.ptr +// CHECK: %[[B:.*]] = cir.load{{.*}} %[[B_ADDR:.*]] : !cir.ptr, !cir.bool // CHECK: %[[B_NOT:.*]] = cir.unary(not, %[[B]]) : !cir.bool, !cir.bool -// CHECK: cir.store %[[B_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr -// CHECK: %[[C:.*]] = cir.load %[[C_ADDR:.*]] : !cir.ptr, !cir.float +// CHECK: cir.store{{.*}} %[[B_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr +// CHECK: %[[C:.*]] = cir.load{{.*}} %[[C_ADDR:.*]] : !cir.ptr, !cir.float // CHECK: %[[C_BOOL:.*]] = cir.cast(float_to_bool, %[[C]] : !cir.float), !cir.bool // CHECK: %[[C_NOT:.*]] = cir.unary(not, %[[C_BOOL]]) : !cir.bool, !cir.bool // CHECK: %[[C_CAST:.*]] = cir.cast(bool_to_float, %[[C_NOT]] : !cir.bool), !cir.float -// CHECK: cir.store %[[C_CAST]], %[[C_ADDR]] : !cir.float, !cir.ptr -// CHECK: %[[P:.*]] = cir.load %[[P_ADDR:.*]] : !cir.ptr>, !cir.ptr +// CHECK: cir.store{{.*}} %[[C_CAST]], %[[C_ADDR]] : !cir.float, !cir.ptr +// CHECK: %[[P:.*]] = cir.load{{.*}} %[[P_ADDR:.*]] : !cir.ptr>, !cir.ptr // CHECK: %[[P_BOOL:.*]] = cir.cast(ptr_to_bool, %[[P]] : !cir.ptr), !cir.bool // CHECK: %[[P_NOT:.*]] = cir.unary(not, %[[P_BOOL]]) : !cir.bool, !cir.bool -// CHECK: cir.store %[[P_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr -// CHECK: %[[D:.*]] = cir.load %[[D_ADDR:.*]] : !cir.ptr, !cir.double +// CHECK: cir.store{{.*}} %[[P_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr +// CHECK: %[[D:.*]] = cir.load{{.*}} %[[D_ADDR:.*]] : !cir.ptr, !cir.double // CHECK: %[[D_BOOL:.*]] = cir.cast(float_to_bool, %[[D]] : !cir.double), !cir.bool // CHECK: %[[D_NOT:.*]] = cir.unary(not, %[[D_BOOL]]) : !cir.bool, !cir.bool -// CHECK: cir.store %[[D_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr +// CHECK: cir.store{{.*}} %[[D_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr // LLVM: define void @_Z16test_logical_notv() // LLVM: %[[A:.*]] = load i32, ptr %[[A_ADDR:.*]], align 4 diff --git a/clang/test/CIR/CodeGen/union.c b/clang/test/CIR/CodeGen/union.c index 790fbb7effdda..96c1e420e5ef0 100644 --- a/clang/test/CIR/CodeGen/union.c +++ b/clang/test/CIR/CodeGen/union.c @@ -78,11 +78,11 @@ int f2(void) { // CIR-NEXT: %[[U:.*]] = cir.alloca !rec_U1, !cir.ptr, ["u"] {alignment = 4 : i64} // CIR-NEXT: %[[I:.*]] = cir.const #cir.int<42> : !s32i // CIR-NEXT: %[[N:.*]] = cir.get_member %[[U]][0] {name = "n"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: cir.store %[[I]], %[[N]] : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[I]], %[[N]] : !s32i, !cir.ptr // CIR-NEXT: %[[N2:.*]] = cir.get_member %[[U]][0] {name = "n"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: %[[VAL:.*]] = cir.load %[[N2]] : !cir.ptr, !s32i -// CIR-NEXT: cir.store %[[VAL]], %[[RETVAL_ADDR]] : !s32i, !cir.ptr -// CIR-NEXT: %[[RET:.*]] = cir.load %[[RETVAL_ADDR]] : !cir.ptr, !s32i +// CIR-NEXT: %[[VAL:.*]] = cir.load{{.*}} %[[N2]] : !cir.ptr, !s32i +// CIR-NEXT: cir.store{{.*}} %[[VAL]], %[[RETVAL_ADDR]] : !s32i, !cir.ptr +// CIR-NEXT: %[[RET:.*]] = cir.load{{.*}} %[[RETVAL_ADDR]] : !cir.ptr, !s32i // CIR-NEXT: cir.return %[[RET]] : !s32i // LLVM: define i32 @f2() @@ -114,39 +114,39 @@ void shouldGenerateUnionAccess(union U2 u) { // CIR: cir.func @shouldGenerateUnionAccess(%[[ARG:.*]]: !rec_U2 // CIR-NEXT: %[[U:.*]] = cir.alloca !rec_U2, !cir.ptr, ["u", init] {alignment = 8 : i64} -// CIR-NEXT: cir.store %[[ARG]], %[[U]] : !rec_U2, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ARG]], %[[U]] : !rec_U2, !cir.ptr // CIR-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i // CIR-NEXT: %[[ZERO_CHAR:.*]] = cir.cast(integral, %[[ZERO]] : !s32i), !s8i // CIR-NEXT: %[[B_PTR:.*]] = cir.get_member %[[U]][0] {name = "b"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: cir.store %[[ZERO_CHAR]], %[[B_PTR]] : !s8i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ZERO_CHAR]], %[[B_PTR]] : !s8i, !cir.ptr // CIR-NEXT: %[[B_PTR2:.*]] = cir.get_member %[[U]][0] {name = "b"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: %[[B_VAL:.*]] = cir.load %[[B_PTR2]] : !cir.ptr, !s8i +// CIR-NEXT: %[[B_VAL:.*]] = cir.load{{.*}} %[[B_PTR2]] : !cir.ptr, !s8i // CIR-NEXT: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i // CIR-NEXT: %[[I_PTR:.*]] = cir.get_member %[[U]][2] {name = "i"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: cir.store %[[ONE]], %[[I_PTR]] : !s32i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ONE]], %[[I_PTR]] : !s32i, !cir.ptr // CIR-NEXT: %[[I_PTR2:.*]] = cir.get_member %[[U]][2] {name = "i"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: %[[I_VAL:.*]] = cir.load %[[I_PTR2]] : !cir.ptr, !s32i +// CIR-NEXT: %[[I_VAL:.*]] = cir.load{{.*}} %[[I_PTR2]] : !cir.ptr, !s32i // CIR-NEXT: %[[FLOAT_VAL:.*]] = cir.const #cir.fp<1.000000e-01> : !cir.float // CIR-NEXT: %[[F_PTR:.*]] = cir.get_member %[[U]][3] {name = "f"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: cir.store %[[FLOAT_VAL]], %[[F_PTR]] : !cir.float, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[FLOAT_VAL]], %[[F_PTR]] : !cir.float, !cir.ptr // CIR-NEXT: %[[F_PTR2:.*]] = cir.get_member %[[U]][3] {name = "f"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: %[[F_VAL:.*]] = cir.load %[[F_PTR2]] : !cir.ptr, !cir.float +// CIR-NEXT: %[[F_VAL:.*]] = cir.load{{.*}} %[[F_PTR2]] : !cir.ptr, !cir.float // CIR-NEXT: %[[DOUBLE_VAL:.*]] = cir.const #cir.fp<1.000000e-01> : !cir.double // CIR-NEXT: %[[D_PTR:.*]] = cir.get_member %[[U]][4] {name = "d"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: cir.store %[[DOUBLE_VAL]], %[[D_PTR]] : !cir.double, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[DOUBLE_VAL]], %[[D_PTR]] : !cir.double, !cir.ptr // CIR-NEXT: %[[D_PTR2:.*]] = cir.get_member %[[U]][4] {name = "d"} : !cir.ptr -> !cir.ptr -// CIR-NEXT: %[[D_VAL:.*]] = cir.load %[[D_PTR2]] : !cir.ptr, !cir.double +// CIR-NEXT: %[[D_VAL:.*]] = cir.load{{.*}} %[[D_PTR2]] : !cir.ptr, !cir.double // CIR-NEXT: cir.return // LLVM: define void @shouldGenerateUnionAccess(%union.U2 %[[ARG:.*]]) // LLVM-NEXT: %[[U:.*]] = alloca %union.U2, i64 1, align 8 // LLVM-NEXT: store %union.U2 %[[ARG]], ptr %[[U]], align 8 -// LLVM-NEXT: store i8 0, ptr %[[U]], align 1 -// LLVM-NEXT: %[[B_VAL:.*]] = load i8, ptr %[[U]], align 1 -// LLVM-NEXT: store i32 1, ptr %[[U]], align 4 -// LLVM-NEXT: %[[I_VAL:.*]] = load i32, ptr %[[U]], align 4 -// LLVM-NEXT: store float 0x3FB99999A0000000, ptr %[[U]], align 4 -// LLVM-NEXT: %[[F_VAL:.*]] = load float, ptr %[[U]], align 4 +// LLVM-NEXT: store i8 0, ptr %[[U]], align 8 +// LLVM-NEXT: %[[B_VAL:.*]] = load i8, ptr %[[U]], align 8 +// LLVM-NEXT: store i32 1, ptr %[[U]], align 8 +// LLVM-NEXT: %[[I_VAL:.*]] = load i32, ptr %[[U]], align 8 +// LLVM-NEXT: store float 0x3FB99999A0000000, ptr %[[U]], align 8 +// LLVM-NEXT: %[[F_VAL:.*]] = load float, ptr %[[U]], align 8 // LLVM-NEXT: store double 1.000000e-01, ptr %[[U]], align 8 // LLVM-NEXT: %[[D_VAL:.*]] = load double, ptr %[[U]], align 8 // LLVM-NEXT: ret void @@ -172,14 +172,14 @@ void f3(union U3 u) { // CIR: cir.func @f3(%[[ARG:.*]]: !rec_U3 // CIR-NEXT: %[[U:.*]] = cir.alloca !rec_U3, !cir.ptr, ["u", init] {alignment = 1 : i64} -// CIR-NEXT: cir.store %[[ARG]], %[[U]] : !rec_U3, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ARG]], %[[U]] : !rec_U3, !cir.ptr // CIR-NEXT: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i // CIR-NEXT: %[[ZERO_CHAR:.*]] = cir.cast(integral, %[[ZERO]] : !s32i), !s8i // CIR-NEXT: %[[IDX:.*]] = cir.const #cir.int<2> : !s32i // CIR-NEXT: %[[C_PTR:.*]] = cir.get_member %[[U]][0] {name = "c"} : !cir.ptr -> !cir.ptr> // CIR-NEXT: %[[C_DECAY:.*]] = cir.cast(array_to_ptrdecay, %[[C_PTR]] : !cir.ptr>), !cir.ptr // CIR-NEXT: %[[ELEM_PTR:.*]] = cir.ptr_stride(%[[C_DECAY]] : !cir.ptr, %[[IDX]] : !s32i), !cir.ptr -// CIR-NEXT: cir.store %[[ZERO_CHAR]], %[[ELEM_PTR]] : !s8i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ZERO_CHAR]], %[[ELEM_PTR]] : !s8i, !cir.ptr // CIR-NEXT: cir.return // LLVM: define void @f3(%union.U3 %[[ARG:.*]]) @@ -204,14 +204,14 @@ void f5(union U4 u) { // CIR: cir.func @f5(%[[ARG:.*]]: !rec_U4 // CIR-NEXT: %[[U:.*]] = cir.alloca !rec_U4, !cir.ptr, ["u", init] {alignment = 4 : i64} -// CIR-NEXT: cir.store %[[ARG]], %[[U]] : !rec_U4, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[ARG]], %[[U]] : !rec_U4, !cir.ptr // CIR-NEXT: %[[CHAR_VAL:.*]] = cir.const #cir.int<65> : !s32i // CIR-NEXT: %[[CHAR_CAST:.*]] = cir.cast(integral, %[[CHAR_VAL]] : !s32i), !s8i // CIR-NEXT: %[[IDX:.*]] = cir.const #cir.int<4> : !s32i // CIR-NEXT: %[[C_PTR:.*]] = cir.get_member %[[U]][0] {name = "c"} : !cir.ptr -> !cir.ptr> // CIR-NEXT: %[[C_DECAY:.*]] = cir.cast(array_to_ptrdecay, %[[C_PTR]] : !cir.ptr>), !cir.ptr // CIR-NEXT: %[[ELEM_PTR:.*]] = cir.ptr_stride(%[[C_DECAY]] : !cir.ptr, %[[IDX]] : !s32i), !cir.ptr -// CIR-NEXT: cir.store %[[CHAR_CAST]], %[[ELEM_PTR]] : !s8i, !cir.ptr +// CIR-NEXT: cir.store{{.*}} %[[CHAR_CAST]], %[[ELEM_PTR]] : !s8i, !cir.ptr // CIR-NEXT: cir.return // LLVM: define void @f5(%union.U4 %[[ARG:.*]]) @@ -219,7 +219,7 @@ void f5(union U4 u) { // LLVM-NEXT: store %union.U4 %[[ARG]], ptr %[[U]], align 4 // LLVM-NEXT: %[[C_PTR:.*]] = getelementptr i8, ptr %[[U]], i32 0 // LLVM-NEXT: %[[ELEM_PTR:.*]] = getelementptr i8, ptr %[[C_PTR]], i64 4 -// LLVM-NEXT: store i8 65, ptr %[[ELEM_PTR]], align 1 +// LLVM-NEXT: store i8 65, ptr %[[ELEM_PTR]], align 4 // LLVM-NEXT: ret void // OGCG: define dso_local void @f5(i64 %[[ARG:.*]]) diff --git a/clang/test/CIR/CodeGen/union.cpp b/clang/test/CIR/CodeGen/union.cpp index 24cd93f6b8edb..e931587c16d98 100644 --- a/clang/test/CIR/CodeGen/union.cpp +++ b/clang/test/CIR/CodeGen/union.cpp @@ -29,16 +29,16 @@ void shouldGenerateUnionAccess(union U u) { } // CIR: cir.func {{.*}}shouldGenerateUnionAccess // CIR: %[[#BASE:]] = cir.get_member %0[0] {name = "b"} : !cir.ptr -> !cir.ptr -// CIR: cir.store %{{.+}}, %[[#BASE]] : !cir.bool, !cir.ptr +// CIR: cir.store{{.*}} %{{.+}}, %[[#BASE]] : !cir.bool, !cir.ptr // CIR: cir.get_member %0[0] {name = "b"} : !cir.ptr -> !cir.ptr // CIR: %[[#BASE:]] = cir.get_member %0[2] {name = "i"} : !cir.ptr -> !cir.ptr -// CIR: cir.store %{{.+}}, %[[#BASE]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %{{.+}}, %[[#BASE]] : !s32i, !cir.ptr // CIR: %[[#BASE:]] = cir.get_member %0[2] {name = "i"} : !cir.ptr -> !cir.ptr // CIR: %[[#BASE:]] = cir.get_member %0[3] {name = "f"} : !cir.ptr -> !cir.ptr -// CIR: cir.store %{{.+}}, %[[#BASE]] : !cir.float, !cir.ptr +// CIR: cir.store{{.*}} %{{.+}}, %[[#BASE]] : !cir.float, !cir.ptr // CIR: %[[#BASE:]] = cir.get_member %0[3] {name = "f"} : !cir.ptr -> !cir.ptr // CIR: %[[#BASE:]] = cir.get_member %0[4] {name = "d"} : !cir.ptr -> !cir.ptr -// CIR: cir.store %{{.+}}, %[[#BASE]] : !cir.double, !cir.ptr +// CIR: cir.store{{.*}} %{{.+}}, %[[#BASE]] : !cir.double, !cir.ptr // CIR: %[[#BASE:]] = cir.get_member %0[4] {name = "d"} : !cir.ptr -> !cir.ptr // LLVM: define {{.*}}shouldGenerateUnionAccess diff --git a/clang/test/CIR/CodeGen/vector-ext.cpp b/clang/test/CIR/CodeGen/vector-ext.cpp index e0417e40fca3b..0c640b7f89ac8 100644 --- a/clang/test/CIR/CodeGen/vector-ext.cpp +++ b/clang/test/CIR/CodeGen/vector-ext.cpp @@ -79,26 +79,26 @@ void foo() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_E_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_E_VAL]], %[[VEC_E]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_E_VAL]], %[[VEC_E]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[GLOBAL_X:.*]] = cir.get_global @x : !cir.ptr -// CIR: %[[X_VAL:.*]] = cir.load %[[GLOBAL_X]] : !cir.ptr, !s32i +// CIR: %[[X_VAL:.*]] = cir.load{{.*}} %[[GLOBAL_X]] : !cir.ptr, !s32i // CIR: %[[CONST_5:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_6:.*]] = cir.const #cir.int<6> : !s32i // CIR: %[[GLOBAL_X:.*]] = cir.get_global @x : !cir.ptr -// CIR: %[[X:.*]] = cir.load %[[GLOBAL_X]] : !cir.ptr, !s32i +// CIR: %[[X:.*]] = cir.load{{.*}} %[[GLOBAL_X]] : !cir.ptr, !s32i // CIR: %[[CONST_1:.*]] = cir.const #cir.int<1> : !s32i // CIR: %[[X_PLUS_1:.*]] = cir.binop(add, %[[X]], %[[CONST_1]]) nsw : !s32i // CIR: %[[VEC_F_VAL:.*]] = cir.vec.create(%[[X_VAL]], %[[CONST_5]], %[[CONST_6]], %[[X_PLUS_1]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_F_VAL]], %[[VEC_F]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_F_VAL]], %[[VEC_F]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_5:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_0:.*]] = cir.const #cir.int<0> : !s32i // CIR: %[[VEC_G_VAL:.*]] = cir.vec.create(%[[CONST_5]], %[[CONST_0]], %[[CONST_0]], %[[CONST_0]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_G_VAL]], %[[VEC_G]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_G_VAL]], %[[VEC_G]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i // CIR: %[[VEC_H_VAL:.*]] = cir.vec.create(%[[ZERO]], %[[ZERO]], %[[ZERO]], %[[ZERO]] : !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_H_VAL]], %[[VEC_H]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_H_VAL]], %[[VEC_H]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[VEC_B:.*]] = alloca <3 x i32>, i64 1, align 16 @@ -129,7 +129,7 @@ void foo() { void foo2(vi4 p) {} // CIR: %[[VEC_A:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr>, ["p", init] -// CIR: cir.store %{{.*}}, %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %{{.*}}, %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: store <4 x i32> %{{.*}}, ptr %[[VEC_A]], align 16 @@ -150,11 +150,11 @@ void foo3() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[IDX:.*]] = cir.const #cir.int<1> : !s32i // CIR: %[[ELE:.*]] = cir.vec.extract %[[TMP]][%[[IDX]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[ELE]], %[[INIT]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ELE]], %[[INIT]] : !s32i, !cir.ptr // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[INIT:.*]] = alloca i32, i64 1, align 4 @@ -186,13 +186,13 @@ void foo4() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_IDX:.*]] = cir.const #cir.int<2> : !s32i -// CIR: cir.store %[[CONST_IDX]], %[[IDX]] : !s32i, !cir.ptr -// CIR: %[[TMP1:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP2:.*]] = cir.load %[[IDX]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[CONST_IDX]], %[[IDX]] : !s32i, !cir.ptr +// CIR: %[[TMP1:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP2:.*]] = cir.load{{.*}} %[[IDX]] : !cir.ptr, !s32i // CIR: %[[ELE:.*]] = cir.vec.extract %[[TMP1]][%[[TMP2]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[ELE]], %[[INIT]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ELE]], %[[INIT]] : !s32i, !cir.ptr // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[IDX:.*]] = alloca i32, i64 1, align 4 @@ -227,12 +227,12 @@ void foo5() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_VAL:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_IDX:.*]] = cir.const #cir.int<2> : !s32i -// CIR: %[[TMP:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[NEW_VEC:.*]] = cir.vec.insert %[[CONST_VAL]], %[[TMP]][%[[CONST_IDX]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: store <4 x i32> , ptr %[[VEC]], align 16 @@ -262,16 +262,16 @@ void foo6() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_IDX:.*]] = cir.const #cir.int<2> : !s32i -// CIR: cir.store %[[CONST_IDX]], %[[IDX]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[CONST_IDX]], %[[IDX]] : !s32i, !cir.ptr // CIR: %[[CONST_VAL:.*]] = cir.const #cir.int<5> : !s32i -// CIR: cir.store %[[CONST_VAL]], %[[VAL]] : !s32i, !cir.ptr -// CIR: %[[TMP1:.*]] = cir.load %[[VAL]] : !cir.ptr, !s32i -// CIR: %[[TMP2:.*]] = cir.load %[[IDX]] : !cir.ptr, !s32i -// CIR: %[[TMP3:.*]] = cir.load %0 : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[CONST_VAL]], %[[VAL]] : !s32i, !cir.ptr +// CIR: %[[TMP1:.*]] = cir.load{{.*}} %[[VAL]] : !cir.ptr, !s32i +// CIR: %[[TMP2:.*]] = cir.load{{.*}} %[[IDX]] : !cir.ptr, !s32i +// CIR: %[[TMP3:.*]] = cir.load{{.*}} %0 : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[NEW_VEC:.*]] = cir.vec.insert %[[TMP1]], %[[TMP3]][%[[TMP2]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[IDX:.*]] = alloca i32, i64 1, align 4 @@ -309,15 +309,15 @@ void foo7() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_VAL:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_IDX:.*]] = cir.const #cir.int<2> : !s32i -// CIR: %[[TMP:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[ELE:.*]] = cir.vec.extract %[[TMP]][%[[CONST_IDX]] : !s32i] : !cir.vector<4 x !s32i> // CIR: %[[RES:.*]] = cir.binop(add, %[[ELE]], %[[CONST_VAL]]) nsw : !s32i -// CIR: %[[TMP2:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP2:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[NEW_VEC:.*]] = cir.vec.insert %[[RES]], %[[TMP2]][%[[CONST_IDX]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: store <4 x i32> , ptr %[[VEC]], align 16 @@ -355,16 +355,16 @@ void foo8() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP1:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP1:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[PLUS:.*]] = cir.unary(plus, %[[TMP1]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i> -// CIR: cir.store %[[PLUS]], %[[PLUS_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP2:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[PLUS]], %[[PLUS_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP2:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[MINUS:.*]] = cir.unary(minus, %[[TMP2]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i> -// CIR: cir.store %[[MINUS]], %[[MINUS_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP3:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[MINUS]], %[[MINUS_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP3:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[NOT:.*]] = cir.unary(not, %[[TMP3]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i> -// CIR: cir.store %[[NOT]], %[[NOT_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[NOT]], %[[NOT_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[PLUS_RES:.*]] = alloca <4 x i32>, i64 1, align 16 @@ -412,22 +412,22 @@ void foo9() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_A_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_5:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_6:.*]] = cir.const #cir.int<6> : !s32i // CIR: %[[CONST_7:.*]] = cir.const #cir.int<7> : !s32i // CIR: %[[CONST_8:.*]] = cir.const #cir.int<8> : !s32i // CIR: %[[VEC_B_VAL:.*]] = cir.vec.create(%[[CONST_5]], %[[CONST_6]], %[[CONST_7]], %[[CONST_8]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[SHL:.*]] = cir.shift(left, %[[TMP_A]] : !cir.vector<4 x !s32i>, %[[TMP_B]] : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> -// CIR: cir.store %[[SHL]], %[[SHL_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[SHL]], %[[SHL_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[SHR:.*]] = cir.shift(right, %[[TMP_A]] : !cir.vector<4 x !s32i>, %[[TMP_B]] : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> -// CIR: cir.store %[[SHR]], %[[SHR_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[SHR]], %[[SHR_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[VEC_B:.*]] = alloca <4 x i32>, i64 1, align 16 @@ -477,42 +477,42 @@ void foo11() { // CIR: %[[VEC_B:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr>, ["b", init] // CIR: %[[VEC_A_VAL:.*]] = cir.vec.create({{.*}}, {{.*}}, {{.*}}, {{.*}} : !s32i, !s32i, !s32i, !s32i) : // CIR-SAME: !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[VEC_B_VAL:.*]] = cir.vec.create({{.*}}, {{.*}}, {{.*}}, {{.*}} : !s32i, !s32i, !s32i, !s32i) : // CIR-SAME: !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[ADD:.*]] = cir.binop(add, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[ADD]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[ADD]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[SUB:.*]] = cir.binop(sub, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[SUB]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[SUB]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[MUL:.*]] = cir.binop(mul, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[MUL]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[MUL]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[DIV:.*]] = cir.binop(div, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[DIV]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[DIV]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[REM:.*]] = cir.binop(rem, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[REM]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[REM]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[AND:.*]] = cir.binop(and, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[AND]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[AND]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[OR:.*]] = cir.binop(or, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[OR]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[OR]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[XOR:.*]] = cir.binop(xor, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[XOR]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[XOR]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[VEC_B:.*]] = alloca <4 x i32>, i64 1, align 16 diff --git a/clang/test/CIR/CodeGen/vector.cpp b/clang/test/CIR/CodeGen/vector.cpp index 2ad5b247cd1b0..236a2f3369ae5 100644 --- a/clang/test/CIR/CodeGen/vector.cpp +++ b/clang/test/CIR/CodeGen/vector.cpp @@ -68,27 +68,27 @@ void foo() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_D_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_D_VAL]], %[[VEC_D]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_D_VAL]], %[[VEC_D]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[GLOBAL_X:.*]] = cir.get_global @x : !cir.ptr -// CIR: %[[X_VAL:.*]] = cir.load %[[GLOBAL_X]] : !cir.ptr, !s32i +// CIR: %[[X_VAL:.*]] = cir.load{{.*}} %[[GLOBAL_X]] : !cir.ptr, !s32i // CIR: %[[CONST_5:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_6:.*]] = cir.const #cir.int<6> : !s32i // CIR: %[[GLOBAL_X:.*]] = cir.get_global @x : !cir.ptr -// CIR: %[[X:.*]] = cir.load %[[GLOBAL_X]] : !cir.ptr, !s32i +// CIR: %[[X:.*]] = cir.load{{.*}} %[[GLOBAL_X]] : !cir.ptr, !s32i // CIR: %[[CONST_1:.*]] = cir.const #cir.int<1> : !s32i // CIR: %[[X_PLUS_1:.*]] = cir.binop(add, %[[X]], %[[CONST_1]]) nsw : !s32i // CIR: %[[VEC_E_VAL:.*]] = cir.vec.create(%[[X_VAL]], %[[CONST_5]], %[[CONST_6]], %[[X_PLUS_1]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_E_VAL]], %[[VEC_E]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_E_VAL]], %[[VEC_E]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_5:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_0:.*]] = cir.const #cir.int<0> : !s32i // CIR: %[[VEC_F_VAL:.*]] = cir.vec.create(%[[CONST_5]], %[[CONST_0]], %[[CONST_0]], %[[CONST_0]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_F_VAL]], %[[VEC_F]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_F_VAL]], %[[VEC_F]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_0:.*]] = cir.const #cir.int<0> : !s32i // CIR: %[[VEC_G_VAL:.*]] = cir.vec.create(%[[CONST_0]], %[[CONST_0]], %[[CONST_0]], %[[CONST_0]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_G_VAL]], %[[VEC_G]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_G_VAL]], %[[VEC_G]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[VEC_B:.*]] = alloca <2 x double>, i64 1, align 16 @@ -117,7 +117,7 @@ void foo() { void foo2(vi4 p) {} // CIR: %[[VEC_A:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr>, ["p", init] -// CIR: cir.store %{{.*}}, %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %{{.*}}, %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: store <4 x i32> %{{.*}}, ptr %[[VEC_A]], align 16 @@ -138,11 +138,11 @@ void foo3() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[IDX:.*]] = cir.const #cir.int<1> : !s32i // CIR: %[[ELE:.*]] = cir.vec.extract %[[TMP]][%[[IDX]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[ELE]], %[[INIT]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ELE]], %[[INIT]] : !s32i, !cir.ptr // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[INIT:.*]] = alloca i32, i64 1, align 4 @@ -174,13 +174,13 @@ void foo4() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_IDX:.*]] = cir.const #cir.int<2> : !s32i -// CIR: cir.store %[[CONST_IDX]], %[[IDX]] : !s32i, !cir.ptr -// CIR: %[[TMP1:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP2:.*]] = cir.load %[[IDX]] : !cir.ptr, !s32i +// CIR: cir.store{{.*}} %[[CONST_IDX]], %[[IDX]] : !s32i, !cir.ptr +// CIR: %[[TMP1:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP2:.*]] = cir.load{{.*}} %[[IDX]] : !cir.ptr, !s32i // CIR: %[[ELE:.*]] = cir.vec.extract %[[TMP1]][%[[TMP2]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[ELE]], %[[INIT]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[ELE]], %[[INIT]] : !s32i, !cir.ptr // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[IDX:.*]] = alloca i32, i64 1, align 4 @@ -215,12 +215,12 @@ void foo5() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_VAL:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_IDX:.*]] = cir.const #cir.int<2> : !s32i -// CIR: %[[TMP:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[NEW_VEC:.*]] = cir.vec.insert %[[CONST_VAL]], %[[TMP]][%[[CONST_IDX]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: store <4 x i32> , ptr %[[VEC]], align 16 @@ -250,16 +250,16 @@ void foo6() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_IDX:.*]] = cir.const #cir.int<2> : !s32i -// CIR: cir.store %[[CONST_IDX]], %[[IDX]] : !s32i, !cir.ptr +// CIR: cir.store{{.*}} %[[CONST_IDX]], %[[IDX]] : !s32i, !cir.ptr // CIR: %[[CONST_VAL:.*]] = cir.const #cir.int<5> : !s32i -// CIR: cir.store %[[CONST_VAL]], %[[VAL]] : !s32i, !cir.ptr -// CIR: %[[TMP1:.*]] = cir.load %[[VAL]] : !cir.ptr, !s32i -// CIR: %[[TMP2:.*]] = cir.load %[[IDX]] : !cir.ptr, !s32i -// CIR: %[[TMP3:.*]] = cir.load %0 : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[CONST_VAL]], %[[VAL]] : !s32i, !cir.ptr +// CIR: %[[TMP1:.*]] = cir.load{{.*}} %[[VAL]] : !cir.ptr, !s32i +// CIR: %[[TMP2:.*]] = cir.load{{.*}} %[[IDX]] : !cir.ptr, !s32i +// CIR: %[[TMP3:.*]] = cir.load{{.*}} %0 : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[NEW_VEC:.*]] = cir.vec.insert %[[TMP1]], %[[TMP3]][%[[TMP2]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[IDX:.*]] = alloca i32, i64 1, align 4 @@ -297,15 +297,15 @@ void foo7() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_VAL:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_IDX:.*]] = cir.const #cir.int<2> : !s32i -// CIR: %[[TMP:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[ELE:.*]] = cir.vec.extract %[[TMP]][%[[CONST_IDX]] : !s32i] : !cir.vector<4 x !s32i> // CIR: %[[RES:.*]] = cir.binop(add, %[[ELE]], %[[CONST_VAL]]) nsw : !s32i -// CIR: %[[TMP2:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP2:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[NEW_VEC:.*]] = cir.vec.insert %[[RES]], %[[TMP2]][%[[CONST_IDX]] : !s32i] : !cir.vector<4 x !s32i> -// CIR: cir.store %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[NEW_VEC]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: store <4 x i32> , ptr %[[VEC]], align 16 @@ -343,16 +343,16 @@ void foo8() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP1:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[VEC_VAL]], %[[VEC]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP1:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[PLUS:.*]] = cir.unary(plus, %[[TMP1]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i> -// CIR: cir.store %[[PLUS]], %[[PLUS_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP2:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[PLUS]], %[[PLUS_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP2:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[MINUS:.*]] = cir.unary(minus, %[[TMP2]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i> -// CIR: cir.store %[[MINUS]], %[[MINUS_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP3:.*]] = cir.load %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[MINUS]], %[[MINUS_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP3:.*]] = cir.load{{.*}} %[[VEC]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[NOT:.*]] = cir.unary(not, %[[TMP3]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i> -// CIR: cir.store %[[NOT]], %[[NOT_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[NOT]], %[[NOT_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[PLUS_RES:.*]] = alloca <4 x i32>, i64 1, align 16 @@ -400,22 +400,22 @@ void foo9() { // CIR: %[[CONST_4:.*]] = cir.const #cir.int<4> : !s32i // CIR: %[[VEC_A_VAL:.*]] = cir.vec.create(%[[CONST_1]], %[[CONST_2]], %[[CONST_3]], %[[CONST_4]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[CONST_5:.*]] = cir.const #cir.int<5> : !s32i // CIR: %[[CONST_6:.*]] = cir.const #cir.int<6> : !s32i // CIR: %[[CONST_7:.*]] = cir.const #cir.int<7> : !s32i // CIR: %[[CONST_8:.*]] = cir.const #cir.int<8> : !s32i // CIR: %[[VEC_B_VAL:.*]] = cir.vec.create(%[[CONST_5]], %[[CONST_6]], %[[CONST_7]], %[[CONST_8]] : // CIR-SAME: !s32i, !s32i, !s32i, !s32i) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[SHL:.*]] = cir.shift(left, %[[TMP_A]] : !cir.vector<4 x !s32i>, %[[TMP_B]] : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> -// CIR: cir.store %[[SHL]], %[[SHL_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[SHL]], %[[SHL_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[SHR:.*]] = cir.shift(right, %[[TMP_A]] : !cir.vector<4 x !s32i>, %[[TMP_B]] : !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> -// CIR: cir.store %[[SHR]], %[[SHR_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[SHR]], %[[SHR_RES]] : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[VEC_B:.*]] = alloca <4 x i32>, i64 1, align 16 @@ -465,42 +465,42 @@ void foo11() { // CIR: %[[VEC_B:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr>, ["b", init] // CIR: %[[VEC_A_VAL:.*]] = cir.vec.create({{.*}}, {{.*}}, {{.*}}, {{.*}} : !s32i, !s32i, !s32i, !s32i) : // CIR-SAME: !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[VEC_A_VAL]], %[[VEC_A]] : !cir.vector<4 x !s32i>, !cir.ptr> // CIR: %[[VEC_B_VAL:.*]] = cir.vec.create({{.*}}, {{.*}}, {{.*}}, {{.*}} : !s32i, !s32i, !s32i, !s32i) : // CIR-SAME: !cir.vector<4 x !s32i> -// CIR: cir.store %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[VEC_B_VAL]], %[[VEC_B]] : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[ADD:.*]] = cir.binop(add, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[ADD]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[ADD]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[SUB:.*]] = cir.binop(sub, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[SUB]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[SUB]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[MUL:.*]] = cir.binop(mul, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[MUL]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[MUL]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[DIV:.*]] = cir.binop(div, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[DIV]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[DIV]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[REM:.*]] = cir.binop(rem, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[REM]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[REM]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[AND:.*]] = cir.binop(and, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[AND]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[AND]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[OR:.*]] = cir.binop(or, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[OR]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> -// CIR: %[[TMP_A:.*]] = cir.load %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> -// CIR: %[[TMP_B:.*]] = cir.load %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: cir.store{{.*}} %[[OR]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[VEC_A]] : !cir.ptr>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[VEC_B]] : !cir.ptr>, !cir.vector<4 x !s32i> // CIR: %[[XOR:.*]] = cir.binop(xor, %[[TMP_A]], %[[TMP_B]]) : !cir.vector<4 x !s32i> -// CIR: cir.store %[[XOR]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> +// CIR: cir.store{{.*}} %[[XOR]], {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr> // LLVM: %[[VEC_A:.*]] = alloca <4 x i32>, i64 1, align 16 // LLVM: %[[VEC_B:.*]] = alloca <4 x i32>, i64 1, align 16 diff --git a/clang/test/CIR/CodeGenOpenACC/combined.cpp b/clang/test/CIR/CodeGenOpenACC/combined.cpp index d55ce762ce6f1..6124f38967285 100644 --- a/clang/test/CIR/CodeGenOpenACC/combined.cpp +++ b/clang/test/CIR/CodeGenOpenACC/combined.cpp @@ -190,7 +190,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc serial loop self(N) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[N_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.serial combined(loop) self(%[[CONV_CAST]]) { @@ -202,7 +202,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc parallel loop if(N) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[N_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.parallel combined(loop) if(%[[CONV_CAST]]) { @@ -226,7 +226,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop if(N == 1) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[EQ_RES:.*]] = cir.cmp(eq, %[[N_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES]] : !cir.bool to i1 @@ -239,11 +239,11 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc parallel loop if(N == 1) self(N == 2) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[EQ_RES_IF:.*]] = cir.cmp(eq, %[[N_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST_IF:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES_IF]] : !cir.bool to i1 - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[EQ_RES_SELF:.*]] = cir.cmp(eq, %[[N_LOAD]], %[[TWO_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST_SELF:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES_SELF]] : !cir.bool to i1 @@ -350,7 +350,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc parallel loop gang(static:N, dim: 1) device_type(nvidia, radeon) gang(static:*, dim : 2) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.parallel combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_CONST:.*]] = arith.constant 1 : i64 // CHECK-NEXT: %[[STAR_CONST:.*]] = arith.constant -1 : i64 @@ -364,9 +364,9 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop gang(num:N) device_type(nvidia, radeon) gang(num:N) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV2:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD2]] : !s32i to si32 // CHECK-NEXT: acc.loop combined(kernels) gang({num=%[[N_CONV]] : si32}, {num=%[[N_CONV2]] : si32} [#acc.device_type], {num=%[[N_CONV2]] : si32} [#acc.device_type]) { // CHECK: acc.yield @@ -376,7 +376,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop gang(static:N) device_type(nvidia) gang(static:*) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[STAR_CONST:.*]] = arith.constant -1 : i64 // CHECK-NEXT: acc.loop combined(kernels) gang({static=%[[N_CONV]] : si32}, {static=%[[STAR_CONST]] : i64} [#acc.device_type]) { @@ -387,14 +387,14 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop gang(static:N, num: N + 1) device_type(nvidia) gang(static:*, num : N + 2) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CIR_ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD2]], %[[CIR_ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 // CHECK-NEXT: %[[STAR_CONST:.*]] = arith.constant -1 : i64 - // CHECK-NEXT: %[[N_LOAD3:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD3:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CIR_TWO_CONST:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[N_PLUS_TWO:.*]] = cir.binop(add, %[[N_LOAD3]], %[[CIR_TWO_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_TWO_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_TWO]] : !s32i to si32 @@ -416,7 +416,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop worker(N) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop combined(kernels) worker(%[[N_CONV]] : si32) { // CHECK: acc.yield @@ -436,7 +436,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop worker(N) device_type(nvidia, radeon) worker for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop combined(kernels) worker([#acc.device_type, #acc.device_type], %[[N_CONV]] : si32) { // CHECK: acc.yield @@ -447,7 +447,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop worker device_type(nvidia, radeon) worker(N) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop combined(kernels) worker([#acc.device_type], %[[N_CONV]] : si32 [#acc.device_type], %[[N_CONV]] : si32 [#acc.device_type]) { // CHECK: acc.yield @@ -458,9 +458,9 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop worker(N) device_type(nvidia, radeon) worker(N + 1) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD2]], %[[ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 @@ -473,7 +473,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop device_type(nvidia, radeon) worker(num:N + 1) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD]], %[[ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 @@ -503,7 +503,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop vector(N) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop combined(kernels) vector(%[[N_CONV]] : si32) { // CHECK: acc.yield @@ -523,7 +523,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop vector(N) device_type(nvidia, radeon) vector for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop combined(kernels) vector([#acc.device_type, #acc.device_type], %[[N_CONV]] : si32) { // CHECK: acc.yield @@ -534,9 +534,9 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop vector(N) device_type(nvidia, radeon) vector(N + 1) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD2]], %[[ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 @@ -549,7 +549,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop device_type(nvidia, radeon) vector(length:N + 1) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD]], %[[ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 @@ -562,13 +562,13 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop worker(N) vector(N) device_type(nvidia) worker(N) vector(N) for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: acc.kernels combined(loop) { - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV2:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD2]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD3:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD3:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV3:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD3]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD4:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD4:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV4:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD4]] : !s32i to si32 // CHECK-NEXT: acc.loop combined(kernels) worker(%[[N_CONV]] : si32, %[[N_CONV3]] : si32 [#acc.device_type]) vector(%[[N_CONV2]] : si32, %[[N_CONV4]] : si32 [#acc.device_type]) { // CHECK: acc.yield @@ -631,7 +631,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop wait(devnum: cond : 1) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -644,11 +644,11 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc parallel loop wait(devnum: cond : 1) device_type(nvidia) wait(devnum: cond : 1) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -661,7 +661,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc serial loop wait(devnum: cond : 1, 2) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -676,13 +676,13 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop wait(devnum: cond : 1, 2) device_type(nvidia, radeon) wait(devnum: cond : 1, 2) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -697,7 +697,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc parallel loop wait(cond, 1) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -710,7 +710,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc serial loop wait(queues: cond, 1) device_type(radeon) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -734,7 +734,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop num_gangs(cond) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.kernels combined(loop) num_gangs({%[[CONV_CAST]] : si32}) { // CHECK-NEXT: acc.loop combined(kernels) { @@ -747,7 +747,7 @@ extern "C" void acc_combined(int N, int cond) { for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -762,7 +762,7 @@ extern "C" void acc_combined(int N, int cond) { for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.kernels combined(loop) num_gangs({%[[ONE_CAST]] : si32}, {%[[CONV_CAST]] : si32} [#acc.device_type]) { // CHECK-NEXT: acc.loop combined(kernels) { @@ -775,7 +775,7 @@ extern "C" void acc_combined(int N, int cond) { for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -796,7 +796,7 @@ extern "C" void acc_combined(int N, int cond) { for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -815,7 +815,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc parallel loop num_workers(cond) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel combined(loop) num_workers(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.loop combined(parallel) { @@ -826,7 +826,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop num_workers(cond) device_type(nvidia) num_workers(2u) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !u32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !u32i to ui32 @@ -839,7 +839,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc parallel loop num_workers(cond) device_type(nvidia, host) num_workers(2) device_type(radeon) num_workers(3) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -854,7 +854,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop num_workers(cond) device_type(nvidia) num_workers(2) device_type(radeon, multicore) num_workers(4) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -882,7 +882,7 @@ extern "C" void acc_combined(int N, int cond) { // #pragma acc parallel loop vector_length(cond) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel combined(loop) vector_length(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.loop combined(parallel) { @@ -893,7 +893,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop vector_length(cond) device_type(nvidia) vector_length(2u) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !u32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !u32i to ui32 @@ -906,7 +906,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc parallel loop vector_length(cond) device_type(nvidia, host) vector_length(2) device_type(radeon) vector_length(3) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -921,7 +921,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc kernels loop vector_length(cond) device_type(nvidia) vector_length(2) device_type(radeon, multicore) vector_length(4) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -958,7 +958,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc serial loop async(cond) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.serial combined(loop) async(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.loop combined(serial) { @@ -980,7 +980,7 @@ extern "C" void acc_combined(int N, int cond) { for(unsigned I = 0; I < N; ++I); // CHECK-NEXT: %[[THREE_LITERAL:.*]] = cir.const #cir.int<3> : !s32i // CHECK-NEXT: %[[THREE_CAST:.*]] = builtin.unrealized_conversion_cast %[[THREE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel combined(loop) async(%[[THREE_CAST]] : si32, %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.loop combined(parallel) { @@ -991,7 +991,7 @@ extern "C" void acc_combined(int N, int cond) { #pragma acc serial loop async device_type(nvidia, radeon) async(cond) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.serial combined(loop) async([#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.loop combined(serial) { diff --git a/clang/test/CIR/CodeGenOpenACC/data.c b/clang/test/CIR/CodeGenOpenACC/data.c index 5c8d32dfd2b73..948119f66e93d 100644 --- a/clang/test/CIR/CodeGenOpenACC/data.c +++ b/clang/test/CIR/CodeGenOpenACC/data.c @@ -43,7 +43,7 @@ void acc_data(int cond) { #pragma acc data default(none) async(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.data async(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.terminator @@ -59,7 +59,7 @@ void acc_data(int cond) { {} // CHECK-NEXT: %[[THREE_LITERAL:.*]] = cir.const #cir.int<3> : !s32i // CHECK-NEXT: %[[THREE_CAST:.*]] = builtin.unrealized_conversion_cast %[[THREE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.data async(%[[THREE_CAST]] : si32, %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.terminator @@ -67,7 +67,7 @@ void acc_data(int cond) { #pragma acc data default(none) async device_type(nvidia, radeon) async(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.data async([#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.terminator @@ -83,7 +83,7 @@ void acc_data(int cond) { #pragma acc data default(none) if(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.data if(%[[CONV_CAST]]) { @@ -101,7 +101,7 @@ void acc_data(int cond) { #pragma acc data default(none) if(cond == 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[EQ_RES:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES]] : !cir.bool to i1 @@ -149,7 +149,7 @@ void acc_data(int cond) { #pragma acc data default(none) wait(devnum: cond : 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -159,11 +159,11 @@ void acc_data(int cond) { #pragma acc data default(none) wait(devnum: cond : 1) device_type(nvidia) wait(devnum: cond : 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -173,7 +173,7 @@ void acc_data(int cond) { #pragma acc data default(none) wait(devnum: cond : 1, 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -185,13 +185,13 @@ void acc_data(int cond) { #pragma acc data default(none) wait(devnum: cond : 1, 2) device_type(nvidia, radeon) wait(devnum: cond : 1, 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -203,7 +203,7 @@ void acc_data(int cond) { #pragma acc data default(none) wait(cond, 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -213,7 +213,7 @@ void acc_data(int cond) { #pragma acc data default(none) wait(queues: cond, 1) device_type(radeon) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 diff --git a/clang/test/CIR/CodeGenOpenACC/init.c b/clang/test/CIR/CodeGenOpenACC/init.c index d0385f857240d..54f686dbe8ebc 100644 --- a/clang/test/CIR/CodeGenOpenACC/init.c +++ b/clang/test/CIR/CodeGenOpenACC/init.c @@ -21,7 +21,7 @@ void acc_init(int cond) { // CHECK-NEXT: acc.init attributes {device_types = [#acc.device_type, #acc.device_type]} #pragma acc init if(cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[BOOL_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.init if(%[[BOOL_CONV]]) @@ -33,7 +33,7 @@ void acc_init(int cond) { // CHECK-NEXT: acc.init if(%[[BOOL_CONV]]) #pragma acc init device_num(cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.init device_num(%[[COND_CONV]] : si32) @@ -43,10 +43,10 @@ void acc_init(int cond) { // CHECK-NEXT: acc.init device_num(%[[ONE_CONV]] : si32) #pragma acc init if(cond) device_num(cond) device_type(*) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[BOOL_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_CAST]] : !cir.bool to i1 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.init device_num(%[[COND_CONV]] : si32) if(%[[BOOL_CONV]]) attributes {device_types = [#acc.device_type]} } diff --git a/clang/test/CIR/CodeGenOpenACC/kernels.c b/clang/test/CIR/CodeGenOpenACC/kernels.c index 500bec875cf6b..333669c8de7de 100644 --- a/clang/test/CIR/CodeGenOpenACC/kernels.c +++ b/clang/test/CIR/CodeGenOpenACC/kernels.c @@ -48,7 +48,7 @@ void acc_kernels(int cond) { #pragma acc kernels self(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.kernels self(%[[CONV_CAST]]) { @@ -66,7 +66,7 @@ void acc_kernels(int cond) { #pragma acc kernels if(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.kernels if(%[[CONV_CAST]]) { @@ -84,7 +84,7 @@ void acc_kernels(int cond) { #pragma acc kernels if(cond == 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[EQ_RES:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES]] : !cir.bool to i1 @@ -94,11 +94,11 @@ void acc_kernels(int cond) { #pragma acc kernels if(cond == 1) self(cond == 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[EQ_RES_IF:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST_IF:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES_IF]] : !cir.bool to i1 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[EQ_RES_SELF:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[TWO_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST_SELF:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES_SELF]] : !cir.bool to i1 @@ -108,7 +108,7 @@ void acc_kernels(int cond) { #pragma acc kernels num_workers(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.kernels num_workers(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.terminator @@ -116,7 +116,7 @@ void acc_kernels(int cond) { #pragma acc kernels num_workers(cond) device_type(nvidia) num_workers(2u) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !u32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !u32i to ui32 @@ -126,7 +126,7 @@ void acc_kernels(int cond) { #pragma acc kernels num_workers(cond) device_type(nvidia, host) num_workers(2) device_type(radeon) num_workers(3) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -138,7 +138,7 @@ void acc_kernels(int cond) { #pragma acc kernels num_workers(cond) device_type(nvidia) num_workers(2) device_type(radeon, multicore) num_workers(3) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -160,7 +160,7 @@ void acc_kernels(int cond) { #pragma acc kernels vector_length(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.kernels vector_length(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.terminator @@ -168,7 +168,7 @@ void acc_kernels(int cond) { #pragma acc kernels vector_length(cond) device_type(nvidia) vector_length(2u) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !u32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !u32i to ui32 @@ -178,7 +178,7 @@ void acc_kernels(int cond) { #pragma acc kernels vector_length(cond) device_type(nvidia, host) vector_length(2) device_type(radeon) vector_length(3) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -190,7 +190,7 @@ void acc_kernels(int cond) { #pragma acc kernels vector_length(cond) device_type(nvidia) vector_length(2) device_type(radeon, multicore) vector_length(3) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -218,7 +218,7 @@ void acc_kernels(int cond) { #pragma acc kernels async(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.kernels async(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.terminator @@ -234,7 +234,7 @@ void acc_kernels(int cond) { {} // CHECK-NEXT: %[[THREE_LITERAL:.*]] = cir.const #cir.int<3> : !s32i // CHECK-NEXT: %[[THREE_CAST:.*]] = builtin.unrealized_conversion_cast %[[THREE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.kernels async(%[[THREE_CAST]] : si32, %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.terminator @@ -242,7 +242,7 @@ void acc_kernels(int cond) { #pragma acc kernels async device_type(nvidia, radeon) async(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.kernels async([#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.terminator @@ -266,7 +266,7 @@ void acc_kernels(int cond) { #pragma acc kernels num_gangs(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.kernels num_gangs({%[[CONV_CAST]] : si32}) { // CHECK-NEXT: acc.terminator @@ -276,7 +276,7 @@ void acc_kernels(int cond) { {} // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.kernels num_gangs({%[[ONE_CAST]] : si32}, {%[[CONV_CAST]] : si32} [#acc.device_type]) { // CHECK-NEXT: acc.terminator @@ -294,7 +294,7 @@ void acc_kernels(int cond) { #pragma acc kernels num_gangs(cond) device_type(radeon, nvidia) num_gangs(4) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[FOUR_LITERAL:.*]] = cir.const #cir.int<4> : !s32i // CHECK-NEXT: %[[FOUR_CAST:.*]] = builtin.unrealized_conversion_cast %[[FOUR_LITERAL]] : !s32i to si32 @@ -342,7 +342,7 @@ void acc_kernels(int cond) { #pragma acc kernels wait(devnum: cond : 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -352,11 +352,11 @@ void acc_kernels(int cond) { #pragma acc kernels wait(devnum: cond : 1) device_type(nvidia) wait(devnum: cond : 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -366,7 +366,7 @@ void acc_kernels(int cond) { #pragma acc kernels wait(devnum: cond : 1, 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -378,13 +378,13 @@ void acc_kernels(int cond) { #pragma acc kernels wait(devnum: cond : 1, 2) device_type(nvidia, radeon) wait(devnum: cond : 1, 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -396,7 +396,7 @@ void acc_kernels(int cond) { #pragma acc kernels wait(cond, 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -406,7 +406,7 @@ void acc_kernels(int cond) { #pragma acc kernels wait(queues: cond, 1) device_type(radeon) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 diff --git a/clang/test/CIR/CodeGenOpenACC/loop.cpp b/clang/test/CIR/CodeGenOpenACC/loop.cpp index 4b7a7e7366323..db94e2819b301 100644 --- a/clang/test/CIR/CodeGenOpenACC/loop.cpp +++ b/clang/test/CIR/CodeGenOpenACC/loop.cpp @@ -205,7 +205,7 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop worker(N) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop worker(%[[N_CONV]] : si32) { // CHECK: acc.yield @@ -219,7 +219,7 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop worker(N) device_type(nvidia, radeon) worker for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop worker([#acc.device_type, #acc.device_type], %[[N_CONV]] : si32) { // CHECK: acc.yield @@ -227,7 +227,7 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop worker device_type(nvidia, radeon) worker(N) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop worker([#acc.device_type], %[[N_CONV]] : si32 [#acc.device_type], %[[N_CONV]] : si32 [#acc.device_type]) { // CHECK: acc.yield @@ -235,9 +235,9 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop worker(N) device_type(nvidia, radeon) worker(N + 1) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD2]], %[[ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 @@ -247,7 +247,7 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop device_type(nvidia, radeon) worker(num:N + 1) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD]], %[[ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 @@ -261,7 +261,7 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop vector(N) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop vector(%[[N_CONV]] : si32) { // CHECK: acc.yield @@ -275,7 +275,7 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop vector(N) device_type(nvidia, radeon) vector for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.loop vector([#acc.device_type, #acc.device_type], %[[N_CONV]] : si32) { // CHECK: acc.yield @@ -283,9 +283,9 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop vector(N) device_type(nvidia, radeon) vector(N + 1) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD2]], %[[ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 @@ -295,7 +295,7 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop device_type(nvidia, radeon) vector(length:N + 1) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD]], %[[ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 @@ -311,13 +311,13 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { #pragma acc loop worker(N) vector(N) device_type(nvidia) worker(N) vector(N) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV2:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD2]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD3:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD3:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV3:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD3]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD4:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD4:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV4:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD4]] : !s32i to si32 // CHECK-NEXT: acc.loop worker(%[[N_CONV]] : si32, %[[N_CONV3]] : si32 [#acc.device_type]) vector(%[[N_CONV2]] : si32, %[[N_CONV4]] : si32 [#acc.device_type]) { // CHECK: acc.yield @@ -346,7 +346,7 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { // CHECK-NEXT: } loc #pragma acc loop gang(static:N, dim: 1) device_type(nvidia, radeon) gang(static:*, dim : 2) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_CONST:.*]] = arith.constant 1 : i64 // CHECK-NEXT: %[[STAR_CONST:.*]] = arith.constant -1 : i64 @@ -360,16 +360,16 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { { #pragma acc loop gang(num:N) device_type(nvidia, radeon) gang(num:N) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV2:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD2]] : !s32i to si32 // CHECK-NEXT: acc.loop gang({num=%[[N_CONV]] : si32}, {num=%[[N_CONV2]] : si32} [#acc.device_type], {num=%[[N_CONV2]] : si32} [#acc.device_type]) { // CHECK: acc.yield // CHECK-NEXT: } loc #pragma acc loop gang(static:N) device_type(nvidia) gang(static:*) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[STAR_CONST:.*]] = arith.constant -1 : i64 // CHECK-NEXT: acc.loop gang({static=%[[N_CONV]] : si32}, {static=%[[STAR_CONST]] : i64} [#acc.device_type]) { @@ -377,14 +377,14 @@ extern "C" void acc_loop(int *A, int *B, int *C, int N) { // CHECK-NEXT: } loc #pragma acc loop gang(static:N, num: N + 1) device_type(nvidia) gang(static:*, num : N + 2) for(unsigned I = 0; I < N; ++I); - // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[N_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD2:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CIR_ONE_CONST:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[N_PLUS_ONE:.*]] = cir.binop(add, %[[N_LOAD2]], %[[CIR_ONE_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_ONE]] : !s32i to si32 // CHECK-NEXT: %[[STAR_CONST:.*]] = arith.constant -1 : i64 - // CHECK-NEXT: %[[N_LOAD3:.*]] = cir.load %[[ALLOCA_N]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[N_LOAD3:.*]] = cir.load{{.*}} %[[ALLOCA_N]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CIR_TWO_CONST:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[N_PLUS_TWO:.*]] = cir.binop(add, %[[N_LOAD3]], %[[CIR_TWO_CONST]]) nsw : !s32i // CHECK-NEXT: %[[N_PLUS_TWO_CONV:.*]] = builtin.unrealized_conversion_cast %[[N_PLUS_TWO]] : !s32i to si32 diff --git a/clang/test/CIR/CodeGenOpenACC/parallel.c b/clang/test/CIR/CodeGenOpenACC/parallel.c index 54b3cd024123f..a6d60ee3ad271 100644 --- a/clang/test/CIR/CodeGenOpenACC/parallel.c +++ b/clang/test/CIR/CodeGenOpenACC/parallel.c @@ -47,7 +47,7 @@ void acc_parallel(int cond) { #pragma acc parallel self(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.parallel self(%[[CONV_CAST]]) { @@ -65,7 +65,7 @@ void acc_parallel(int cond) { #pragma acc parallel if(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.parallel if(%[[CONV_CAST]]) { @@ -83,7 +83,7 @@ void acc_parallel(int cond) { #pragma acc parallel if(cond == 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[EQ_RES:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES]] : !cir.bool to i1 @@ -93,11 +93,11 @@ void acc_parallel(int cond) { #pragma acc parallel if(cond == 1) self(cond == 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[EQ_RES_IF:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST_IF:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES_IF]] : !cir.bool to i1 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[EQ_RES_SELF:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[TWO_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST_SELF:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES_SELF]] : !cir.bool to i1 @@ -107,7 +107,7 @@ void acc_parallel(int cond) { #pragma acc parallel num_workers(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel num_workers(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.yield @@ -115,7 +115,7 @@ void acc_parallel(int cond) { #pragma acc parallel num_workers(cond) device_type(nvidia) num_workers(2u) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !u32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !u32i to ui32 @@ -125,7 +125,7 @@ void acc_parallel(int cond) { #pragma acc parallel num_workers(cond) device_type(nvidia, host) num_workers(2) device_type(radeon) num_workers(3) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -137,7 +137,7 @@ void acc_parallel(int cond) { #pragma acc parallel num_workers(cond) device_type(nvidia) num_workers(2) device_type(radeon, multicore) num_workers(4) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -159,7 +159,7 @@ void acc_parallel(int cond) { #pragma acc parallel vector_length(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel vector_length(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.yield @@ -167,7 +167,7 @@ void acc_parallel(int cond) { #pragma acc parallel vector_length(cond) device_type(nvidia) vector_length(2u) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !u32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !u32i to ui32 @@ -177,7 +177,7 @@ void acc_parallel(int cond) { #pragma acc parallel vector_length(cond) device_type(nvidia, host) vector_length(2) device_type(radeon) vector_length(3) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -189,7 +189,7 @@ void acc_parallel(int cond) { #pragma acc parallel vector_length(cond) device_type(nvidia) vector_length(2) device_type(radeon, multicore) vector_length(4) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -217,7 +217,7 @@ void acc_parallel(int cond) { #pragma acc parallel async(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel async(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.yield @@ -233,7 +233,7 @@ void acc_parallel(int cond) { {} // CHECK-NEXT: %[[THREE_LITERAL:.*]] = cir.const #cir.int<3> : !s32i // CHECK-NEXT: %[[THREE_CAST:.*]] = builtin.unrealized_conversion_cast %[[THREE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel async(%[[THREE_CAST]] : si32, %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.yield @@ -241,7 +241,7 @@ void acc_parallel(int cond) { #pragma acc parallel async device_type(nvidia, radeon) async(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel async([#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.yield @@ -265,7 +265,7 @@ void acc_parallel(int cond) { #pragma acc parallel num_gangs(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel num_gangs({%[[CONV_CAST]] : si32}) { // CHECK-NEXT: acc.yield @@ -275,7 +275,7 @@ void acc_parallel(int cond) { {} // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -287,7 +287,7 @@ void acc_parallel(int cond) { {} // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.parallel num_gangs({%[[ONE_CAST]] : si32}, {%[[CONV_CAST]] : si32} [#acc.device_type]) { // CHECK-NEXT: acc.yield @@ -297,7 +297,7 @@ void acc_parallel(int cond) { {} // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -315,7 +315,7 @@ void acc_parallel(int cond) { {} // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 @@ -369,7 +369,7 @@ void acc_parallel(int cond) { #pragma acc parallel wait(devnum: cond : 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -379,11 +379,11 @@ void acc_parallel(int cond) { #pragma acc parallel wait(devnum: cond : 1) device_type(nvidia) wait(devnum: cond : 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -393,7 +393,7 @@ void acc_parallel(int cond) { #pragma acc parallel wait(devnum: cond : 1, 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -405,13 +405,13 @@ void acc_parallel(int cond) { #pragma acc parallel wait(devnum: cond : 1, 2) device_type(nvidia, radeon) wait(devnum: cond : 1, 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -423,7 +423,7 @@ void acc_parallel(int cond) { #pragma acc parallel wait(cond, 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -433,7 +433,7 @@ void acc_parallel(int cond) { #pragma acc parallel wait(queues: cond, 1) device_type(radeon) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 diff --git a/clang/test/CIR/CodeGenOpenACC/serial.c b/clang/test/CIR/CodeGenOpenACC/serial.c index 90756b04d8f52..cf077ca2834e5 100644 --- a/clang/test/CIR/CodeGenOpenACC/serial.c +++ b/clang/test/CIR/CodeGenOpenACC/serial.c @@ -48,7 +48,7 @@ void acc_serial(int cond) { #pragma acc serial self(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.serial self(%[[CONV_CAST]]) { @@ -66,7 +66,7 @@ void acc_serial(int cond) { #pragma acc serial if(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.serial if(%[[CONV_CAST]]) { @@ -84,7 +84,7 @@ void acc_serial(int cond) { #pragma acc serial if(cond == 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[EQ_RES:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES]] : !cir.bool to i1 @@ -94,11 +94,11 @@ void acc_serial(int cond) { #pragma acc serial if(cond == 1) self(cond == 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[EQ_RES_IF:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[ONE_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST_IF:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES_IF]] : !cir.bool to i1 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[EQ_RES_SELF:.*]] = cir.cmp(eq, %[[COND_LOAD]], %[[TWO_LITERAL]]) : !s32i, !cir.bool // CHECK-NEXT: %[[CONV_CAST_SELF:.*]] = builtin.unrealized_conversion_cast %[[EQ_RES_SELF]] : !cir.bool to i1 @@ -114,7 +114,7 @@ void acc_serial(int cond) { #pragma acc serial async(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.serial async(%[[CONV_CAST]] : si32) { // CHECK-NEXT: acc.yield @@ -130,7 +130,7 @@ void acc_serial(int cond) { {} // CHECK-NEXT: %[[THREE_LITERAL:.*]] = cir.const #cir.int<3> : !s32i // CHECK-NEXT: %[[THREE_CAST:.*]] = builtin.unrealized_conversion_cast %[[THREE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.serial async(%[[THREE_CAST]] : si32, %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.yield @@ -138,7 +138,7 @@ void acc_serial(int cond) { #pragma acc serial async device_type(nvidia, radeon) async(cond) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.serial async([#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type], %[[CONV_CAST]] : si32 [#acc.device_type]) { // CHECK-NEXT: acc.yield @@ -192,7 +192,7 @@ void acc_serial(int cond) { #pragma acc serial wait(devnum: cond : 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -202,11 +202,11 @@ void acc_serial(int cond) { #pragma acc serial wait(devnum: cond : 1) device_type(nvidia) wait(devnum: cond : 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -216,7 +216,7 @@ void acc_serial(int cond) { #pragma acc serial wait(devnum: cond : 1, 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -228,13 +228,13 @@ void acc_serial(int cond) { #pragma acc serial wait(devnum: cond : 1, 2) device_type(nvidia, radeon) wait(devnum: cond : 1, 2) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 // CHECK-NEXT: %[[TWO_LITERAL:.*]] = cir.const #cir.int<2> : !s32i // CHECK-NEXT: %[[TWO_CAST:.*]] = builtin.unrealized_conversion_cast %[[TWO_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST2:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST2:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -246,7 +246,7 @@ void acc_serial(int cond) { #pragma acc serial wait(cond, 1) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -256,7 +256,7 @@ void acc_serial(int cond) { #pragma acc serial wait(queues: cond, 1) device_type(radeon) {} - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 diff --git a/clang/test/CIR/CodeGenOpenACC/set.c b/clang/test/CIR/CodeGenOpenACC/set.c index 3a8a9c24569e5..ced581680c037 100644 --- a/clang/test/CIR/CodeGenOpenACC/set.c +++ b/clang/test/CIR/CodeGenOpenACC/set.c @@ -13,7 +13,7 @@ void acc_set(int cond) { // CHECK-NEXT: acc.set attributes {device_type = #acc.device_type} #pragma acc set default_async(cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.set default_async(%[[COND_CONV]] : si32) @@ -23,9 +23,9 @@ void acc_set(int cond) { // CHECK-NEXT: acc.set default_async(%[[ONE_CONV]] : si32) #pragma acc set device_num(cond) if (cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[BOOL_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.set device_num(%[[COND_CONV]] : si32) if(%[[BOOL_CONV]]) @@ -33,9 +33,9 @@ void acc_set(int cond) { #pragma acc set device_type(radeon) default_async(1) device_num(cond) if (cond) // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CONV:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[BOOL_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.set default_async(%[[ONE_CONV]] : si32) device_num(%[[COND_CONV]] : si32) if(%[[BOOL_CONV]]) attributes {device_type = #acc.device_type} diff --git a/clang/test/CIR/CodeGenOpenACC/shutdown.c b/clang/test/CIR/CodeGenOpenACC/shutdown.c index 99b840a723057..e8ab6bd75d0e9 100644 --- a/clang/test/CIR/CodeGenOpenACC/shutdown.c +++ b/clang/test/CIR/CodeGenOpenACC/shutdown.c @@ -21,7 +21,7 @@ void acc_shutdown(int cond) { // CHECK-NEXT: acc.shutdown attributes {device_types = [#acc.device_type, #acc.device_type]} #pragma acc shutdown if(cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[BOOL_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.shutdown if(%[[BOOL_CONV]]) @@ -33,7 +33,7 @@ void acc_shutdown(int cond) { // CHECK-NEXT: acc.shutdown if(%[[BOOL_CONV]]) #pragma acc shutdown device_num(cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.shutdown device_num(%[[COND_CONV]] : si32) @@ -43,10 +43,10 @@ void acc_shutdown(int cond) { // CHECK-NEXT: acc.shutdown device_num(%[[ONE_CONV]] : si32) #pragma acc shutdown if(cond) device_num(cond) device_type(*) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[BOOL_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_CAST]] : !cir.bool to i1 - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[COND_CONV:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.shutdown device_num(%[[COND_CONV]] : si32) if(%[[BOOL_CONV]]) attributes {device_types = [#acc.device_type]} } diff --git a/clang/test/CIR/CodeGenOpenACC/wait.c b/clang/test/CIR/CodeGenOpenACC/wait.c index c8e345d4b9a0e..ec2ab6e9446cc 100644 --- a/clang/test/CIR/CodeGenOpenACC/wait.c +++ b/clang/test/CIR/CodeGenOpenACC/wait.c @@ -9,7 +9,7 @@ void acc_wait(int cond) { // CHECK-NEXT: acc.wait #pragma acc wait if (cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: acc.wait if(%[[CONV_CAST]]) @@ -18,7 +18,7 @@ void acc_wait(int cond) { // CHECK-NEXT: acc.wait async loc #pragma acc wait async(cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: acc.wait async(%[[CONV_CAST]] : si32) loc @@ -36,7 +36,7 @@ void acc_wait(int cond) { #pragma acc wait(queues:1) if (cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i @@ -44,7 +44,7 @@ void acc_wait(int cond) { // CHECK-NEXT: acc.wait(%[[ONE_CAST]] : si32) if(%[[CONV_CAST]]) #pragma acc wait(queues:1, 2) async(cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_LOAD]] : !s32i to si32 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i // CHECK-NEXT: %[[ONE_CAST:.*]] = builtin.unrealized_conversion_cast %[[ONE_LITERAL]] : !s32i to si32 @@ -53,7 +53,7 @@ void acc_wait(int cond) { // CHECK-NEXT: acc.wait(%[[ONE_CAST]], %[[TWO_CAST]] : si32, si32) async(%[[CONV_CAST]] : si32) loc #pragma acc wait(devnum:1: 2, 3) if (cond) - // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load %[[COND]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[COND_LOAD:.*]] = cir.load{{.*}} %[[COND]] : !cir.ptr, !s32i // CHECK-NEXT: %[[BOOL_CAST:.*]] = cir.cast(int_to_bool, %[[COND_LOAD]] : !s32i), !cir.bool // CHECK-NEXT: %[[CONV_CAST:.*]] = builtin.unrealized_conversion_cast %[[BOOL_CAST]] : !cir.bool to i1 // CHECK-NEXT: %[[ONE_LITERAL:.*]] = cir.const #cir.int<1> : !s32i diff --git a/clang/test/CIR/Lowering/array.cpp b/clang/test/CIR/Lowering/array.cpp index d4efd4f82ba49..4d9161d77663f 100644 --- a/clang/test/CIR/Lowering/array.cpp +++ b/clang/test/CIR/Lowering/array.cpp @@ -1,4 +1,5 @@ -// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o - 2>&1 | FileCheck %s +// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll +// RUN: FileCheck --input-file=%t-cir.ll %s int a[10]; // CHECK: @a = dso_local global [10 x i32] zeroinitializer @@ -40,7 +41,7 @@ void func() { // CHECK-NEXT: %[[INIT_2:.*]] = alloca i32, i64 1, align 4 // CHECK-NEXT: %[[ARR_PTR:.*]] = getelementptr i32, ptr %[[ARR_ALLOCA]], i32 0 // CHECK-NEXT: %[[ELE_PTR:.*]] = getelementptr i32, ptr %[[ARR_PTR]], i64 0 -// CHECK-NEXT: %[[TMP:.*]] = load i32, ptr %[[ELE_PTR]], align 4 +// CHECK-NEXT: %[[TMP:.*]] = load i32, ptr %[[ELE_PTR]], align 16 // CHECK-NEXT: store i32 %[[TMP]], ptr %[[INIT]], align 4 // CHECK-NEXT: %[[ARR_PTR:.*]] = getelementptr i32, ptr %[[ARR_ALLOCA]], i32 0 // CHECK-NEXT: %[[ELE_PTR:.*]] = getelementptr i32, ptr %[[ARR_PTR]], i64 1 diff --git a/clang/test/CIR/Lowering/local-vars.cpp b/clang/test/CIR/Lowering/local-vars.cpp index fc8130e2c1d80..fe46c57918481 100644 --- a/clang/test/CIR/Lowering/local-vars.cpp +++ b/clang/test/CIR/Lowering/local-vars.cpp @@ -1,4 +1,5 @@ -// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o - 2>&1 | FileCheck %s +// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll +// RUN: FileCheck -input-file=%t-cir.ll %s void test() { int i = 1; @@ -42,13 +43,13 @@ void test() { // CHECK: %[[UID_PTR:.*]] = alloca double, i64 1, align 8 // CHECK: %[[UIB_PTR:.*]] = alloca i8, i64 1, align 1 // CHECK: store i32 1, ptr %[[I_PTR]], align 4 -// CHECK: store i64 2, ptr %[[L_PTR]], align 4 +// CHECK: store i64 2, ptr %[[L_PTR]], align 8 // CHECK: store float 3.000000e+00, ptr %[[F_PTR]], align 4 // CHECK: store double 4.000000e+00, ptr %[[D_PTR]], align 8 // CHECK: store i8 1, ptr %[[B1_PTR]], align 1 // CHECK: store i8 0, ptr %[[B2_PTR]], align 1 // CHECK: store i32 1, ptr %[[CI_PTR]], align 4 -// CHECK: store i64 2, ptr %[[CL_PTR]], align 4 +// CHECK: store i64 2, ptr %[[CL_PTR]], align 8 // CHECK: store float 3.000000e+00, ptr %[[CF_PTR]], align 4 // CHECK: store double 4.000000e+00, ptr %[[CD_PTR]], align 8 // CHECK: store i8 1, ptr %[[CB1_PTR]], align 1 diff --git a/clang/test/CIR/Lowering/unary-expr-or-type-trait.cpp b/clang/test/CIR/Lowering/unary-expr-or-type-trait.cpp index edf6ed7f58757..7c42d00d6d19a 100644 --- a/clang/test/CIR/Lowering/unary-expr-or-type-trait.cpp +++ b/clang/test/CIR/Lowering/unary-expr-or-type-trait.cpp @@ -1,47 +1,48 @@ -// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o - 2>&1 | FileCheck %s +// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll +// RUN: FileCheck -input-file=%t-cir.ll %s void foo() { unsigned long b = sizeof(bool); - // CHECK: store i64 1, ptr {{%.*}}, align 4 + // CHECK: store i64 1, ptr {{%.*}}, align 8 unsigned long i = sizeof(int); - // CHECK: store i64 4, ptr {{%.*}}, align 4 + // CHECK: store i64 4, ptr {{%.*}}, align 8 unsigned long l = sizeof(long); - // CHECK: store i64 8, ptr {{%.*}}, align 4 + // CHECK: store i64 8, ptr {{%.*}}, align 8 unsigned long f = sizeof(float); - // CHECK: store i64 4, ptr {{%.*}}, align 4 + // CHECK: store i64 4, ptr {{%.*}}, align 8 unsigned long d = sizeof(double); - // CHECK: store i64 8, ptr {{%.*}}, align 4 + // CHECK: store i64 8, ptr {{%.*}}, align 8 unsigned long iArr = sizeof(float[5]); - // CHECK: store i64 20, ptr {{%.*}}, align 4 + // CHECK: store i64 20, ptr {{%.*}}, align 8 unsigned long dArr = sizeof(double[5]); - // CHECK: store i64 40, ptr {{%.*}}, align 4 + // CHECK: store i64 40, ptr {{%.*}}, align 8 } void foo2() { unsigned long b = alignof(bool); - // CHECK: store i64 1, ptr {{%.*}}, align 4 + // CHECK: store i64 1, ptr {{%.*}}, align 8 unsigned long i = alignof(int); - // CHECK: store i64 4, ptr {{%.*}}, align 4 + // CHECK: store i64 4, ptr {{%.*}}, align 8 unsigned long l = alignof(long); - // CHECK: store i64 8, ptr {{%.*}}, align 4 + // CHECK: store i64 8, ptr {{%.*}}, align 8 unsigned long f = alignof(float); - // CHECK: store i64 4, ptr {{%.*}}, align 4 + // CHECK: store i64 4, ptr {{%.*}}, align 8 unsigned long d = alignof(double); - // CHECK: store i64 8, ptr {{%.*}}, align 4 + // CHECK: store i64 8, ptr {{%.*}}, align 8 unsigned long iArr = alignof(int[5]); - // CHECK: store i64 4, ptr {{%.*}}, align 4 + // CHECK: store i64 4, ptr {{%.*}}, align 8 unsigned long dArr = alignof(double[5]); - // CHECK: store i64 8, ptr {{%.*}}, align 4 + // CHECK: store i64 8, ptr {{%.*}}, align 8 }