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[RISCV] Add shlcofideleg extension #141572

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Merged
wangpc-pp merged 3 commits into from
May 30, 2025
Merged

[RISCV] Add shlcofideleg extension #141572

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385ae30
[RISCV] Add shlcofideleg extension
punkyc May 27, 2025
158d7f8
update ReleaseNotes.md
punkyc May 28, 2025
78759a5
update
punkyc May 30, 2025
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1 change: 1 addition & 0 deletions clang/test/Driver/print-supported-extensions-riscv.c
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Expand Up @@ -119,6 +119,7 @@
// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor)
// CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: shgatpa 1.0 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
// CHECK-NEXT: shlcofideleg 1.0 'Shlcofideleg' (Delegating LCOFI interrupts to VS-mode)
// CHECK-NEXT: shtvala 1.0 'Shtvala' (htval provides all needed values)
// CHECK-NEXT: shvsatpa 1.0 'Shvsatpa' (vsatp supports all modes supported by satp)
// CHECK-NEXT: shvstvala 1.0 'Shvstvala' (vstval provides all needed values)
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9 changes: 9 additions & 0 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -24,6 +24,7 @@
// CHECK-NOT: __riscv_sha {{.*$}}
// CHECK-NOT: __riscv_shcounterenw {{.*$}}
// CHECK-NOT: __riscv_shgatpa {{.*$}}
// CHECK-NOT: __riscv_shlcofideleg {{.*$}}
// CHECK-NOT: __riscv_shtvala {{.*$}}
// CHECK-NOT: __riscv_shvsatpa {{.*$}}
// CHECK-NOT: __riscv_shvstvala {{.*$}}
Expand Down Expand Up @@ -370,6 +371,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SHGATPA-EXT %s
// CHECK-SHGATPA-EXT: __riscv_shgatpa 1000000{{$}}

// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ishlcofideleg -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SHLCOFIDELEG-EXT %s
// RUN: %clang --target=riscv64-unknown-linux-gnu \
// RUN: -march=rv64ishlcofideleg -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SHLCOFIDELEG-EXT %s
// CHECK-SHLCOFIDELEG-EXT: __riscv_shlcofideleg 1000000{{$}}

// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ishtvala -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SHTVALA-EXT %s
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1 change: 1 addition & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -123,6 +123,7 @@ on support follow.
``Sha`` Supported
``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Shlcofideleg`` Supported
``Shtvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Shvsatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Shvstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -201,6 +201,7 @@ Changes to the RISC-V Backend
* Adds experimental assembler support for the SiFive Xsfmm* Attached Matrix
Extensions.
* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
* The `Shlcofideleg` extension was added.

Changes to the WebAssembly Backend
----------------------------------
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -906,6 +906,10 @@ def FeatureStdExtShvsatpa
: RISCVExtension<1, 0,
"vsatp supports all modes supported by satp">;

def FeatureStdExtShlcofideleg
: RISCVExtension<1, 0,
"Delegating LCOFI Interrupts to VS-mode">;

def FeatureStdExtSmaia
: RISCVExtension<1, 0,
"Advanced Interrupt Architecture Machine Level">;
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4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -47,6 +47,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SHCOUNTERENW %s
; RUN: llc -mtriple=riscv32 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHGATPA %s
; RUN: llc -mtriple=riscv32 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSATPA %s
; RUN: llc -mtriple=riscv32 -mattr=+shlcofideleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SHLCOFIDELEG %s
; RUN: llc -mtriple=riscv32 -mattr=+ssccfg %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCFG %s
; RUN: llc -mtriple=riscv32 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCPTR %s
; RUN: llc -mtriple=riscv32 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOFPMF %s
Expand Down Expand Up @@ -222,6 +223,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SHCOUNTERENW %s
; RUN: llc -mtriple=riscv64 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHGATPA %s
; RUN: llc -mtriple=riscv64 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSATPA %s
; RUN: llc -mtriple=riscv64 -mattr=+shlcofideleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SHLCOFIDELEG %s
; RUN: llc -mtriple=riscv64 -mattr=+ssccfg %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCFG %s
; RUN: llc -mtriple=riscv64 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCPTR %s
; RUN: llc -mtriple=riscv64 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOFPMF %s
Expand Down Expand Up @@ -396,6 +398,7 @@
; RV32SHCOUNTERENW: .attribute 5, "rv32i2p1_shcounterenw1p0"
; RV32SHGATPA: .attribute 5, "rv32i2p1_shgatpa1p0"
; RV32SHVSATPA: .attribute 5, "rv32i2p1_shvsatpa1p0"
; RV32SHLCOFIDELEG: .attribute 5, "rv32i2p1_shlcofideleg1p0"
; RV32SSCCFG: .attribute 5, "rv32i2p1_ssccfg1p0"
; RV32SSCCPTR: .attribute 5, "rv32i2p1_ssccptr1p0"
; RV32SSCOFPMF: .attribute 5, "rv32i2p1_sscofpmf1p0"
Expand Down Expand Up @@ -572,6 +575,7 @@
; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0"
; RV64SHGATPA: .attribute 5, "rv64i2p1_shgatpa1p0"
; RV64SHVSATPA: .attribute 5, "rv64i2p1_shvsatpa1p0"
; RV64SHLCOFIDELEG: .attribute 5, "rv64i2p1_shlcofideleg1p0"
; RV64SSCCFG: .attribute 5, "rv64i2p1_ssccfg1p0"
; RV64SSCCPTR: .attribute 5, "rv64i2p1_ssccptr1p0"
; RV64SSCOFPMF: .attribute 5, "rv64i2p1_sscofpmf1p0"
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3 changes: 3 additions & 0 deletions llvm/test/MC/RISCV/attribute-arch.s
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Expand Up @@ -309,6 +309,9 @@
.attribute arch, "rv32i_shvsatpa1p0"
# CHECK: attribute 5, "rv32i2p1_shvsatpa1p0"

.attribute arch, "rv32i_shlcofideleg1p0"
# CHECK: attribute 5, "rv32i2p1_shlcofideleg1p0"

.attribute arch, "rv32i_shtvala1p0"
# CHECK: attribute 5, "rv32i2p1_shtvala1p0"

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1 change: 1 addition & 0 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1090,6 +1090,7 @@ R"(All available -march extensions for RISC-V
sha 1.0
shcounterenw 1.0
shgatpa 1.0
shlcofideleg 1.0
shtvala 1.0
shvsatpa 1.0
shvstvala 1.0
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