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AMDGPU: Cost model for minimumnum/maximumnum #141946

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Merged
merged 1 commit into from
Jun 17, 2025
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AMDGPU: Cost model for minimumnum/maximumnum #141946

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19 changes: 19 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -685,6 +685,8 @@ static bool intrinsicHasPackedVectorBenefit(Intrinsic::ID ID) {
case Intrinsic::fma:
case Intrinsic::fmuladd:
case Intrinsic::copysign:
case Intrinsic::minimumnum:
case Intrinsic::maximumnum:
case Intrinsic::canonicalize:
// There's a small benefit to using vector ops in the legalized code.
case Intrinsic::round:
Expand Down Expand Up @@ -742,6 +744,23 @@ GCNTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
break;
case Intrinsic::copysign:
return NElts * getFullRateInstrCost();
case Intrinsic::minimumnum:
case Intrinsic::maximumnum: {
// Instruction + 2 canonicalizes. For cases that need type promotion, we the
// promotion takes the place of the canonicalize.
Comment on lines +749 to +750
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@Pierre-vh Pierre-vh Jun 2, 2025

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Suggested change
// Instruction + 2 canonicalizes. For cases that need type promotion, we the
// promotion takes the place of the canonicalize.
// Instruction + 2 canonicalizes. For cases that need type promotion, the
// promotion takes the place of the canonicalize.

unsigned NumOps = 3;
if (const IntrinsicInst *II = ICA.getInst()) {
// Directly legal with ieee=0
// TODO: Not directly legal with strictfp
if (fpenvIEEEMode(*II) == KnownIEEEMode::Off)
NumOps = 1;
}

unsigned BaseRate =
SLT == MVT::f64 ? get64BitInstrCost(CostKind) : getFullRateInstrCost();
InstRate = BaseRate * NumOps;
break;
}
case Intrinsic::canonicalize: {
InstRate =
SLT == MVT::f64 ? get64BitInstrCost(CostKind) : getFullRateInstrCost();
Expand Down
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