diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp index 98a32f9225ba9..14101e57f5143 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -1090,22 +1090,6 @@ bool AMDGPUCallLowering::areCalleeOutgoingArgsTailCallable( return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs); } -/// Return true if the calling convention is one that we can guarantee TCO for. -static bool canGuaranteeTCO(CallingConv::ID CC) { - return CC == CallingConv::Fast; -} - -/// Return true if we might ever do TCO for calls with this calling convention. -static bool mayTailCallThisCC(CallingConv::ID CC) { - switch (CC) { - case CallingConv::C: - case CallingConv::AMDGPU_Gfx: - return true; - default: - return canGuaranteeTCO(CC); - } -} - bool AMDGPUCallLowering::isEligibleForTailCallOptimization( MachineIRBuilder &B, CallLoweringInfo &Info, SmallVectorImpl &InArgs, SmallVectorImpl &OutArgs) const { @@ -1130,7 +1114,7 @@ bool AMDGPUCallLowering::isEligibleForTailCallOptimization( if (!CallerPreserved) return false; - if (!mayTailCallThisCC(CalleeCC)) { + if (!AMDGPU::mayTailCallThisCC(CalleeCC)) { LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n"); return false; } @@ -1144,8 +1128,10 @@ bool AMDGPUCallLowering::isEligibleForTailCallOptimization( } // If we have -tailcallopt, then we're done. - if (MF.getTarget().Options.GuaranteedTailCallOpt) - return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv(); + if (MF.getTarget().Options.GuaranteedTailCallOpt) { + return AMDGPU::canGuaranteeTCO(CalleeCC) && + CalleeCC == CallerF.getCallingConv(); + } // Verify that the incoming and outgoing arguments from the callee are // safe to tail call. diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp index 6568d9031987e..241dbd63eb5c0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp @@ -125,13 +125,6 @@ void getUsesOfLDSByFunction(const CallGraph &CG, Module &M, } bool isKernelLDS(const Function *F) { - // Some weirdness here. AMDGPU::isKernelCC does not call into - // AMDGPU::isKernel with the calling conv, it instead calls into - // isModuleEntryFunction which returns true for more calling conventions - // than AMDGPU::isKernel does. There's a FIXME on AMDGPU::isKernel. - // There's also a test that checks that the LDS lowering does not hit on - // a graphics shader, denoted amdgpu_ps, so stay with the limited case. - // Putting LDS in the name of the function to draw attention to this. return AMDGPU::isKernel(F->getCallingConv()); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index f0a0c2113bf81..d59087839b0e1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -978,7 +978,9 @@ bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const { if (auto *Arg = dyn_cast(V); - Arg && AMDGPU::isKernelCC(Arg->getParent()) && !Arg->hasByRefAttr()) + Arg && + AMDGPU::isModuleEntryFunctionCC(Arg->getParent()->getCallingConv()) && + !Arg->hasByRefAttr()) return AMDGPUAS::GLOBAL_ADDRESS; const auto *LD = dyn_cast(V); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 1957e442dbabb..97a249259b5b4 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3574,21 +3574,6 @@ void SITargetLowering::passSpecialInputs( } } -static bool canGuaranteeTCO(CallingConv::ID CC) { - return CC == CallingConv::Fast; -} - -/// Return true if we might ever do TCO for calls with this calling convention. -static bool mayTailCallThisCC(CallingConv::ID CC) { - switch (CC) { - case CallingConv::C: - case CallingConv::AMDGPU_Gfx: - return true; - default: - return canGuaranteeTCO(CC); - } -} - bool SITargetLowering::isEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg, const SmallVectorImpl &Outs, @@ -3597,7 +3582,7 @@ bool SITargetLowering::isEligibleForTailCallOptimization( if (AMDGPU::isChainCC(CalleeCC)) return true; - if (!mayTailCallThisCC(CalleeCC)) + if (!AMDGPU::mayTailCallThisCC(CalleeCC)) return false; // For a divergent call target, we need to do a waterfall loop over the @@ -3619,7 +3604,7 @@ bool SITargetLowering::isEligibleForTailCallOptimization( bool CCMatch = CallerCC == CalleeCC; if (DAG.getTarget().Options.GuaranteedTailCallOpt) { - if (canGuaranteeTCO(CalleeCC) && CCMatch) + if (AMDGPU::canGuaranteeTCO(CalleeCC) && CCMatch) return true; return false; } diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 1233973da140d..c0cd43a9c35df 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -2124,71 +2124,6 @@ bool getHasDepthExport(const Function &F) { return F.getFnAttributeAsParsedInteger("amdgpu-depth-export", 0) != 0; } -bool isShader(CallingConv::ID cc) { - switch (cc) { - case CallingConv::AMDGPU_VS: - case CallingConv::AMDGPU_LS: - case CallingConv::AMDGPU_HS: - case CallingConv::AMDGPU_ES: - case CallingConv::AMDGPU_GS: - case CallingConv::AMDGPU_PS: - case CallingConv::AMDGPU_CS_Chain: - case CallingConv::AMDGPU_CS_ChainPreserve: - case CallingConv::AMDGPU_CS: - return true; - default: - return false; - } -} - -bool isGraphics(CallingConv::ID cc) { - return isShader(cc) || cc == CallingConv::AMDGPU_Gfx; -} - -bool isCompute(CallingConv::ID cc) { - return !isGraphics(cc) || cc == CallingConv::AMDGPU_CS; -} - -bool isEntryFunctionCC(CallingConv::ID CC) { - switch (CC) { - case CallingConv::AMDGPU_KERNEL: - case CallingConv::SPIR_KERNEL: - case CallingConv::AMDGPU_VS: - case CallingConv::AMDGPU_GS: - case CallingConv::AMDGPU_PS: - case CallingConv::AMDGPU_CS: - case CallingConv::AMDGPU_ES: - case CallingConv::AMDGPU_HS: - case CallingConv::AMDGPU_LS: - return true; - default: - return false; - } -} - -bool isModuleEntryFunctionCC(CallingConv::ID CC) { - switch (CC) { - case CallingConv::AMDGPU_Gfx: - return true; - default: - return isEntryFunctionCC(CC) || isChainCC(CC); - } -} - -bool isChainCC(CallingConv::ID CC) { - switch (CC) { - case CallingConv::AMDGPU_CS_Chain: - case CallingConv::AMDGPU_CS_ChainPreserve: - return true; - default: - return false; - } -} - -bool isKernelCC(const Function *Func) { - return AMDGPU::isModuleEntryFunctionCC(Func->getCallingConv()); -} - bool hasXNACK(const MCSubtargetInfo &STI) { return STI.hasFeature(AMDGPU::FeatureXNACK); } diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index e0534b2091f58..975a8908059c1 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -1306,16 +1306,61 @@ bool getHasColorExport(const Function &F); bool getHasDepthExport(const Function &F); LLVM_READNONE -bool isShader(CallingConv::ID CC); +constexpr bool isShader(CallingConv::ID CC) { + switch (CC) { + case CallingConv::AMDGPU_VS: + case CallingConv::AMDGPU_LS: + case CallingConv::AMDGPU_HS: + case CallingConv::AMDGPU_ES: + case CallingConv::AMDGPU_GS: + case CallingConv::AMDGPU_PS: + case CallingConv::AMDGPU_CS_Chain: + case CallingConv::AMDGPU_CS_ChainPreserve: + case CallingConv::AMDGPU_CS: + return true; + default: + return false; + } +} LLVM_READNONE -bool isGraphics(CallingConv::ID CC); +constexpr bool isGraphics(CallingConv::ID CC) { + return isShader(CC) || CC == CallingConv::AMDGPU_Gfx; +} LLVM_READNONE -bool isCompute(CallingConv::ID CC); +constexpr bool isCompute(CallingConv::ID CC) { + return !isGraphics(CC) || CC == CallingConv::AMDGPU_CS; +} LLVM_READNONE -bool isEntryFunctionCC(CallingConv::ID CC); +constexpr bool isEntryFunctionCC(CallingConv::ID CC) { + switch (CC) { + case CallingConv::AMDGPU_KERNEL: + case CallingConv::SPIR_KERNEL: + case CallingConv::AMDGPU_VS: + case CallingConv::AMDGPU_GS: + case CallingConv::AMDGPU_PS: + case CallingConv::AMDGPU_CS: + case CallingConv::AMDGPU_ES: + case CallingConv::AMDGPU_HS: + case CallingConv::AMDGPU_LS: + return true; + default: + return false; + } +} + +LLVM_READNONE +constexpr bool isChainCC(CallingConv::ID CC) { + switch (CC) { + case CallingConv::AMDGPU_CS_Chain: + case CallingConv::AMDGPU_CS_ChainPreserve: + return true; + default: + return false; + } +} // These functions are considered entrypoints into the current module, i.e. they // are allowed to be called from outside the current module. This is different @@ -1324,16 +1369,17 @@ bool isEntryFunctionCC(CallingConv::ID CC); // include functions that can be called from other functions inside or outside // the current module. Module entry functions are allowed to allocate LDS. LLVM_READNONE -bool isModuleEntryFunctionCC(CallingConv::ID CC); - -LLVM_READNONE -bool isChainCC(CallingConv::ID CC); - -bool isKernelCC(const Function *Func); +constexpr bool isModuleEntryFunctionCC(CallingConv::ID CC) { + switch (CC) { + case CallingConv::AMDGPU_Gfx: + return true; + default: + return isEntryFunctionCC(CC) || isChainCC(CC); + } +} -// FIXME: Remove this when calling conventions cleaned up LLVM_READNONE -inline bool isKernel(CallingConv::ID CC) { +constexpr inline bool isKernel(CallingConv::ID CC) { switch (CC) { case CallingConv::AMDGPU_KERNEL: case CallingConv::SPIR_KERNEL: @@ -1343,6 +1389,23 @@ inline bool isKernel(CallingConv::ID CC) { } } +LLVM_READNONE +constexpr bool canGuaranteeTCO(CallingConv::ID CC) { + return CC == CallingConv::Fast; +} + +/// Return true if we might ever do TCO for calls with this calling convention. +LLVM_READNONE +constexpr bool mayTailCallThisCC(CallingConv::ID CC) { + switch (CC) { + case CallingConv::C: + case CallingConv::AMDGPU_Gfx: + return true; + default: + return canGuaranteeTCO(CC); + } +} + bool hasXNACK(const MCSubtargetInfo &STI); bool hasSRAMECC(const MCSubtargetInfo &STI); bool hasMIMG_R128(const MCSubtargetInfo &STI);